GB2101845A - Telecommunication exchange system - Google Patents

Abstract

An interface assembly uses a Signalling Interworking Subsystem (SIS) for signalling conversion between PCM junctions and the analogue exchange's junctions (OGJ and ICJ). It also has a controlling processor (System X Central Processor), a message transmission subsystem (MTS) via which control is exerted on the signalling interworking subsystem (SIS) at time slot 16 on a link therebetween, and an automatic announcement subsystem (AAS). The latter co-operates with the facilities assembly to provide verbal announcements to the subscribers when needed. One part, call processing handler subsystem (CPHS) of the Central Processor, is connected to a common bus (SECURE BUS) in the facilities assembly. The facilities assembly includes the common bus (SECURE BUS) plug its control means (Bus Control), to which all parts of the assembly are connected, as are CPHS, and the control means (MCU, OPU) of the analogue exchange. It also includes subsystems (MPGRS, RRRS, AARS, DCRS) for providing the facilities. <IMAGE>

Description

SPECIFICATION Telecommunication exchange system This invention relates to automatictelecommunica- tion exchange systems.

The telecommunications network includes a number of processor-controlled analogue telephone exchanges which are interconnected in the main by analogue junctions. In addition processor-controlled digital telephone exchanges are being installed, and it is desirable for these to be able to interwork with the existing analogue exchanges. With digital exchanges and digital inter-exchange connections the number and variety of facilities which can be provided for the subscribers is increased as compared with what is possible for an analogue exchange. Hence we find that the two varieties of exchange would be providing different levels of service to the subscribers.As many of the processorcontrolled analogue exchanges are quite new, and as more of them are being installed, it becomes desirable to be able to offer these additional facilities to all subscribers whether they are connected to an analogue or to a digital processor-controlled exchange.

According to the invention there is provided an automatic telecommunication exchange system, which includes an analogue telephone exchange, an interface assembly for connecting the exchange to a digital telecommunications network, and a facilities assembly for providing additional communications facilities to the subscribers served by the analogue exchange, wherein the interface assembly included analogue-to-digital conversion means so that calls outgoing from the exchange can be set up over digital (PCM) inter-exchange junctions, digital-toanalogue conversion means so that calls incoming to the analogue exchange from digital (PCM) interexchange junctions can be handled, signalling equipment for dealing with inter-exchange signalling and/or signalling between the interface assembly and the analogue exchange, and processing means separate from the control means of the analogue exchange for controlling the interface assembly, and wherein the facilities assembly includes a common bus system to which the analogue exchange and its control means and the interface assembly and its processing means are connected, special purpose circuit units appropriate to the facilities to be provided which are coupled to the common bus system, and a controlling circuit associated with said common bus systems.

In the context of the British telecommunications network the processor-controlled analogue exchanges installed and to be installed are assumed to be of the now well-known TXE4 and TXE4A types, and the digital exchanges are System X exchanges.

However, it will be clear that although our invention is described in the contect of TXE4A and System X, it is not so limited.

An embodiment of the invention will now be described with reference to the accompanying drawings, in which: Figure 1 is a simplified schematic diagram of a processor-controlled analogue exchange of the TXE4Atype, modified and enhanced in accordance with the principles of the present invention.

Figure 2 shows the inter-relation of a common bus, which forms part of the system of Figure land its associated elements.

Figure 3 shows one of the common bus interfaces used in the arrangement of Figure 2.

Figure 4 shows a common bus controller and allotter, such as used in the arrangement of Figure 2.

Figure 5 shows common bus controller-allotter arrangements, as used in the arrangement of Figure 2.

Figures 6 and 7 show in block diagram form alternative versions of the unit SIS of Figure 1.

The switching network of the TXE4A exchange, like that of TXE4, embodies the sectionalisation principle, which is described in British Patent Specifications No. 989336 and No. 999945 (Associated Electrical Industries Ltd). However, as compared with the systems described in the above two Patent Specifications, TXE4 and TXE4A use a modified and improved switching network, which follows the principles enunciated in our British Patent Specification No. 1165526 (G. Harland et al 1-1), and system operation follows in general the principles set out in British Patent Specirication No. 1057218 (Standard Telephones and Cables Limited, Her Majesty's Postmaster-General and Automatic Telephone and Electric Company Limited).In TXE4Athe control arrangements are improved as compared with those described in No. 1057218 mainly by the use of modern microprocessors in the exchange's Main Control Units (MCU's).

Figure 1 shows the system in its basic essentials: there are three blocks, one of which is a TXE4A exchange, a second of which is an interface assembly formed in the present case by items of System X equipment, and a third of which is a facilities assembly.

The TXE4A block is not described in detail as the TXE4A system is now well-known. In this block OGJ and ICJ are outgoing and incoming junctions respectively, OPU is an operational processing unit, MCU is a main control unit, of which a TXE4A exchange has a number, SPU is a supervisory processing unit and SER is a supervisory electronics rack, which is associated with an SPU. The OPU, MCU and SPU form the processing means for TXE4A, and are not described in detail. They also, as can be seen from the drawing, communicate with the facilities assembly.

Now we consider the interface assembly, which provides the interface between the analogue exchange, in this case TXE4A, and the digital network, in this case System X. For convenience, this assembly uses System X standard units, modified if necessary for use in the interface assembly. PCM junctions incoming to and outgoing from the system of Figure 1 are connected to a signalling interworking sub-system SIS. This acts as an interface between the PCM junctions and analogue junction circuits connected as inlets to and outlets from the TXE4A switch network. The block SIS includes digital-to-analogue and analogue-to-digital conver sion circuitry, plus means to extract signalling from PCM bit streams and insert signalling into such bit streams (at time slot 16), as needed for the calls being dealt with, using an SIS-MTS link.It is controlled by a central processor, which co-operates with SIS both directly and via a message transmission sub-system MTS. This provides message-based signalling compatible with the digital network and digital exchanges.

The other elements of the interface assembly are as follows, all System X units in the present case: MCS Maintenance Control Subsystem AAS Automatic Announcement Subsystems used where pre-recorded speech announcements have to be made to the subscriber.

MSS Management Statistics Subsystem - responsible for collecting traffic statistics.

OCS Overload control subsystem, for detecting overload conditions and recording such conditions.

CAS Call accounting subsystem -this is an electronic arrangement which replaces the subscriber's meters normally used.

CPHS Call processing handler subsystem, which is an interface between the standard System X software and processor and the TXE4A control equipment. This provides basic call processing functions.

Most of the above elements are, as indicated above, System X units with little or no modification.

Where the digital system is other than System X the units to provide the corresponding functions may have to be specially designed. The unit CPHS, shown as associated with a System X-type Central Processor, has a number of functions, as follows: (a) Transfer of signalling messages occurring during call set-up from MCU, the main processing part of TXE4A, to MTS and AAS, for signalling where necessary to the digital system and for generating any audible announcement required.

(b) Transfer of line signalling messages from SIS to MTS.

(c) Transfer of messages relating to call set-up and supervision with access to additional facilities, between MCU, MTS, AAS and FRSS (facilities relay set subsystem - see below). Thus for each call, calling and called line identity are passed from the MCU to CPHS and CAS, plus the call's supervisory address.

The call state recording equipment provides information on the times of answer and of clear and CPHS identifies the call charging rate.

(d) Transfer of information from MCU and CSRS (Call State Recording Subsystem - see below) for call accounting purposes. This is appropriate because centralised "electronic" metering is used in preference to the more usual banks of individual subscriber's meters which has the merit of reducing space requirements.

(e) Supports supplementary subscriber services by providing data storage, e.g. for abbreviated dialling, alarm calls, etc.

(f) Passage of messages between MCS and TXE4A OPU for cyclic store and routiner control. In TXE4A the cyclic stores, which are scanned in step with line scanning, contain data about the various subscriber's lines served.

The TXE4A software is modified in a number of respects, especially in the MCU, as follows: (i) To use common channel signalling where appropriate.

(ii) To provide calling line, called line, and supervisory address information for call accounting.

(iii) To access data tables in CPHS where needed to support supplementary services.

(iv) To set up additional serial trunking sequences in support of new services, and supervise facility relay sets. Serial trunking is used, inter alia, to connect the facility relay sets to a call, by connecting one or both lines involved in the call to a special relay set as if a new connection is set up through the switching network.

For outgoing calls, the MCU in use forthe call may select a route using common channel signalling. A TXE4A outgoing junction OGJ is selected in the normal way, it gives access to a PCM junction, the signalling via that junction is detected by SIS equipment for that junction, and translated by CPHS to common channel signalling messages to be sent by the MTS over channel 16 of the PCM junction. In the present system each of the PCM junctions conveys 32 channels, of which channel 0 is used for synchronisation and channel 16 for signalling in common channel manner. In the reverse direction, line signalling messages received over PCM junctions from remote exchanges are passed via MTS, CPHS, SIS and the selected OGJ to the appropriate MCU.Call routing information is sent directly from the MCU to MTS via CPHS, and not through the OGJ.

Signalling for incoming calls is handled in a similar way to that just described for outgoing calls, the initial calling message passing to the appropriate ICJ via SIS, whereafter the call is dealt with by an MCU taken into use in normal manner.

For signalling between two TXE4A exchanges, signalling can use the selected junction in normal manner, or common channel signalling may be used for routing and other messages, which provides fast call set up in such cases.

We now consider the facilities assembly: this includes a number of items: (a) FRSS, which is the Facilities Relay Set Sub scription, and embraces the next four items.

(b) MPGRS, which is the meter pulse generator relay set.

(c) RRRS, which is the register recall relay set.

(d) AARS, which is the automatic announcement relay set.

(e) DCRS, which is the dummy call relay set.

(f) CSRS, which is the call state recording subsystem, referred to above.

(g) Bus Control, which will be referred to when describing the following drawings.

When a call involves a subscriber with a class of service which does not allow register recall, the MCU involved refers as appropriate to additional data stores in the interface assembly's processor under the control of CPHS. This reference can involve input of data to CPHS as part of normal call procedure or as a request for a specific service facility. Again it could occur due to call origination using data stored in CPHS, e.g. abbreviated dialling, or by a serving request by a subscriber using the appropriate service code prefix. Data is recovered from the calling line or junction via the register in use for the call, and where appropriate the MCU seized for the call arranges the connection of an AARS to give the appropriate announcement to the subscriber, CPHS then controls the sending of announcements as needed.

If the call involves a subscriber with a register recall class of service, an RRRS is connected to the calling line, and retained forthe duration of the call.

The RRRS has three ports connectable to the switch network and a direct connection to the automatic announcement subsystem AARS. Two of these ports are used for the initial connection during call set up, and the third port is used to make calls when register recall is needed, e.g. hold for enquiry and transfer etc. Aspects of register recall as usable in TXE4 or TXE4A are described in some detail in our British Patent No. 1589161 (B. Patience-P.R. Dudley 14-2).

The basic principles of serial trunking as used in TXE4A generally as described in detail in British Patent No. 1123571 (Associated Electrical Industries Ltd).

The AARS referred to is used for such services as Reminder and Advice Duration and Charge, where the exchange has to originate calls. A call initiated by such a relay set is set up in the normal way under MCU control, and on answer the AARS provides an announcement from AAS. The DCRS generates locally-generated calling conditions for MCU -seizure in the normal way.

For the calls from coin collecting boxes and subscribers with private meters an MPGRS is connected to the calling line, the connected relay set generating meter pulses at a rate specified by CPHS.

A special class of service is allotted to subscribers needing meter pulses.

As already indicated, the various relay sets described from the FRSS, which also includes common equipment for the transfer of messages between the relay sets and other subsystems via the secure bus.

We now consider, with reference to Figure 2, the common bus interfaces (CBl's) and their arrangements with respect to the secure bus. It will be appreciated that Figure 2 is an expansion of that part of Figure 1 which relates to the facilities assembty.

The elements shown in Figure 2 form the means by which the MCU and OPU, CSRS, FRSS and CPHS exchange data. The bus can be a ten-bit parallel common highway with two lines to each interface.

Note that in the interests of system security the common bus is duplicated, Figure 2 showing COM MON BUS 1 and COMMON BUS 2. Thus all functions are duplicated, with a continuous check on the integrity of both levels, the system being operable with one level down. Overall control of bus access is handled by a Common Bus Controller (CBC), Figure 4, which is also responsible for routine and diagnostic checks of the CBl subsystem.

Where the bus is relatively long, or when a relatively large number of MCU's etc exist, the bus is in two or more sections, coupled by Bus Expander Interfaces, as shown. Such a bus expander interface is used to isolate and staticize the signals on the two sections of an expanded bus. It receives a signal from the Common Bus Controller, below, to identify the direction of transmission.

As can be seen from Figure 2, each device to be coupled to the bus has its own interface, which attends to such necessary functions as conversion of material for transmission to or from the format needed on the common bus, and in view of what has been said about these elements no detailed description of Figure 2 is considered necessary. Note that CPHS elements are in groups, also known as clusters.

A message to be conveyed over the common bus is headed by the addresses of the receiving and the transmitting devices, followed by the message type, the message itself, a redundancy check group and then the message end indicator. Messages have a maximum length of 32 bytes, so a message needing more than this is sent as two or more messages of up to 32 bytes. The receiving device identifies a "multi-message" from its message contents.

Figure 3 shows a typical common bus interface arrangement, and as shown uses a three-unit, in this case each unit is on a printed circuit card layout. The design is based on an eight-bit microprocessor 1 with a read only memory (ROM) 2, with capacity for 2K eight-bit words, a random access memory (RAM) 3, also with 2K eight bit word capacity, and FIFO's (First-in-first out buffers) 4, 5, 6,7. The three units which form the interface are connected via the processor's data/address bus and other control lines.

Unit 1, which is on Card 1, and includes the microprocessor 1, receives and transmits information from and to one security level of the common bus. Its inputs also include duplicated inputs from the common bus allotter CBA, which are compared by a comparator 10 to assess whether a level has failed. The unit also contains, as shown RAM 2, ROM 3, control logic 12, bus input check and select circuitry 13, and a FIFO 4for received data messages.

Unit 2, on Card 2, consists of transmitters and receiversforthe second security level, and a FIFO 14 for messages to be transmitted, plus its control logic 5.

Unit 3, on Card 3, contains a combination of two eight-bit parallel ports and sixteen input/output single-bit ports. The eight-bit ports are used for the input and output of parallel data, and the sixteen single bit ports are used to control the systems connected to the unit. Two of the eight bit parallel ports are used as a 16-bit programmable input/ output port, for providing communication to and from other sub-systems.

For such interfaces, the firmware is divided into the bus handling firmware, which is common to all interfaces, and the interface handling firmware, which is designed to suit the requirements of each individual subsystem.

The bus-handling firmware BHF deals with message transfer across the interface, and all "housekeeping" functions, including diagnostic reporting. It is written in a 2K x 8 bit EPROM (Eraseable Programmable Read Only Memory), the ROM 2, for instance, and can deal with the following: (a) transfer of single blocks of data of specific length and start address from memory to FIFO.

(b) transfer of single blocks of data from FIFO to any location in RAM on detection of an interrupt.

(c) indicate to the Interface Handling Firmware (IHF) that a message is available for processing.

(d) detect internally indicated faults and enter a self-check routine at the end of which the fault (if any) is indicated to the Common Bus Control (CBC), and either bypassed or corrected.

The Interface handling firmware (IHF) can be "tailored" to the needs of each interface, to perform message handling operations according to the subsystems to which the interface is connected. The MCU and CPHS-IHF are responsible for translating messages from a System X format to a format suitable for transmission on the internal highways of an MCU, or vice-versa.

The lHF of the Common Bus Controller (CBC), Figure 4, is different from that of the other interfaces as its function is to perform routine checks of the interfaces, and to respond to error flags from its associated priority logic.

As will be seen from Figure 4, the Common Bus Controller CBS, Cards 1 and 2, is similar to Cards 1 and 2 of Figure 3. In addition, the third card in Figure 3 is the Common Bus allotter.

The CBS controls access to the common bus; it polls each interface's requirements to send, giving each interface in turn an opportunity to send a message on the bus. Each CBl is allocated enough time to send a message, except that if no message is ready for sending, the next CBl is given access to the bus. The twenty CBl's provided have inputs to a set of buffers 20, one per CBI, whose contents, which indicate whether the CBl's have messages to send, are placed into the block EN, which also receives scan inputs from a counter 21 via a demultiplexer 22.

When EN detects that a CBl is "calling" it stops the counter 21 via the control unit 24 for long enough to send a message, and also sends a signal via buffers 25 to the calling CBl to acknowledge its "calling" signal. The message is then sent, and counter 21 resumes its count after the present message sending time. If there is no message to be sent, scanning, i.e.

counting by the counter 21, continues. The priority system is duplicated for security, and each can be interrogated by its associated controller lHF during routine maintenance. lfthere are more than twenty interfaces, an additional unit may be used to extend the scan to 40. There is a TXE4A timing input to a timing control unit 26 which operates on the control unit 24 to maintain operations properly in synchronism with the TXE4A exchange. Unit 26 is also connected, as shown, to the other CBA, if any, for synchronising, timing and bus expansion.

The Common Bus Controller also generates and directs routine messages to the other interfaces via the bus to maintain the security of the Common Bus Interface Subsystem (CBIS).

Figure 5 shows how two common bus controller/ allotter assemblies are interconnected, and it is felt that the arrangement, as annotated in the drawing, needs no specific description.

For calls between the TXE4A exchange and System X, the former's MCU is not usually connected when supervisory signals are sent or received.

Hence supervisory line signals have to be identified from the TXE4Ajunction signalling by the signalling interworking subsystem SIS, Figure 1. Two variants of this will be described with reference to Figures 6 and 7.

The version shown in Figure 6 is the simpler of the two versions, which does not have provision for metering over the junctions.

The processor in Figure 6 and the block MTS both appear in Figure 1. The arrangement of Figure 6 caters for one PCM junction, i.e. 30 channels, and is connected to a multiplexer-demultiplexer MUX, which has access to the processor via MTS. MUX has access to the analogue junctions, one of which is shown via a first signal conversion unit SCR. This has access via signal conversion electronics SCE to the two paths, one each way, to the Time Slot 16B block; this extracts the signalling which is conveyed over the PCM junction in time slot 16 for application to the processor. This responds to the signal as is appropriate.

The other version of SIS caters for 30 PCM junctions, i.e. 900 channels. As shown, the arrangement is similar to that of Figure 6, except that a larger amount of equipment is provided, as can be seen from Figure 7. The functions of the block ACCESS in Figure 6 are assumed by the time slot extraction unitsTSl6A. Note that TSl6A and the multiplexer/demultiplexer blocks MUX are duplicated in the interests of system security. Each such block MUX produces a 2 megabit data stream containing the signalling from the time slot 16's of the 30 PCM junctions. In this version of SIS there is provision for metering over the junctions.

The software used in the MCU's, which are the main processors for the analogue exchange (TXE4A) is modified to be able to handle the additional operations needed. Thus formatting of messages outgoing to the digital (System X) equipment is needed, and incoming messages have to be decoded and associated with the appropriate calls. In addition, some reconfiguration of the "executive" portions of the software is needed for transmitting messages to be bus handling firmware - in the Bus Control block of Figure 1 - and the acceptance of messages therefrom.

The common channel signalling functions call for by-pass of normal digit reception and outpulsing programs, with dialled digit transfer undertaken by messages to and from the "digital" processor in the System X equipment block. In addition, the information needed by CPHS is provided using CCITT No 7 signalling.

In addition, some extension of the portions of the MCU software which deal with serial trunking is included as the associated with the digital equipment calls for some additional serial trunking sequencies. For a description ofthefundamentals of the serial trunking sequencies as used in TXE4 and TXE4A reference is directed to the above-mentioned British Patent No. 1123571 (AEI).

Where itemized billing is needed, the MCU in use for a call causes a record to be set up in the digital (System X) equipment, which record contains calling and called line numbers, and the identities of the supervisory circuits (bridge links, through links, etc).

The software used in the digital equipment needs less alteration and additions than that of the analogue exchange; in fact the main addition is to provide for interworking with the common bus.

Claims (4)

1. An automatic telecommunication exchange system, which includes an analogue telephone exchange, an interface assembly for connecting the exchange to a digital telecommunications network, and a facilities assembly for providing additional communications facilities to the subscribers served by the analogue exchange, wherein the interface assembly includes analogue-to-digital conversion means so that calls outgoing from the exchange can be set up over digital (PCM) inter-exchange junctions, digital-to-analogue conversion means so that calls incoming to the analogue exchange from digital (PCM) inter-exchange junctions can be handled, signalling equipment for dealing with interexchange signalling and/or signalling between the interface assembly and the analogue exchange, and processing means separate from the control means of the analogue exchange for controlling the interface assembly, and wherein the facilities assembly includes a common bus system to which the analogue exchange and its control means and the interface assembly and its processing means are connected, special purpose circuit units appropriate to the facilities to be provided which are coupled to the common bus system, and a controlling circuit associated with said common bus system.

2. A system as claimed in claim 1, and wherein the controlling circuit for the facilities assembly includes a microprocessor by which the operations using the common bus are controlled, said operations including the allotment of the bus to the facilities circuits and other units as required.

3. A system as claimed in claim 2, and wherein the facilities circuits and other units connectable to the common bus are each connected thereto via an interface which includes a microprocessor.

4. An automatic telecommunications exchange system, substantially as described with reference to Figures 1 to 6 orto Figures 1 to 5 and 7 ofthe accompanying drawings.