GB2095494A - Interface circuit - Google Patents

Abstract

An interface circuit for connecting a telephone exchange line to a subscriber's line interface circuit is described which permits the transmission of signals differentially appearing on the exchange line to be transmitted to the interface circuit but which is arranged to float with common mode voltages appearing on the exchange line. The circuit proposed uses two parallel current circuits carrying equal, controlled currents with series transistors to which the input voltage from the exchange line is differentially applied so that the differential voltage appears across a resistor joining corresponding points on the parallel circuits and an output current is derived from the parallel circuits in dependence on the current through the resistors. <IMAGE>

Description

SPECIFICATION Interface circuit This invention relates to interface circuits for connecting, for example, the circuits of a telephone exchange to the lines connected to the subscriber's instruments.

A difficulty which occurs in the interfacing of the connection of subscriber's lines to a telephone exchange is that substantial common mode voltages can be induced into the subscriber's line. With a conventional semiconductor SLIC which presents a low impedance to common signals it is necessary to ensure that the interface is capable of tolerating a relatively large common mode current resulting from the induced signal. In addition the interface must not transmit the common mode signal to the exchange.

According to the invention an interface circuit includes an output stage having connections for balanced signal lines, a floating power supply for the output stage, low voltage circuitry and a floating interface stage connecting the low voltage circuitry to the output stage, wherein the floating interface stage operates to effect a shift of voltage level between a differential signal in the output stage and an unbalanced signal referenced to a fixed voltage usable in or produced by the low voltage circuitry.

Although the invention is of particular importance in connection with subscriber lines at a telephone exchange, it will be appreciated that it is applicable to any circuit in which a balanced input or output signal is liable to common mode interference, the floating interface stage providing isolation of the low voltage circuitry from the common mode signals. Probably two floating interface stages will be required for signal transmission in both directions.

A particular form of floating interface stage comprises two parallel circuits carrying equal controlled currents with series transistors to which the input voltage to the stage is differentially applied so that the voltage appears across a resistor joining corresponding points in the parallel circuits, and means for deriving one or more output currents from the parallel circuits dependent on the current through the resistor. The output current or currents may be produced by "mirroring" the current in one circuit into the other circuit, so that twice the current through the resistor appears as the output current or the combined output currents.

In order that the invention may be fully understood and readily carried into effect an example of it will now be described with reference to the accompanying drawings, of which: Figure 1 shows a circuit for testing the response of a subscriber's line interface circuit (SLIC) to common mode interference signals; Figure 2 shows in block diagrammatic form a subscriber's line interface circuit according to the invention, and its connections to the rest of a telephone exchange, and Figure 3 shows the circuit of the interface stage between the output stage and the low voltage circuitry of Fig. 2.

A subscriber's line interface circuit (SLIC) must be able to absorb relatively large longitudinal or common mode currents resulting from signals induced in the subscriber's line without generating a large differential component at the port of the circuit. A suitable test circuit for evaluating this rejection is shown in Fig. 1 in which a common mode signal of voltage V, is applied via respective equai (300 Gb) resistors to the terminals A and B of a two-wire port of a SLIC, and the value V2 of the apparent differential signal is measured between A and B.A measure of this rejection is designated the L1 performance and is given by: longitudinal signal rejection = 20

in dBs Conventional semiconductor S.L.I.C. designs return poor L1 test performance because their 2wire port output terminals, designated A and B in Fig. 1 present a relatively low impedance to ground and consequently they must be capable of tolerating a common mode current flowing as a direct result of the common mode driving signal V,. This imposes two main constraints on a conventional S.L.l.C. design utilising a direct semiconductor interface to the 2 wire phone line.

(i) the design of the A and B wire amplifiers must take into account the increased power dissipation to the common mode current flowing in them, and (ii) to achieve good L1 test performance there are constraints on the degree of gain and component balance between the A and B wire amplifiers and any associated feedback loop in order not to generate a significant differential component, V2 in Fig. 1 from the common mode drive signal V1.

The invention seeks to overcome this difficulty by allowing the output stage including the amplifiers and other parts connected to the wires to float relative to ground, though not, of course, relative to each other since a balanced output signal is to be produced and a balanced input signal to be received. This requires that the amplifiers be energised by a floating power supply and that the low voltage circuits should be isolated from the amplifiers and other parts by a floating interface stage. The interface stage serves to shift the level between a differential signal at the output stage and an unbalanced signal referenced to a fixed voltage, such as ground, usable in or produced by the low voltage circuitry.The interface stage (or stages) must be bi-directional since not only are signals to be applied to the output amplifiers from the low voltage circuitry but also signals incoming from the line are to be applied to the low voltage circuitry. The circuit of one example of the interface stage is shown in Fig. 3 and will be described later.

Referring now to Fig. 2, the example of a subscriber's line interface circuit shown has an output stage 10 containing the line amplifiers and connected to the two wires 11 and 1 2 of a two-wire subscriber's line. The stage 10 is energised by a floating power supply 1 3 producing an output voltage Vs from the exchange battery (not shown) to which it is connected by conductors 14. The positive terminal of the power supply 1 3 is grounded through a high value resistor 1 5. An interface stage 16 is connected to the output stage 10 by a conductor 1 7 and to low voltage circuitry 18 by a conductor 1 9. The low voltage circuitry is connected to the remainder of the exchange by a 4-wire line represented by input and output channels 20 and 21.The low voltage circuitry 18 has for example, + 5 and - 5 volt supplies which means that the signals in the low voltage circuitry must lie between + 5 and - 5 volts. The supplies for the interface stage 1 6 on the other hand, must be of sufficiently large positive and negative voltages that the stage can perform the requisite level shifting even when the highest voltage common mode signal occurs; it should be borne in mind that the common mode signal is just as likely to be negative as positive.

The resistor 15, through which the positive terminal of the floating power supply 1 3 is connected to ground, is provided to tend to hold that terminal near ground potential except when a common mode signal occurs. The value of the resistor 1 5 should be low enough to ensure a rapid return to ground potential of the power supply positive terminal, but high enough to limit the common mode signal current, which will flow through it, to a value which will not damage the output stage.

The circuit Fig. 2 operates as follows. In the presence of a common mode signal at the 2 wire port 11, 12 of magnitude VCM, and A and B wire amplifier outputs are made to follow the common mode signal by employing the floating power supply unit 1 3 which is referenced to ground through a high value resistor 1 5. The common mode signal will then be developed across the resistor 1 5 with respect to ground, and the common mode current flowing in the output amplifiers will be limited to the small current flowing in the resistor 1 5 needed to establish across it the common mode voltage VCM.

Unwanted power dissipation in the output stage due to the flow of large common mode currents has thus been removed. Likewise, by isolating the output stage 10 from the ground referenced common mode signal through the common mode signal developed across the resistor 15, longitudinal signal rejection performance (L, test) of the SLIC is vastly superior to that obtained when operating the output stage in a non-floating mode.

To enable bi-directional signal communication between the floating output stage 10 and the low voltage circuitry 1 8 in the presence of the common mode signal at the 2 wire port, the interface stage 1 6 is employed whose supply voltages are increased by an amount necessary to handle the common mode voltage swing developed across the resistor 1 5. Two interface stages may be required to transmit signals in both directions between the output stage and the low voltage circuitry.

The circuit of one example of the interface stage 1 8 is shown in Fig. 3. The stage consists of two parallel circuits connected between the positive and the negative supply terminals 30 and 31. The first parallel circuit contains a resistor 32, the emitter-collector paths of transistors Q6, Q3 and Q1, and a resistor 33 in series. The second parallel circuit consists a resistor 34, the emitter-collector paths of transistors Q7, 05, 04 and Q2, and a resistor 35 in series. The transistors Q1, Q2, Q3 and Q4 are of n-p-n type and the transistors Q5, Q6 and 07 are of p-n-p type. The emitter-collector paths of the transistors are all connected conventionally with respect to the power supply polarity. Two input terminals 36 and 37, for connection to the output stage 10 (Fig. 2), are connected respectively to the base electrodes of the transistors Q3 and Q4. A terminal 38, for connection to the low voltage circuitry 1 8 (Fig. 2) is connected to the collector electrodes of the transistors 04 and Q5. The bases of transistors Q1 and Q2 are connected together and to a common bias voltage. The emitters of transistors Q3 and Q4 are joined through a resistor 39 of value R. The base of transistor OS is connected directly to the collectors of transistors Q3 and Q6. The collector of the transistor Q7 is connected directly to its base and is the base of transistor Q6.

The interface stage is of the transconductance form with an approximate g, given by L 2 IgmI= - Vin R where i, is the current fed to the terminal 38 (i.e. the low voltage circuitry 18) and Vjn is the voltage between terminals 36 and 37.

Hence

where Vout is the voltage at the terminal 38 and RWoad is the impedance of the low voltage circuitry 1 8. The transistors Q1 and Q2 act as constant current generators, the current being determined by the bias voltage on their bases which is fixed with respect to the minus (-) supply terminal 31, their emitter resistors 33 and 35 and the base-emitter voltages. Equal currents flow through the collectors of Q1 and Q2. The transistors Q5, Q6, Q7 form a 3 transistor current mirror reflecting the collector current of the transistor Q3 into collector circuit of the transistor Q4. When V, is set to zero (and assuming no offset errors) the current i, into the load is zero and there is consequently no output voltage generated.When Vjn is non-zero, however, the voltage Vjn appears across the resistor 39 (R), the transistors 03 and 04 operating as emitter followers, so that a current V R flows through the resistor 39. This current flow unbalances the collector currents of the transistor Q3 and Q4 by 2 Vjn R with the result that the "mirrored" current at the collector of transistor OS no longer matches the collector current of the transistor Q4 and the difference between the currents 2 Vin R is produced as the output current i, of the stage.

The circuit of Fig. 3 may also be used in reverse to interface the low voltage circuitry to the line. Clearly, the conductivity types of the transistors and the polarities of the supply terminals may be reversed, and other types of current source and current mirror could be used.

It will be appreciated that the invention could be used other than as a telephone subscriber's line interface and modifications could be made to the operating voltages and component values to suit the particular application of the circuit.

Claims (6)

1. An interface circuit including an output stage having connections for balanced signal lines, a floating power supply for the output stage, low voltage circuitry and a floating interface stage connecting the low voltage circuitry to the output stage, wherein the floating interface stage operates to effect a shift of voltage level between a differential signal in the output stage and an unbalanced signal referenced to a fixed voltage usable in or produced by the low voltage circuitry.

2. A circuit according to claim 1 wherein the fixed voltage to which the unbalanced signal usable in or produced by the low voltage circuitry is referenced is ground.

3. A circuit according to claim 1 or 2, wherein the floating interface stage includes a first stage which converts a differential signal received by the output stage from the line into an unbalanced signal referenced to the fixed voltage usable by the low voltage circuitry, and a second stage which converts an unbalanced signal referenced to the fixed voltage and produced by the low voltage circuitry into a differential drive signal for line amplifiers in the output stage.

4. A circuit according to claim 3 wherein each floating interface stage comprises two parallel circuits carrying equal controlled currents with series transistors to which the input voltage to the stage is differentially applied so that the voltage appears across a resistor joining corresponding points in the parallel circuits and means for deriving one or more output currents from the parallel circuits dependent on the current through the resistor.

5. A circuit according to claim 4 wherein the output current or currents is or are produced by means of a current mirror which reproduces the current flowing in one of the parallel circuits in the other of the parallel circuits, so that twice the current flowing through the resistor appears as the output current or the combined output currents.

6. An interface circuit substantially as described herein with reference to Figs. 2 and 3 of the accompanying drawings.