GB2095040A - Method of producing printed circuits - Google Patents
Method of producing printed circuits Download PDFInfo
- Publication number
- GB2095040A GB2095040A GB8207926A GB8207926A GB2095040A GB 2095040 A GB2095040 A GB 2095040A GB 8207926 A GB8207926 A GB 8207926A GB 8207926 A GB8207926 A GB 8207926A GB 2095040 A GB2095040 A GB 2095040A
- Authority
- GB
- United Kingdom
- Prior art keywords
- copper
- bores
- connecting surfaces
- conductive pattern
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
- H05K3/243—Reinforcing the conductive pattern characterised by selective plating, e.g. for finish plating of pads
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
- H05K3/428—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in substrates having a metal pattern
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/04—Soldering or other types of metallurgic bonding
- H05K2203/043—Reflowing of solder coated conductors, not during connection of components, e.g. reflowing solder paste
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/05—Patterning and lithography; Masks; Details of resist
- H05K2203/0502—Patterning and lithography
- H05K2203/0505—Double exposure of the same photosensitive layer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/05—Patterning and lithography; Masks; Details of resist
- H05K2203/0502—Patterning and lithography
- H05K2203/054—Continuous temporary metal layer over resist, e.g. for selective electroplating
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/05—Patterning and lithography; Masks; Details of resist
- H05K2203/0562—Details of resist
- H05K2203/0574—Stacked resist layers used for different processes
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0017—Etching of the substrate by chemical or physical means
- H05K3/0023—Etching of the substrate by chemical or physical means by exposure and development of a photosensitive insulating layer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3452—Solder masks
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
- H05K3/3473—Plating of solder
Abstract
A method of producing printed circuits in copper with part coppered and part tinned connecting surfaces and bores comprises etching the conductive pattern from the copper coating (2) of a base material (1), applying a layer of copper (8) to the base material as supply for auxiliary current, part coppering and part tinning the connecting surfaces and bores (4, 5), removing the copper layer (8) and then protecting the conductive pattern from corrosion by means of a protective layer. <IMAGE>
Description
SPECIFICATION
Method of producing printed circuits
The invention relates to a method of producing printed circuits with copper having part copper and part tinned connection surfaces and bores.
Progressive miniaturisation of the discrete components and, the increasing degree of integration of integrated circuits makes new demands on wiring in the form of printed circuits. Despite the fact that the subtractive technique has been perfected, it is no longer possible to meet these demands with existing means. Up to now it has not been possible to achieve geometries of greater than or equal to 50 jurn in mass production using additive techniques, semi-additive techniques, PDR and photo-additive techniques. Foreign bodies such as dust, moisture in the air, temperature, the properties of the specific base materials and solid resistant foils, scumming effects, traces of resist material, electrolytic effects etc., are the cause of this.For cost reasons and because of the fact that the systems can barely be repaired, the use of multi layer systems is limited.
The invention seeks to provide a method which is able to fulfill the highest requirements and also makes it possible to produce conductors in widths of 50 Mm upwards without any restriction and in thicknesses of 15 um, 70 um to 175 Mm and to provide for spacing between conductors of 50 ,um upwards also without restriction, at low cost.
According to the invention, there is provided a method of producing printed circuits in copper with coppered and tinned connecting surfaces and bores comprising etching the structure of a conductive pattern from a copper coating on a base material, applying a copper layer to the base material for supply of auxiliary current, coppering and tinning the connecting surfaces and bores, removing the copper layer for auxiliary current supply and protecting the copper conductive pattern from corrosion by application of a protective layer.
The protective layer preferably comprises photo polymer epoxy resin.
In one embodiment of the invention, the first step consists of etching the structure of the conductive pattern out of the coating of the base material. If a positively acting liquid resist material is used having a resolution capacity of approximately 1 4m, then the effect of dust is minimal. By choosing a layer thickness for the copper coating of the base material it is possible to fix the thickness of the conductors. Since there is no electrolytic deposition on the conductors, the disruptive effects of subtractive techniques and semi additive techniques are avoided.
Auxiliary current supply is required in order to partially copperise and tin contact surfaces and bores. This auxiliary current supply is applied over the entire area and also comprises the pre metalization of the bores. The fact that the auxiliary current supply is resistant to bonding on the base material exposed by etching and has a value of only approximately 2 kp/inch, is not a problem since it is etched away again. The auxiliary current supply is removed by differential etching after partial copperisation of 30 ym and tinning of 8 #m to 20 ,um depending on the technique used. In order to prevent differential etching, the first etching mask is preferably left on the copper conductors and merely coppered over.
Of course a second photo or screen printed mask is necessary for partial copperisation and tinning but this is not critical because of the relatively large geometries of the connecting surfaces and bores.
The copper conductors may be protected from corrosion and mechanical damage. Since the tolerances of the conventional screen printing method are approximately 0.2 mm with twocomponent lacquers, a photo polymer epoxy resin may be used, hardened thermally at 13500 after exposure and developing using its hardener additives. The tolerances of this method are 30 ym. The resistance to bonding with copper is good.
The following schedule method steps relate to one example of the method according to the invention.
1. Making a blank for base material having a suitable coating layer thickness.
2. Drilling holes with the aid of a CNCcontrolled drilling machine.
3. Deburring and fine polishing.
4. Applying the positively acting liquid resist lacquer with an inner layer thickness of approximately 8 ,um by a casting process.
5. Exposing and developing the conductive pattern.
6. Etching the structure of the conductive pattern preferably with CuCl2-etching solution, or alternatively an alkaline solution.
7. Exposing for the second time and developing the connecting surface and bores.
8. Applying the auxiliary current supply and premetalizating the bores with the aid of chemical and electrolytic copper deposition.
9. Polishing finely the premetalization.
10. Applying the second mask by means of photo or screen printing techniques.
1 1. Part copperising (30 ,t~m) and part tinning (8-20 yam).
12. Stripping in methylene chloride.
1 3. Etching differentially in an alkali with optical bleach in the case of lead tin.
14. Stripping the first photo mask in methylene chloride.
15. Melting in the case of lead-tin.
16. 1 6. Polishing the copper surfaces by fine polishing and drying.
17. Coating with a photopolymer epoxy resin by a casting process.
18. Exposing and developing with the aid of a mask film.
19. Hardening at 1 3500 for one hour.
20. Contoured cutting.
21. Final check.
The invention will now be described in greater detail, by way of example, with reference to the drawings, in which:
Figure 1 is a partially perspective view of a coated base material to which the method of the invention is applied,
Figure 2 is a view similar to figure 1 but showing a first stage of a method in accordance with the invention;
Figure 3 is a view similar to figure 1 but showing a second stage of a method in accordance with the invention;
Figure 4 is a view similar to figure 1 but showing a third stage of a method in accordance with the invention;
Figure 5 is a view similar to figure 1 but showing a fourth stage of a method in accordance with the invention;
Figure 6 is a view similar to figure 1 but showing a fifth stage of a method in accordance with the invention;;
Figure 7 is a view similar to figure 1 but showing a sixth stage of a method in accordance with the invention;
Figure 8 is a view similar to figure 1 but showing a seventh stage of a method in accordance with the invention;
Figure 9 is a view similar to figure 1 but showing an eighth stage of a method in accordance with the invention;
Figure 10 is a view similar to figure 1 but showing a ninth stage of a method in accordance with the invention; and
Figure 1 1 is a view similar to figure 1 but showing the finished printed circuit.
In accordance with Figure 1, in order to produce one embodiment of a printed circuit in accordance with the invention an insulating plate 1 which is coated on both sides with copper is used. The plate 1 thus has a copper layer 2 on one surface and a copper layer 3-on the opposite surface. The insulating plate 1, known as the base material is provided with suitable bores for producing an electrically conductive connection between certain points on one surface and certain points on the other surface. These bores extending from one surface to the other.
The bores are applied in accordance with geometry or dimensions of the base material either at the beginning of the process of manufacture or at some other stage in the manufacturing process. If the insulating plate has a small geometry then bores are produced before applying a layer of photo lacquer for further processing. This embodiment is shown in Figure 2 in which the insulating plate 1 which has two coatings 2, 3 is provided with two bores 4, 5.
Figure 2 of course only shows a portion of the whole of the base material; in fact there are usually substantially more than the two bores shown.
According to Figure 3, a photo lacquer layer 6, 7 is applied to both sides of the insulating plate 1 which has two coatings 2, 3 and is provided with the bores 4, 5. The photo lacquer layers 6 and 7
are exposed and developed in structured form in
order to produce a desired conductive pattern and
a photo lacquer mask is provided in accordance
with Figure 4 with the desired conductor
structure. The copper layers 2, 3 are etched
away, with the exception of those points at which the photo lacquer is located. This stage is shown
in Figure 5 in which only the conductive pattern 2, 3 with its covering layer 6, 7 comprising photo
lacquer and the bores 4, 5 are left on the insulating plate 1.
Certain areas of the conductor paths are intended to be thickened by metal, i.e. the connecting areas and the bores. The remaining parts of the positively acting photo lacquer layers are structured for a second time in order to achieve this. The photo lacquer layers 6, 7 which are again structured are shown in Fig. 6 in which the photo lacquer layer is removed by renewed structuring in the region of the bores 4, 5. Since an electrolytic deposition takes place next, which serves to strengthen the connection areas and to apply metal to the bores, current supply is necessary. A copper layer 8, 9 is applied to both sides of the arrangement of Figure 6, as shown in
Figure 7, this copper layer 8, 9 at the same time serving as a premetalization layer for the bores and the connecting areas. The thickness of these copper layers (8, 9) is preferably smaller than 10 rum.
In order to restrict the copper layer 8, 9 to the areas at which the copper covering is required a second mask layer 10, 1 1 is applied to the arrangement of Fig. 7, as shown in Figure 8, on both surfaces. This second layer 10, 1 1 is structured by exposure and developing in the desired manner. In the electrolytic reinforcement, in accordance with Figure 9, copper 12 and then tin 13 is deposited in the orifices in the mask layers 10, 1 1 at the exposed connecting areas and in the bores. The deposited layers 12, 13 comprise an approximately 30 ,um thick copper layer 12 and a tin layer 13 which is thinner than 20 cm.
In accordance with Figure 10 the second mask 10, 1 1 and the auxiliary current supply 8, 9 is then removed. The second mask 10, 1 1 is preferably stripped to achieve this and differential etching is carried out in order to remove the current supply 8, 9. The first mask 6, 7 is stripped away from the conductors 2, 3.
If tinning comprises lead-tin then it is preferably molten. If oxidation of the conductors comprising copper occurs during melting, then the resultant copper oxide layer is removed and this is achieved, for example, by a polishing process. In order to protect the copper conductors from corrosion, the conductors 2, 3 are preferably embedded in a plastics layer 14 in accordance with Figure 11. The plastics layer 14 preferably comprises a photopolymer epoxy resin which is removed in the region of the bores and connecting areas in order to facilitate subsequent soldering. After the plastics layer 14 has been structured, the epoxy resin is hardened thermally as a two-component system. The insulating plate 1 is then cut out and tested.
Claims (14)
1. A method of producing printed circuits in copper with coppered and tinned connecting surfaces and bores comprising etching the structure of a conductive pattern from a copper coating on a base material, applying a copper layer to the base material for supply of auxiliary current, coppering and tinning the connecting surfaces and bores, removing the copper layer for auxiliary current supply and protecting the copper conductive pattern from corrosion by application of a protective layer.
2. A method as claimed in claim 1; wherein the coppering and tinning of the connecting surfaces and bores is carried out by a photo lacquering technique.
3. A method as claimed in claim 1 or 2, wherein the copper layer for auxiliary current supply is removed by differential etching.
4. A method as claimed in claim 1, 2 or 3, wherein the copper conductive pattern is protected from corrosion by a polymer epoxy resin having optical properties.
5. A method as claimed in any one of claims 1 to 4 wherein the bores are produced after etching the structure of the conductive pattern in the case of rough geometries and before etching the structure of the conductive pattern in the case of precise geometries.
6. A method as claimed in any one of claims 1 to 5, wherein a first photo polymer mask is used for etching the structure of said conductive pattern.
7. A method as claimed in claim 6, wherein the first polymer mask operates positively, is exposed several times and can be developed.
8. A method as claimed in claim 6 or 7 wherein said connecting surfaces and bores are uncovered by partial secondary exposure and development of the photo lacquer after the structure of the conductive pattern has been etched while the first photo polymer mask is maintained on the copper conductors as a barrier layer to differential etching.
9. A method as claimed in any one of claims 6 to 8 wherein the copper layer for the auxiliary current supply is applied chemically and electrolytically and the first photo polymer mask covers the copper conductors and the connecting surfaces and bores are precoppered.
10. A method as claimed in claim 9 wherein a second photo polymer mask or a mask produced by screen printing is used as an electrolyte resistant layer for part coppering and part tinning the connecting surfaces and bores.
1 A method as claimed in claim 10, wherein the second mask is removed after part coppering and part tinning of the connecting surfaces and bores, the copper layer for said auxiliary current is etched away by differential etching, the first photopolymer mask on the copper conductors and the tinning on the connecting surfaces and bores preventing etching from attacking these surfaces and therefore maintaining the original precision of the structure.
12. A method as claimed in any one of claims 1 to 11, wherein a photo polymer epoxy resin is applied by casting in order to protect the conductors, the resin being exposed through the film and being hardened thermally once the connecting surfaces and bores have been fully uncovered.
13. A method as claimed in any one of claims
1 to 12, wherein the part tinning process consists of mirror finished tin, lead-tin or molten lead-tin.
14. A method of producing printed circuits in copper substantially as described herein with reference to the drawings.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19813110528 DE3110528A1 (en) | 1981-03-18 | 1981-03-18 | METHOD FOR PRODUCING PRINTED CIRCUITS |
Publications (1)
Publication Number | Publication Date |
---|---|
GB2095040A true GB2095040A (en) | 1982-09-22 |
Family
ID=6127622
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB8207926A Withdrawn GB2095040A (en) | 1981-03-18 | 1982-03-18 | Method of producing printed circuits |
Country Status (3)
Country | Link |
---|---|
DE (1) | DE3110528A1 (en) |
FR (1) | FR2502444A1 (en) |
GB (1) | GB2095040A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0189975A1 (en) * | 1985-01-15 | 1986-08-06 | Prestwick Circuits Limited | Manufacture of printed circuit boards |
EP0312607A1 (en) * | 1987-04-28 | 1989-04-26 | Fanuc Ltd. | Power circuit board and manufacturing method |
US5665525A (en) * | 1990-10-30 | 1997-09-09 | Nokia Mobile Phones Ltd. | Method for producing printed circuit boards |
EP1381260A1 (en) * | 2002-07-11 | 2004-01-14 | Ultratera Corporation | Method of plating connecting layers on a conductor pattern of a printed circuit board (PCB) |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE1142926B (en) * | 1961-11-15 | 1963-01-31 | Telefunken Patent | Process for the manufacture of printed circuit boards |
DE1206976B (en) * | 1963-09-19 | 1965-12-16 | Siemens Ag | Process for producing printed circuits according to the build-up method |
US3475284A (en) * | 1966-04-18 | 1969-10-28 | Friden Inc | Manufacture of electric circuit modules |
DE1690152B1 (en) * | 1968-03-07 | 1971-04-22 | Siemens Ag | Process for the production of printed circuit boards provided with finished configurations |
BE758490A (en) * | 1969-11-05 | 1971-05-05 | Int Standard Electric Corp | IMPROVEMENT OF PRINTED CIRCUIT PLATES |
GB1409737A (en) * | 1972-09-29 | 1975-10-15 | Exacta Circuits Ltd | Through-hole plated printed circuits |
GB1410780A (en) * | 1972-09-29 | 1975-10-22 | Exacta Circuits Ltd | Through-hole plated printed circuits |
US4104111A (en) * | 1977-08-03 | 1978-08-01 | Mack Robert L | Process for manufacturing printed circuit boards |
CA1054259A (en) * | 1977-10-14 | 1979-05-08 | John A. Galko | Printed circuit board carrying protective mask having improved adhesion |
-
1981
- 1981-03-18 DE DE19813110528 patent/DE3110528A1/en not_active Ceased
-
1982
- 1982-03-18 GB GB8207926A patent/GB2095040A/en not_active Withdrawn
- 1982-03-18 FR FR8204631A patent/FR2502444A1/en not_active Withdrawn
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0189975A1 (en) * | 1985-01-15 | 1986-08-06 | Prestwick Circuits Limited | Manufacture of printed circuit boards |
EP0312607A1 (en) * | 1987-04-28 | 1989-04-26 | Fanuc Ltd. | Power circuit board and manufacturing method |
EP0312607A4 (en) * | 1987-04-28 | 1990-09-26 | Fanuc Ltd | Power circuit board and manufacturing method |
US5665525A (en) * | 1990-10-30 | 1997-09-09 | Nokia Mobile Phones Ltd. | Method for producing printed circuit boards |
EP1381260A1 (en) * | 2002-07-11 | 2004-01-14 | Ultratera Corporation | Method of plating connecting layers on a conductor pattern of a printed circuit board (PCB) |
Also Published As
Publication number | Publication date |
---|---|
FR2502444A1 (en) | 1982-09-24 |
DE3110528A1 (en) | 1982-10-07 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP0457501B1 (en) | Method of manufacturing a multilayer wiring board | |
US5160579A (en) | Process for manufacturing printed circuit employing selective provision of solderable coating | |
US4810332A (en) | Method of making an electrical multilayer copper interconnect | |
US4629681A (en) | Method of manufacturing multilayer circuit board | |
US4643798A (en) | Composite and circuit board having conductive layer on resin layer and method of manufacturing | |
US5207865A (en) | Multilayer structure and method for fabricating the same | |
US5985521A (en) | Method for forming electrically conductive layers on chip carrier substrates having through holes or via holes | |
GB2137421A (en) | Printed circuits | |
EP0483979B1 (en) | Method for producing printed circuit boards | |
US5776662A (en) | Method for fabricating a chip carrier with migration barrier, and resulating chip carrier | |
US3745094A (en) | Two resist method for printed circuit structure | |
JPS59197139A (en) | Method of treating integrated circuit | |
US4525246A (en) | Making solderable printed circuit boards | |
WO1990001251A1 (en) | Electrical circuits | |
GB2095040A (en) | Method of producing printed circuits | |
US6641983B1 (en) | Method for forming exposed portion of circuit pattern in printed circuit board | |
US6998339B2 (en) | Method of forming conductor wiring pattern | |
JPS58186994A (en) | Method of producing printed circuit board | |
US4490457A (en) | Cold/dry substrate treatment technique which improves photolithographic limits of resolution and exposure tolerance | |
EP0095256B1 (en) | Method of making printed circuits | |
US5980721A (en) | Fabrication method for double metallic resist printed circuit boards | |
CA1051559A (en) | Process for the production of printed circuits with solder rejecting sub-zones | |
KR100403761B1 (en) | Fabrication method of high reliability printed circuit board | |
JPH05259614A (en) | Resin filling method for printed wiring board | |
JP2897365B2 (en) | Manufacturing method of wiring board |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |