GB2092824A - A Non-volatile Semiconductor Memory Device - Google Patents
A Non-volatile Semiconductor Memory Device Download PDFInfo
- Publication number
- GB2092824A GB2092824A GB8135384A GB8135384A GB2092824A GB 2092824 A GB2092824 A GB 2092824A GB 8135384 A GB8135384 A GB 8135384A GB 8135384 A GB8135384 A GB 8135384A GB 2092824 A GB2092824 A GB 2092824A
- Authority
- GB
- United Kingdom
- Prior art keywords
- insulating layer
- silicon nitride
- semiconductor memory
- layer
- memory device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 34
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 34
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims 3
- 238000010276 construction Methods 0.000 claims 1
- 230000015556 catabolic process Effects 0.000 description 12
- 238000002347 injection Methods 0.000 description 12
- 239000007924 injection Substances 0.000 description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 9
- 229910052814 silicon oxide Inorganic materials 0.000 description 9
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 229910052757 nitrogen Inorganic materials 0.000 description 3
- 229910021529 ammonia Inorganic materials 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 125000004433 nitrogen atom Chemical group N* 0.000 description 1
- 125000004430 oxygen atom Chemical group O* 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Non-Volatile Memory (AREA)
Abstract
A non-volatile semiconductor memory device includes a first polycrystalline silicon layer (8) which is to form a floating gate and a second polycrystalline silicon layer (6) which is to form a control gate. A silicon nitride insulating layer (71 is disposed between the first and second polycrystalline silicon layers. This silicon nitride insulating layer may be formed by converting part of the first polycrystalline silicon layer into silicon nitride. The insulating layer (9) under the floating gate (8) may also be of silicon nitride. <IMAGE>
Description
SPECIFICATION
A Non-volatile Semiconductor Memory Device
This invention relates to non-volatile semiconductor memory devices of the floating gate type.
According to the present invention there is provided a non-volatile semiconductor memory device including a first polycrystalline silicon layer which is to form a floating gate and a second polycrystalline silicon layer which is to form a control gate, and a silicon nitride insulating layer between said first and second polycrystalline silicon layer.
In the preferred embodiment the silicon nitride insulating layer is formed by converting part of said first polycrystalline silicon layer into silicon nitride.
The non-volatile semiconductor memory device may include a further silicon nitride insulating layer between a substrate and said first polycrystalline silicon layer. Preferably said further silicon nitride insulating layer is formed by converting part of the substrate with silicon nitride.
The invention will be explained, merely by way of example, in the accompanying drawings, in which:~
Figure 1 is a schematic view of a conventional non-volatile semiconductor memory device;
Figure 2 shows graphically the relationship between injection efficiency of a non-volatile semiconductor memory device and the thickness of an intermediate insulating layer thereof;
Figure 3 shows graphically the relationship between threshold voltage of an intermediate insulating layer of a non-volatile semiconductor memory device and the thickness of the intermediate insulating layer; and
Figure 4 shows graphically the relationship between breakdown voltage of an intermediate insulating layer of a non-volatile semiconductor memory device and the intermediate insulating layer.
A conventional non-volatile semiconductor memory device of the floating gate type is illustrated in Figure 1. This conventional nonvolatile semiconductor memory device has a Ptype substrate 1, an N-type diffusion layer 2, an oxide isolation layer 3, polycrystalline silicon 6 for forming a control gate, polycrystalline silicon 8 for forming a floating gate, a gate insulating layer 9, and an intermediate insulating layer 7.
Conventionally, an oxide layer on the substrate 1 is used as the gate insulating layer 9 and an oxide layer of the polycrystalline silicon 8 is used for the insulating layer 7.
It is desirable that non-volatile semiconductor memory devices have the following characteristics: (1) Relatively high injection efficiency of
electric charge into the floating gate.
(2) Relatively low threshold voltage in a first
state, i.e. before electric charge is injected
into the floating gate.
(3) Relatively high breakdown voltage of the
insulating layer 7.
These three characteristics make it possible to lower the supply voltage or current required when programming information into such a non-volatile semiconductor memory device to increase the speed of reading information from the nonvolatile semi-conductor memory device, and to improve the retention time of information.
Figures 2, 3 and 4 show graphically respectively the relationship between injection efficiency, threshold voltage and breakdown voltage of the insulating layer 7 and the thickness of the insulating layer. As shown in these Figures, the breakdown voltage tends to be the inverse of injection efficiency and threshold voltage with respect to the thickness of the insulating layer.
In other words, it is necessary to reduce the thickness of the insulating layer 7 in order to increase the injection efficiency and to lower the threshold voltage in the first state, i.e.
before electric charge is injected into the floating gate. But by reducing the thickness of the insulating layer 7, its breakdown voltage is reduced as shown in Figure 4 so that electric charge accumulated within the floating gate leaks for example, to the substrate 1 in a relatively short time. Therefore, in the conventional manufacturing process of a non-volatile semiconductor memory device the optimum thickness of the insulating layer is determined such that injection efficiency is reduced and injection voltage is increased.
It is highly desirable to increase injection efficiency because this reduces programming time, programming voltage and test time. The embodiment of the present invention described hereinafter overcomes the disadvantages of conventional non-volatile semiconductor memory devices, has a lower threshold voltage in the first state, i.e. before electric charge is injected into the floating gate, improved breakdown voltage and increased injection efficiency.
In this embodiment of the present invention, which will be described in relation to Figure 1 , the insulating layer 7 is formed by converting part of the polycrystalline silicon 8 which is to form the floating gate into silicon nitride thereby to form the insulating layer 7. As generally known, a silicon nitride insulating layer has both a breakdown voltage and a dielectric constant which are higher than that of a silicon oxide insulating layer of the same thickness. A silicon nitride insulating layer of the same thickness as a silicon oxide insulating layer has the following advantages over the latter:
(1) Breakdown voltage of the intermediate
layer is higher.
(2) Threshold voltage in the first stage is lower
because the dielectric constant is higher.
(3) Injection efficiency is higher because
capacitance between the control gate and
the floating gate is greater.
These advantages will now be explained in greater detail. The reason for the increased breakdown voltage of the silicon nitride insulating layer is related to the difference of binding energy between the oxygen atom and the nitrogen atom to the silicon atom, and further related to the difference in density between a silicon nitride insulating layer and a silicon oxide insulating layer. These differences have the result that the relatively small leakage current flowing through the silicon nitride insulating layer compared to the silicon oxide insulating layer is reduced, and breakdown voltage is increased.As for the threshold voltage in the first state, it will be readily appreciated that when comparing the case where the insulating layer 7 is formed of silicon oxide with the case where it is formed of silicon nitride, the capacitance between the control gate and the floating gate is increased in the latter case due to the fact that the silicon nitride insulating layer has a higher dielectric constant.If the same electric potential is applied to the control gate in the cases where silicon nitride is used for the insulating layer 7 and silicon oxide is used, the potential of the floating gate induced by the electric potential on the control gate is higher in the case of the silicon nitride insulating layer than in the case of the silicon oxide insulating layer, so that inversion of the transistor threshold voltage falls apparently under the electric potential of the control gate in the case of the silicon nitride insulating layer. From the foregoing, it can be said that when a silicon nitride insulating layer 7 is used, the potential of the floating gate is higher than that of the control gate and, as a result, it is possible to increase the kinetic energy in.the direction of the floating gate with respect to the substrate 1 when injecting electric charge into the floating gate.This explains why the use of a silicon nitride insulating layer increases injection efficiency.
Further, when determining the thickness of the silicon nitride insulating layer in order to obtain the same breakdown voltage achieved with a conventional silicon oxide insulating layer, there is the advantage that the threshold voltage in the first state is lower and injection efficiency is increased further. Various methods of converting silicon oxide into silicon nitride are known, for example, high-temperature treatment with nitrogen or ammonia or ionising nitrogen or ammonia and reacting it with polycrystalline silicon at high temperature. Any method can, however, be used in the present invention. It is also possible to form the gate oxide layer 9 under the floating gate as a silicon nitride layer formed by converting part of the substrate 1 into silicon nitride. This too has great advantages since it is expected that the breakdown voltage will be improved and the threshold voltage in the first state will be lower.
Claims (6)
1. A non-volatile semiconductor memory device including a first polycrystalline silicon layer which is to form a floating gate and a second polycrystalline silicon layer which is to form a control gate, and a silicon nitride insulating layer between said first and second polycrystalline silicon layer.
2. A non-volatile semiconductor memory device as claimed in claim 1 in which the silicon nitride insulating layer is formed by converting part of said first polycrystalline silicon layer into silicon nitride.
3. A non-volatile semiconductor memory device as claimed in claim 1 or 2 including a further silicon nitride insulating layer between a substrate and said first polycrystalline silicon layer.
4. A non-volatile semiconductor memory device as claimed in claim 3 in which said further silicon nitride insulating layer is formed by converting part of the substrate with silicon nitride.
5. A non-volatile semiconductor memory device substantially as herein described with reference to the drawings.
6. A non-volatile semiconductor memory device having floating gate construction comprising double polycrystal silicon gates, characterised in that inter insulating layer between the double polycrystal silicon gates is made up of silicon nitride layer formed by direct nitrisation of the first layer of said polycrystal silicon.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17559480A JPS5799782A (en) | 1980-12-12 | 1980-12-12 | Semiconductor memory device |
| JP14902981A JPS5850779A (en) | 1981-09-21 | 1981-09-21 | Semiconductor memory device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB2092824A true GB2092824A (en) | 1982-08-18 |
| GB2092824B GB2092824B (en) | 1984-08-15 |
Family
ID=26479038
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB8135384A Expired GB2092824B (en) | 1980-12-12 | 1981-11-24 | A non-volatile semiconductor memory device |
Country Status (3)
| Country | Link |
|---|---|
| DE (1) | DE3148807C2 (en) |
| GB (1) | GB2092824B (en) |
| HK (1) | HK73886A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0308316A1 (en) * | 1987-09-18 | 1989-03-22 | STMicroelectronics S.A. | Process for self-aligning the floating gates of non-volatile memory floating gate transistors, and memory obtained by this process |
-
1981
- 1981-11-24 GB GB8135384A patent/GB2092824B/en not_active Expired
- 1981-12-10 DE DE3148807A patent/DE3148807C2/en not_active Expired
-
1986
- 1986-10-02 HK HK738/86A patent/HK73886A/en not_active IP Right Cessation
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0308316A1 (en) * | 1987-09-18 | 1989-03-22 | STMicroelectronics S.A. | Process for self-aligning the floating gates of non-volatile memory floating gate transistors, and memory obtained by this process |
| FR2620847A1 (en) * | 1987-09-18 | 1989-03-24 | Thomson Semiconducteurs | METHOD FOR SELF-ALIGNMENT OF FLOATING GRIDS OF FLOATING GRID TRANSISTORS OF A NON-VOLATILE MEMORY AND MEMORY OBTAINED ACCORDING TO THIS METHOD |
Also Published As
| Publication number | Publication date |
|---|---|
| GB2092824B (en) | 1984-08-15 |
| HK73886A (en) | 1986-10-10 |
| DE3148807C2 (en) | 1983-11-03 |
| DE3148807A1 (en) | 1982-08-12 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PE20 | Patent expired after termination of 20 years |
Effective date: 20011123 |