GB2089117A - Improvement in and relating to the manufacture of water scale integrated circuits - Google Patents
Improvement in and relating to the manufacture of water scale integrated circuits Download PDFInfo
- Publication number
- GB2089117A GB2089117A GB8039046A GB8039046A GB2089117A GB 2089117 A GB2089117 A GB 2089117A GB 8039046 A GB8039046 A GB 8039046A GB 8039046 A GB8039046 A GB 8039046A GB 2089117 A GB2089117 A GB 2089117A
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- GB
- United Kingdom
- Prior art keywords
- masking process
- areas
- common
- reticle
- photoresist
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
A patterned integrated circuit metallization layer has parts defined from a common metal layer by a step and repeat mask 18 for component bearing areas of a circuit 24 and by a whole wafer reticle mask 26 for areas of interconnection 30 between the component bearing areas. A single photoresist may be sequentially exposed by these two steps and then processed. Positive or negative photoresist may be used and the order of masking may be reversed. <IMAGE>
Description
SPECIFICATION
Improvement in and relating to the manufacture of wafer scale integrated circuits
The present invention relates to a method for providing metallisation patterns on a wafer scale integrated circuit.
A wafer-scale integrated circuit can be defined as a whole wafer of active circuits mounted in a single package. A large number of usually identical, separately functional integrated circuits are provided on a single, semi-conducting wafer. Certain electrical connections, known as Global connections, are common to all or most of the integrated circuits.
Power connections, and connections carrying common control signals are suitable subjects for Global treatment. Any signal which is provided to a substantial proportion of the integrated circuits on the wafer is a Global signal.
The extensiveness of the distribution of the Global signals on a wafer-scale integrated circuit necessitates that the signal be distributed via metal conduction paths in order to minimise losses.
In the present state of the art there exist two methods for making the metalisation pattern required by a wafer-scale integrated circuit.
In a first method one mask is used which is common to all of the individual integrated circuits on the wafer. The mask is used first in one position on the wafer, then in another, to mark out a repetitive plurality of metal areas on the wafer, each area corresponding to the metalisation pattern of an individual integrated circuit. This process is known as "step and repeat", that is the sam pattern being repeated at controlled intervals across the wafer.
The metal areas for each of the integrated circuits can include Global lines, in which case the disposition and necessary repetitive symmetry of these connections place severe limitations on the manner in which the Global connections can be made. It is more usually the case that the metal areas for the individual integrated circuits are laid down as a first pattern of metalisation, and interconnections between the individual integrated circuits are laid down as a second pattern of metalisation. This necessitates a cost and time consuming two pass metalisation process.
In a second method a reticle can be used, that is, a mask which covers all or most of the area of the wafer. The metalisation pattern both within each of the integrated circuits on the wafer and therebetween is laid down as a single process.
In this second method a first problem arises concerning the positional accuracy which can be defined by a reticle. While the step-and-repeat method currently allows for the definition of position on the wafer and consequent control of conductor dimensions to within around 2 micrometers, the use of a reticle, which can be generated only as accurate- ly as the pattern generator which creates it, allows only that a position on the wafer be defined with an accuracy of the order of 10 micrometers. This five-to-one loss of definition in conductor positions and dimensions necessitates that the individual integrated circuits on the wafer be much more loosely packed with components than might otherwise be possible using a step-and-repeat metalisation masking process.The loss of areal efficiency so encountered makes the use of a single reticle metalisation masking process for a wafer scale integrated circuit most unattractive.
A second problem arises with this second method in that, while it is relatively easy to align a step-andrepeat small area mask over a wafer it is extremely difficult and time consuming and requires much skill, to so align a reticle which bears individual circuit detail.
A wafer-scale integrated circuit is hereinafter defined as an integrated circuit comprising a plurality of identical integrated circuit areas on a common substrate, each of said areas being provided with a local pattern of electrically conductive metalisation and said areas being interconnected for simultaneous operation by a Global pattern of electrically conductive metalisation.
A step and repeat masking process is hereinafter defined as a masking process which uses the same mask in a plurality of locations on a substrate.
A rectic le masking process is hereinafter defined as a masking process using a mask which covers the entire surface of a substrate.
The present invention consists in a method for metalising a wafer scale integrated circuit including the etching of a common metallic layer to leave, as the local metalisation, areas defined by a step-andrepeat optical masking process and to leave, as the
Global metalisation, areas defined by a rectic le optical masking process.
In a preferred embodiment a preferably silicon whole-wafer integrated circuit which has been fabricated to the point of completion of diffusion, has coated thereover a layer of metal which makes ohmic contact where required, with each one out of a plurality of areas of diffusion thereon. The metal is preferably coated with a layer of photresist which preferably becomes etch resistant subsequently to being exposed to light. The areas of diffusion are preferably all identical to one another, in which case the photoresist over the areas of diffusion is exposed to light using the same metalisation defining mask for each of the areas on a step-and-repeat basis. The photoresist intermediate between the diffused areas is preferably exposed to light using a single, reticle mask covering the whole area of the wafer and defining metalisation intermediately between the areas.Subsequently to both exposures, the photoresist is preferably cured and the unexposed part thereof preferably washed away. Thereafter the metal which is not protected by cured photoresist is preferably etched away to leave a pattern of metalisation on the wafer.
The invention, is further explained, by way of an example, by the following description in conjunction with the appended drawings, in which:
Figure 1 shows a diffused wafer substrate prior to metalisation;
Figure 2 shows the substrate of Figure 1 coated in metal;
Figure 3 shows the metal coated substrate of
Figure 2 further coated in unexposed photoresist;
Figure 4 shows the exposing of the photoresist for local metalisation using a step-and-repeat mask;
Figure 5 shows the exposing of the photoresist for
Global metalisation using a reticule masking process.
Figure 1 shows a silicon wafer 10 whereon have been diffused a plurality of identical areas 12 which require only the addition of metalisation to become functionable integrated circuits. The areas 12 are further to be connected to one another and to the outside world to form a wafer scale integrated circuit whereon each of the areas 12 is simultaneously operable, dependently upon being capable of passing a functional test, as part of a larger circuit.
Figure 2 shows the wafer of Figure 1 coated in a metallic layer 14. This is done in the normal way well known in the art of integrated circuit fabrication. The metal is aluminium, but could equally well be any other which is so usable. The metal layer 14 makes ohmic contact with those parts of the diffused areas 12 which are to be electrically connected to any other point by metalisation.
Figure 3 shows the metal coated 14 wafer 10 of
Figure 2 further coated in a photoresist layer 16. The photoresist is of a type which can be cured only when light has been incident thereon.
Figure 4 shows the exposure of the local metalisation of the wafer scale integrated circuit.
A Astep and repeat mask 18 whereon there is only one area of transparency 20 bearing the pattern for the local metalisation of the areas 12, is moved across the surface of the photoresist 16 on the metal 14 and wafer 10 and stopped in conjunction with the operation of a lightsource 22 to provide, over each of the diffused areas 12, an area of exposed photoresist 24 corresponding to the metalisation pattern which is required on the areas 12.
Figure 5 shows the exposure of the photoresist 16, subsequently to the step-and-repeat exposure for the local metalisation, to the light pattern required for the Global metalisation.
A reticle mask 26 covers the entire area of the wafer 10. After the reticle mask 26 has been positioned, the lightsource 22 is operated to expose areas of Global lines 30 on the photoresist 16 in response to the Global metalisation defining areas of transparency 28 on the reticle mask 26.
The photoresist 16 having thus been twice exposed, once for the local metalisation and once for the Global metalisation, using a step-and-repeat optical mask and a reticle optical mask respectively, is cured so that those areas which have had light incident thereon become a tough polymer resistent to metal etching solution.
The metal layer 14 is etched leaving behind only those areas which are protected by the photoresist 16, i.e. leaving a pattern of metalisation on the now wafer scale integrated circuit on the substrate 10 which has been defined according to the present invention.
It is to be appreciated that the diffused areas 12 need not all be identical to one another, several different kinds of areas being possible provided that the local metalisation mask 18 is replaced by one mask for each of the different types of areas 12. It is further to be appreciated that other types of photoresistance schemes may be used, for example a photoresist which is cured only when it has not been exposed to the light being usable with masks 26, 18 which are modified to exclude light from those areas of metal 14 which are required to remain after etching. The order of step-and-repeat masking followed by reticle masking can be reversed, and indeed, the reticle masking can be performed amid the step-and-repeat masking steps. The reticle masking process for the Global lines can be performed in several stages.
CLAIMS (Filed on 27 Nov 81)
1. A method for metalising an integrated circuit comprising a plurality of identical circuit areas on a common substrate, said method including the etching of a common metallic layer to leave, as the metallization in each of said circuit areas, areas of metallization as defined by a step and repeat optical masking process, and to leave, as the metallization between said circuit areas, an area of matallization as defined by a reticle optical masking process.
2. A method according to claim 1 wherein said reticle optical masking process includes the successive masking of different parts of said area of metallization between said circuit areas.
3. A method according to claim 2 wherein the stages of said successive masking of said area of metallization between said circuit areas are performed using the same reticle mask displaced to a different position for each successive stage of said successive masking process.
4. A method according to claim 3 wherein said step-and-repeat masking process and said reticle masking process include the exposure of a common layer of photoresist which resists etching of said common metallic layer subsequently to the incidence of light thereon.
5. A method according to claim 1,2,3 or 4 wherein said common substrate is a circular, semiconductor wafer and said plurality of circuit areas comprises a plurality of data processing cells.
6. A method according to claim 3 wherein said step-and-repeat masking process and said reticle masking process include the exposure of a common layer of photoresist which resists etching of said common metallic layer only if it has not had light incident thereon.
7. A method according to claim 6 wherein said common substrate is a circular, semiconductor wafer and said plurality of circuit areas comprises a plurality of data processing cells.
8. A method according to claim 2 wherein said step-and-repeat masking process and said reticle masking process include the exposure of a common layer of photoresist which resists the etching of said common metallic layer subsequently to the incidence of light thereon.
9. A method according to claim 2 wherein said step-and-repeat masking process and said reticle masking process include the exposure of a common layer of photoresist which resists the etching of said
**WARNING** end of DESC field may overlap start of CLMS **.
Claims (42)
1. A method for metalising an integrated circuit comprising a plurality of identical circuit areas on a common substrate, said method including the etching of a common metallic layer to leave, as the metallization in each of said circuit areas, areas of metallization as defined by a step and repeat optical masking process, and to leave, as the metallization between said circuit areas, an area of matallization as defined by a reticle optical masking process.
2. A method according to claim 1 wherein said reticle optical masking process includes the successive masking of different parts of said area of metallization between said circuit areas.
3. A method according to claim 2 wherein the stages of said successive masking of said area of metallization between said circuit areas are performed using the same reticle mask displaced to a different position for each successive stage of said successive masking process.
4. A method according to claim 3 wherein said step-and-repeat masking process and said reticle masking process include the exposure of a common layer of photoresist which resists etching of said common metallic layer subsequently to the incidence of light thereon.
5. A method according to claim 1,2,3 or 4 wherein said common substrate is a circular, semiconductor wafer and said plurality of circuit areas comprises a plurality of data processing cells.
6. A method according to claim 3 wherein said step-and-repeat masking process and said reticle masking process include the exposure of a common layer of photoresist which resists etching of said common metallic layer only if it has not had light incident thereon.
7. A method according to claim 6 wherein said common substrate is a circular, semiconductor wafer and said plurality of circuit areas comprises a plurality of data processing cells.
8. A method according to claim 2 wherein said step-and-repeat masking process and said reticle masking process include the exposure of a common layer of photoresist which resists the etching of said common metallic layer subsequently to the incidence of light thereon.
9. A method according to claim 2 wherein said step-and-repeat masking process and said reticle masking process include the exposure of a common layer of photoresist which resists the etching of said common metallic layer only if it has not received light incidently thereon.
10. A method according to claim 8 or 9 wherein said common substrate is a semiconductor, circular wafer and wherein said plurality of circuit areas comprises a plurality of data processing cells.
11. A method according to claim 1 wherein said step-and-repeat masking process and said reticle masking process include the exposure of a common layer of photoresist which resists the etching of said common metallic layer subsequently to the incidence of light thereon.
12. A method according to claim 1 wherein said step-and-repeat masking process and said reticle masking process include the exposure of a common layer of photoresist which resists the etching of said common metallic layer only if it has not received light incidentlythereon.
13. A method according to claim 11 orl2where- in said common substrate is a circular, semiconductor wafer and said plurality of circuit areas comprises a plurality of data processing cells.
14. A method substantially as described with reference to the appended drawings.
15. An apparatus for metalising an integrated circuit, where said integrated circuit comprises a plurality of identical circuit areas on a common substrate, said apparatus comprising, means for etching a common metallic layer to leave, as the metallization in each of said circuit areas, areas of metallization as defined by a step-and-repeat optical masking process and to leave, as the metallization between said circuit areas, an area of metallization as defined by a reticle optical masking process.
16. An apparatus according to claim 15 wherein said reticle masking process includes the successive masking of different parts of said area of metallization between said circuit areas.
17. An apparatus according to claim 16 wherein the stages of said successive masking of said area of metallization between said circuit areas are performed using the same reticle mask displaced to a different position for each successive stage of said successive masking process.
18. An apparatus according to claim 17 wherein said step-and-repeat masking process and said reticle masking process include the exposure of a common layer of photoresist which resists the etching of said common metallic layer subsequently to the incidence of light thereon.
19. An apparatus according to claim 18 for use with said common substrate consisting in a circular, semiconductor wafer and said plurality of circuit areas comprising a plurality of data processing cells.
20. An apparatus according to claim 17 wherein said step-and-repeat masking process and said reticle masking process include the exposure of a common layer of photoresist for resisting the etching of said common metallic layer only if it has not received light incidently thereon.
21. An apparatus according to claim 20 for use with said common substrate consisting in a circular, semiconductor wafer and with said plurality of circuit areas comprising a plurlality of data processing cells.
22. An apparatus according to claim 16 wherein said step-and-repeat masking process and said reticle masking process comprise the exposure of a common layer of photoresist for resisting the etching of said common metallic layer only on those parts where light has been incident thereon.
23. An apparatus according to claim 16 wherein said step-and-repeat masking process and said reticle masking process comprise the exposure of a common layer of photoresist for resisting the etching of said common metallic layer only on those parts thereof where light has not been incident thereon.
24. An apparatus according to claim 22 or claim 23 for use where said common substrate consists in a circular, semiconductor wafer and said plurality of circuit areas comprises a plurality of data processing cells.
25. An apparatus according to claim 15 wherein said step-and-repeat masking process and said reticle masking process include the exposure of a common layer of photoresist for resisting the etching of said common metallic layer only on those parts where light has been incident thereon.
26. An apparatus according to claim 15 wherein said step-and-repeat masking process and said reticle masking process include the exposure of a common layer of photoresist for resisting the etching of said common metallic layer only on those parts which have not had a light incident thereon.
27. An apparatus according to claim 25 or 26 for use where said common substrate is a semiconductor, circular wafer and where said plurality of circuit areas comprises a plurality of data processing cells.
28. An apparatus substantially as described with reference to the appended drawings.
29. An integrated circuit comprising a plurality of identical circuit areas on a common substrate and characterised by being fabricated according to a method which includes the etching of a common metallic layer to leave, as the metallization in each of said circuit areas, areas of metallization as defined by a step-and-repeat optical masking process, and to leave, as the metallization between said circuit areas, an area of metalisation as defined by a reticle optical masking process.
30. An integrated circuit according to claim 29 wherein said reticle optical masking process includes the successive masking of different parts of said area of metallization between said circuit areas.
31. An integrated circuit according to claim 30 wherein the stages of said successive masking of said area of metallization between said circuit areas are performed using the same reticle mask displaced to a different position for each successive stage of said successive masking process.
32. An integrated circuit according to claim 31 wherein said step-and-repeat masking process and said reticle masking process include the exposure of a common layer of photoresist for resisting the etching of said common metallic layer only in those parts whereon light is subsequently incident.
33. An integrated circuit according to claim 32 wherein said common substrate is a circular, semiconductor wafer and wherein said plurality of circuit areas comprises a plurality of data processing cells.
34. An integrated circuit according to claim 31 wherein said step-and-repeat masking process and said reticle masking process include the exposure of a acommon layer of photoresistfor resisting the etching of said common metallic areas only in those parts whereon light is not incident.
35. An integrated circuit according to claims 29 to 34 wherein said common substrate is a circular, semiconductor wafer and wherin said plurality of circuit areas comprises a plurality of data processing cells.
36. An integrated circuit according to claim 30 wherein said step-and-repeat masking process and said reticle masking process include the exposure of a common layer of photoresist for resisting the etching of said common metallic layer in those parts whereon light is incident.
37. An integrated circuit according to claim 30 wherein said step-and-repeat masking process and said reticle masking process include the exposure of a common layer of photoresistfor resisting the etching of said common metallic layer in those parts whereon light is not incident.
38. An integrated circuit according to claim 36 or claim 37 wherein said common substrate is a circular semiconductor wafer and said plurality of circuit areas comprises a plurality of data processing cells.
39. An integrated circuit according to claim 29 wherein said step-and-repeat masking process and said reticle masking process include the exposure of a common layer of photoresist for resisting the etching of said common metallic layer in those parts which have light incident thereon.
40. An integrated circuit according to claim 29 wherein said step-and-repeat masking process and said reticle masking process include the exposure of a common layer of photoresist for resisting the etching of said common metallic layer in those parts that do not receive light incidentlythereon.
41. An integrated circuit according to claim 39 or claim 40 wherein said common substrate is a circular, semiconductor wafer and wherein said plurality of circuit areas comprise a plurality of data processing cells.
42. An integrated circuit substantially as described with reference to the appended drawings.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB8039046A GB2089117B (en) | 1980-12-05 | 1980-12-05 | Improvements in and relating to the manufacure of wafer scale integrated circuits |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB8039046A GB2089117B (en) | 1980-12-05 | 1980-12-05 | Improvements in and relating to the manufacure of wafer scale integrated circuits |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB2089117A true GB2089117A (en) | 1982-06-16 |
| GB2089117B GB2089117B (en) | 1984-10-17 |
Family
ID=10517775
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB8039046A Expired GB2089117B (en) | 1980-12-05 | 1980-12-05 | Improvements in and relating to the manufacure of wafer scale integrated circuits |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB2089117B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0403898A2 (en) * | 1989-06-15 | 1990-12-27 | Fujitsu Limited | Wafer-scale semiconductor integrated circuit device and method of forming interconnection lines arranged between chips of wafer-scale semiconductor integrated circuit device |
| US5349219A (en) * | 1989-06-15 | 1994-09-20 | Fujitsu Limited | Wafer-scale semiconductor integrated circuit device and method of forming interconnection lines arranged between chips of wafer-scale semiconductor integrated circuit device |
| EP0646949A2 (en) * | 1993-10-01 | 1995-04-05 | Motorola, Inc. | Method of forming a semiconductor device |
-
1980
- 1980-12-05 GB GB8039046A patent/GB2089117B/en not_active Expired
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0403898A2 (en) * | 1989-06-15 | 1990-12-27 | Fujitsu Limited | Wafer-scale semiconductor integrated circuit device and method of forming interconnection lines arranged between chips of wafer-scale semiconductor integrated circuit device |
| EP0403898A3 (en) * | 1989-06-15 | 1991-08-07 | Fujitsu Limited | Wafer-scale semiconductor integrated circuit device and method of forming interconnection lines arranged between chips of wafer-scale semiconductor integrated circuit device |
| US5349219A (en) * | 1989-06-15 | 1994-09-20 | Fujitsu Limited | Wafer-scale semiconductor integrated circuit device and method of forming interconnection lines arranged between chips of wafer-scale semiconductor integrated circuit device |
| EP0646949A2 (en) * | 1993-10-01 | 1995-04-05 | Motorola, Inc. | Method of forming a semiconductor device |
| EP0646949A3 (en) * | 1993-10-01 | 1997-03-26 | Motorola Inc | Method of forming a semiconductor device. |
Also Published As
| Publication number | Publication date |
|---|---|
| GB2089117B (en) | 1984-10-17 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 19921205 |