GB2085206A - Drop-out compensation for digital data on video tape recorders - Google Patents

Abstract

Prior to recording, data 30 received by an assembler 31-37 is assigned to a predetermined non- standard format in which each "line" comprises a corresponding bit from each word of a block. Addition of synchronising information via a process amplifier allows the digital data to be recorded on an analog video tape recorder 18 as lines of video information. A binary '1' count "line" checksum generator 38 and a word parity bit generator 36 are provided to effect two dimensional coding indicative of assigned data content both prior to recording and following playback each recorded block ending with a "line" of parity bits. By detecting any differences between the played back and regenerated coding information drop out errors can be identified and compensated for. <IMAGE>

Description

SPECIFICATION Storage and retrieval of digital data on video tape recorders The invention relates to the storage and retrieval of digital video data on a video tape recorder (VTR).

Asystem disclosed in British Patent Application 7930222 (Publication 2059713) and U.S. Patent application 172,721 relates to a video information system which allows video digital data to be recorded onto a standard analogue video tape recorder.

With modern types of VTR, there is a tendency for degradation due to a signal drop out (resulting from imperfections on the tape for example). When such tapes are used for duplication purposes, any errors are compounded.

Figure 1 shows a typical defect on the video tape 10. The scratch 11 extends across the path of several recorded fields and the analogue information from the tape on playback is visibly degraded as a result of the drop outs 12 due to this scratch. Several drop outs on a line will give the result of a horizontal stripe on the picture. Thus because such a drop out has no vertical structure, using the basic recording technique described in the aforementioned patent application will mean that the serially recorded data will result in errors occuring whenever a drop out occurs. It is known to compensate for drop outs on normal video information by using data from an adjacent line above or below the drop out to replace any data lost (see U.K. Patent No. 1,436,757 and U.S.

Patent No.3,949,416 for example). Whilst this works well for normal analogue picture information, in the above information system using digital data its configuration is such that adjacent data will not correspond to the data missing in the drop out so this type of error correction is ineffective.

The present invention is concerned with providing an arrangement which may be used for the above purpose for example but having greater immunity to signal drop outs.

According to the invention there is provided a digital data manipulation system for compensating for drop outs on a video recording medium comprising data receiving means for assigning data to a predetermined format prior to recording, coding means for providing two-dimensional coding indicative of assigned data content both prior to recording and following playback, and detector means for identifying any differences between the coding information indicative of drop out errors to allow compensation therefor.

The invention will now be described with reference to the accompanying drawings, in which: Figure 1 shows a typical recorded video tape with imperfections thereon; Figure 2 shows a drop out reproduced on playback; Figure 3 shows the known recording system; Figure 4 shows the data format of this system prior to recording, Figure 5 shows the system of the present invention associated with recording, Figure 6 shows one embodiment of the data format of the present invention; Figure 7 shows the format of data along one T.V.

line; Figure 8 shows the system of the present invention associated with playback, Figure 9 shows one arrangement for producing the desired format and coding on the record side of the system, Figure 10 shows one arrangement concerned with realising the playback side of the system, Figure 11 shows one embodiment of the data correctorof Figure 10, Figure 12 shows drop outs occurring on more than one line, Figure 13 shows the data format adopted in the second embodiment, Figure 14 shows one arrangement for providing this format prior to recording, Figure 15 shows manipulation of the data following playback, Figure 16 shows examples of possible situations resulting from the check sum comparison, Figure 17 shows the concealment aspect in more detail, and Figure 18 shows the modified data corrector.

Figure 3 shows part of the information transfer system of Patent Application 7930222 associated with recording. Video data in digital form is already present on disc 14 and typically during read out, the output data rate from such a disc (e.g. a Winchester disc) will be 1 Megawords/second, each word being in 8 bit parallel form. This data is received by buffer store 15 which holds this data which will typically appear as interrupted blocks with data gaps according to the normal read out pattern of such a standard disc. The buffer store outputs the data as a continuous stream at a somewhat slower rate typically B Megawordisec again in 8 bit parallel form. This data is received by serialiser 16 which converts converts the parallel data into serial form, thus providing a data output rate typically 4M bit/sec.This data stream (shown in Figure 4) is received by a process amplifier 17 in which syncs and colour burst are added so as to produce a digital data stream with analog sync and burst information. This allows the data to be recorded on a standard analogue VTR 18.

The syncs and colour burst may be provided from a local generator in well known manner. On replay the serial data stream will be separated from the synchronising information and typically this digital data will be converted into parallel form and buffered into data blocks compatible with a receiving disc.

As shown in Figure 4, the serial 8 bit word format is recorded onto the tape as a single video line of data (words 1 to N) and such a system works well except when a drop out occurs as the data lost cannot be retrieved.

The present arrangement now shown in Figure 5 provides the ability of detecting and compensating for drop outs on the replayed data by rearranging the data format and by including coding information to accompany the digital data when recorded on an analogue tape recorder or other recording medium.

Incoming information is received by data assembler 19 which data is shown in this example as being received from disc 14 though other data sources could be used. The assembler 19 formats the data into a predetermined configuration described in more detail below and coded information indicative of data contact is provided by the check sum and parity bit generators 20 and 21 respectively and in this example the composite data passes to process amplifier 17 where syncs and colour burst are added to the digital data to provide the analogue tape recorder 18 with the capability of handling the incoming information. The data assembler 19 is designed to rearrange the data into a non-standard format which lends itself to aiding recovery or compensation for any lost data rather than the sequential word format of Figure 4.The generators 20 and 21 provide content information for this data such that a "two-dimensional" code is provided to accompany the rearranged data when received by the process amplifier for example.

One way of rearranging the video data together with the coding data is shown in Figure 6 which will be received by the process amplifier 17 for recording as if it were 9 successive lines of normal video information.

The amount of data, say bits a1 - an, with its check sum is chosen to correspond to a 'length' equivalent to the active T.V. line length. If such digital data as recorded were to be displayed on the T.V. screen it would be somewhat similarto a random chessboard effect with white peak level defining the logically high levels and black level defining the logically low levels, the colour burst and syncs providing the necessary timing information as shown by the T.V.

line in Figure 7.

Drop outs R and S in Figure 6 are included on one line for explanation of the system operation. The 9 lines of data include 8 lines carrying video information and the last line carrying parity information.

Rather than in the Figure 4 arrangement, due to the presence of assembler 19 the lines each carry one bit of each word, so that the most significant bit (MSB) a for the words 1 to N are all on one line and so on, rather than the normal serial data format of a1 to h1, a2 to h2, a3 to h3 etc. At the end of the line, a check sum word is included which gives a count of the number of times a 'high' has occurred in the N bits on that line. The check sum word is of sufficient length to define the maximum value of N. For example, if N = 128 bits (which is also the number of words handled) then the check sum will need to be a 7 bit serial word. A check sum is provided for each line representing the data bits 'a' and so on.In addition a check sum is provided for the parity bits, each parity bit P1 to Pn being generated in dependence on whether there are an odd or even number of 'highs' in the word associated with it. By providing both the check sum and the parity bit for the data format provided, it is possible to produce a two dimensional check so as to be able to identify and also to correct any subsequent errors on playback as now explained in relation to Figure 8.

On playback the digital data from VTR 18 is provided via the output of sync separator and slicer block 25, which data includes the previously recorded check sum and parity bits. On playback however the check sum and parity bits are again computed this time on the outgoing data by means of generators 27 and 28 respectively. The recorded check sum made available on playback is compared in comparator and corrector block 29 with the generated check sum calculated from the played back data and the parity bit is similarly checked and if no error between these calculations is detected then the outgoing data is passed without modification to the output, since a lack of error indicates identity between input and output of the data (i.e. no drop outs).If comparison of a parity bit for a particular word indicates a difference (i.e. an error) then the location of the error can be detected by the comparison of the check sum. By inverting the status of the offending bit in corrector 29 the correct information previously lost has been reconstituted.

Thus looking at the example of the drop outs R and S of Figure 6, during the recording phase the correctly calculated checksum and parity bits will accompany the data onto the tape. Due to drop outs, on playback the calculated check sum 'd' will be different as will parity bits PR and Ps. This effectively defines the X and Y coordinates of the drop outs and by inverting the output of these points the correct data is provided.

Thus by recording the check sum for each line at the end of each line and the parity bits for each word on the 9th line and repeating the calculation process on playback and comparing results, the corruption of data can be detected and corrected. This corrected data is thus available for further use, for example it can be passed to the disc 14.

Subsequent data for recording is handled in the next and subsequent blocks of 9 video lines.

One arrangement for providing the coding of the data prior to recording on the tape is now described in more detail with reference to Figure 9.

The incoming digital video information shown arriving in typical known format of 8 bit parallel word form is passed via switch 30 to one or other storage RAM 32 or 33 (in the illustration the switch is connected to RAM 32). The write cycle for a RAM is completed when the predetermined number of words (e.g. 128) has been written into its internal locations designated by the counter configuration within address block 44 in known manner. As shown, during write in of RAM32, read out from RAM 33 can be effected as selected by switch 35.

Thus write in to a RAM is a word rate (say 1 lis) and, the RAM would be filled in 128 us if the data is received as a continuous stream. Other rates would be possible by varying the word rate and RAM capacity. In practice when data is being received from disc 14 it is typically received as noncontinuous bursts of data so the RAM will take longer to fill in this case. Clocks from the disc 14 received by the input clock generator 42 ensure that the RAMs correctly receive the incoming data. The normal sequencing capability of the clock generator 42 is conveniently used to increment the address block 44. Such generatos have knowledge of start of field or line and with internal counters can count the picture point clocks to provide the necessary sequencing when handling disc (orVTR) information.

A control input to the disc 14 from generator 42 determines when the disc is allowed to produce the video data (and clocks). As shown, the intermittent operation of the disc is effectively under the control of the VTR 18 via output clock generator 43, and this is necessary because the VTR will run continuously and thus require priority. After loading RAM 32, switches 30 and 31 are changed to connect the other RAM and the write process continued. Whilst RAM 32 is receiving data, data from RAM 33 is read out (non-destructively) from its locations in the sequence dependent on the counter configuration within read address block 45. Thus words 1 through 128 are passed via switch 35 to switch 37.Switch 37 is only concerned with passing one of the 8 bits from each word and as shown bit 'a' from word 1 through 128 is passed as a single bit stream to switch 40 to provide the data in the format shown in line 1 of Figure 6. The check sum is calculated for this bit stream by counter 38, the output thereof being in 7 bit (or 8 bit may be more convenient as being a standard item) parallel form. This parallel bit word is converted into serial form by converter 39, switch 40 being arranged to switch after the passage of the 'a' bits to allow the check sum to accompany the data as shown in Figure 6.

The binary levels are converted into suitable black or white levels as necessary in generator 41 (which is typically partofthe process amplifier 17) before the sync and colour burst information is added as described above prior to recording on the VTR 18.

The check sum counter 38 starts at zero at the start of the line and is incremental each time a 1 (high) is detected and the final count for the line (after word 128) is then made available via converter 39 and switch 40.

Thus a1; asp ... to a128 are sent serially to the tape rather than the normal serial format of a1 to hl; a2to h2 etc shown in Figure 4.

The read out process is then repeated with switch 35 in the same position but with switch 37 moved to receive the 'b' bit of words 1 to 128. Although only one bit of each word is passed on, it is convenient to read out the entire 8 bits of each word throughout the RAM. Sequentially switch 37 is moved after each read cycle to provide a total of 9 identical read operations. The RAM read operations for a cycle will be substantially faster than the write operations as the synchronising information from the VTR will typically result in a clock rate from generator 43 of several MHz and the data can be received continuously rather than in burst as in the disc so that the 9 operations may be accommodated within the period taken to effect a single write operation in the other RAM. During the 9th read operation, the parity bit is generated for each data word by generator 36.

The 8 bit data (a to h) for word 1 is received by the known generator which if a high is detected an even number of times (i.e. twice, four or eight times) then a logically high output is provided for that word (see P1 of Figure 6). If an odd number of highs occur for that word then a logically low level is provided.

The parity check is repeated on each word as it is read out and with switch 37 connected to receive these parity bits, P1 through P128, the check sum counter 38 operates to provide a count of the highs detected thereon to provide a check sum output via converter 39 to accompany the parity bits as shown in Figure 6 as line 9.

After completion of the read out cycles from RAM 33, the switches 34 and 35 respectively change position so that write in to RAM 33 and read out of the accumulated data from RAM 32 can be effected.

This data will constitute the next 9 video lines of data recorded, and so on until all the available incoming data is recorded as a number of fields.

The sequencing capabilities of output clock generator 43 can conveniently be used as shown to control switches 30 - 35, input generator 42 and provide clocks for read address block 45. Generator 43 can also be used to operate switch 37 at line rate and blocks 38 and 39 at bit rate. Switch 40 is actuated for a given number of bits at the end of each line to allow passage of the check sum before returning to the position shown.

The processing of the replayed data will now be described in more detail with reference to Figure 10.

The digital data from the VTR (having been stripped of syncs and shaped by slicing as described above) is passed via switch 50 to either RAM 51 or 52. Whilst RAM 51 is being written into in locations defined by address block 60 via switch 49, RAM 52 is available for read out via switch 57 from locations governed by address block 69 via switch 63. As shown schematically, the data has been written into RAM 52 such that bit 'a' of words 1 to 128 are in sequence followed by bits 'b' to 'h' and the parity bits P1 to P128. Thus the data can be considered as effectively being stored in rows, switching at line rate, and it is arranged via the counters within write address block 60 that the addressing is always such that the first bit 'a' of the first word goes into the first line at the start of each field, so that correlation between record and playback is maintained.During playback the system switches will this time be under the control of input generator 53, as again the VTR will run continuously whilst the disc is capable of handling data in bursts when permitted by the system control. The blocks associated with write sequencing will also receive clocks from generator 53.

It is to be noted that the check sum for a particular line is not stored in the RAM but is received by converter 55 which provides the check sum as an 8 bit parallel word for receipt by comparator 56. Prior to the receipt of the previously recorded check sum, the check sum counter 54 is calculating the check sum for that line so that the presently calculated and previously calculated check sums are available to comparator 56 which produces a binary 'low' output if no difference is detected, and a high if an error is detected. The comparator result is passed via switch 59 to one or other check sum registers 65 or 66, such that the result of the 'a' bits from the first video line is stored in one location followed by the 'b' bit etc as shown in Figure 10. Output clock generator 68 in practice controls the sequencing of the disc and the blocks associated with the read side of the system.

Whilst one RAM and register is busy with a write in sequence, the others are available for read out. Thus as shown bits 'a' to 'h' on words 1 through 128 pass from RAM 52 via switch 57 to the corrector 64. At the same time, the parity generator 61 is calculating the parity status of each outgoing word in sequence. The parity bit for each word is compared with the equivalent parity bit received from RAM 52 via switch 58. If a difference is detected then a 'high' is produced by the comparator, if low then no error has been detected. The corrector 64 receives the single bit comparator output from the parity check together with the 8 bit check sum register output via switch 67. The corrector allows all 8 bits 'a' to 'h' for a word to pass unchanged if no parity error indication is received from comparator 62.When an error is received, then only the particular bit of the word identified by an error indication from the check sum register will be corrected (i.e. inverted), all other bits will pass through unchanged. Thus from Figure 6, a parity error will be detected for R and S (PR and Ps) as will a check sum error for bit 'd' for that line.

Because of the coding arrangement, both drop out errors R and S will be corrected, since the system is capable of effectively defining the location of a number of errors.

The corrector 64 can be constructed from standard logic elements as shown in the embodiment of Figure 11. Bits 'a' to 'h' are received by one input of Exclusive OR gates 70 to 77 respectively. The other input to these gates is connected to the output of AND gates 80 through 87 respectively. The output of comparator 62 (of Figure 10) is common to one input of gates 80 to 87 whilst the other input of the gates receives the check sum error status from register 66 (or 65) of Figure 10. As shown the eight bits from word 1 are present at the input to gates 70 to 77. An error previously detected on the parity check for word P1 will be identified as a high by gates 80 through 87. If an error for any bit is received from register 66 as a result of the earlier check sum comparison this will be identified as a high by the particular AND gate.This will cause that gate output to go high and result in inverting the output from the associated Ex.OR gate. Bits without any error will pass through unaltered. Thus the inputs 'a' to 'h' for Ex.OR gates will be changing at word rate as will the parity bit to gates 80 to 87. However, the input from the register will be changing at line rate.

Although the record and playback arrangements have generally been described as comprising separate items, it is clear that with suitable switching some of the system elements can be shared to provide use during both record and playback.

With the system described above using the format of Figure 6, this works well with normal drop out occurances. Thus it will cope with more than one drop out on any particular line provided that no more than one line in any particular block has drop outs. (In this case 8 lines constitutes the block).

Should however there be more than one line in the block which has drop outs, say lines 1 and 4, then the desired correction cannot be maintained and the corrector has to be overridden in this extreme case and the data allowed to pass through uncorrected.

The reason for this inability to correct the data can be seen from Figure 12. A drop out B and C is shown on lines 1 and 4 respectively with a corresponding check sum error being present. A parity bit error will also be present as shown and because of the drop out on two lines the system becomes confused and cannot tell whether the drop outs are at B and C or whether they have occurred atA and D (which in this example they have not).

A refinement to the above system now described allows such an exceptional drop out situation to be coped with by manipulating the data to disguise or conceal the drop out when more than one line in the block has drop outs. Whilst the previous and present schemes will absolutely correct the data when there are errors on only one line, the present scheme will only conceal rather than correct the error when more than one line is involved.

In order to conceal the drop outs, use is made of the normal sampling relationship relative to subcarrier. In this example it is assumed that the sampling rate is 4 x fsc but other rates could be used with subsequent modification of the system. The present system is generally similar to the Figure 8 arrangement although the formatting of the data now corresponds to that shown in Figure 13 and the comparator and corrector block 29 is modified relative to Figure 10 to cope with the additional control functions required.

Comparison of Figures 4,6 and 13 will show that rather than the standard serial word format or the single bit successive word format of the earlier embodiment, the Figure 13 format utilises nonsequential words along a given line. Thus in this embodiment using 8 lines plus 1 parity line in the block, word 1 is followed by words 9 and 17 and so on until the entire line is filled and including the check sum as the last data word on that line. Line two has word 2, 10, 18 etc with a similar eight word gap on the successive lines in that block. The ninth line will carry parity bit data and check sum as before.

An arrangement for producing the desired format and coding on the record side of the system is shown in Figure 14 and is similarto the Figure 9 arrangement except for the additional RAM stores 91 and 92 with associated switches 90 and 93. The system uses addressing and sequencing techniques for the RAMs and switches in similar manner to Figure 9, although now the additional switches 90 and 93 and RAMs also are under the influence ofthe output clock generator.

The incoming video is routed via switch 90 to either RAM 91 or 92. The data is written into the RAM in the sequence received, viz words 1,2,3,4 etc until the RAM is full when switch 90 is changed to input data to the second RAM. Whilst one RAM is receipt ing data the other is available for read out via switch 93. The read addressing is chosen such that the words are read out in the sequence 1,9, 17,25 etc followed by words 2,10, 18,26 etc and so on as in the Figure 13 format for the eight lines in the block.

The data is passed from either RAM 91 or 92 via switches 93 and 30 to RAM 32 or 33 and further processing for parity and check sum is effected on read out under control of the output clock generator as before, prior to recording. The playback arrangement of Figure 15 now described is similar to the Figure 10 configuration except that additional capacity is provided for registers 65 and 66 so that they have the facility to handle errors on the parity bit line (line 9). Also a further switch 95 is provided to connect all 9 locations to a decision making circuit block 96. The decision maker looks at any check sum error on lines 1 to 9 to control the corrector 64 or to actuate the concealer (described below).There are three cases which can be encountered by the decision circuit as follows: Case 1 If one and only one check sum error on one of the lines 1 to 8 is present without a check sum error on line 9 then the corrector 64 operates normally as in the earlier embodiment. (There are 8 possibilities for this case occurring.) Case 2 If a check sum error is present only on line 9 then the corrector is inhibited as is the concealer, so that effectively there is no change to the output video.

(There is only one possibility for this case to occur.) Case 3 If a check sum error is detected on more than one of the lines 1 to 8 then any parity check sum error is ignored, and the corrector is inhibited but the concealer is brought into operation. (There are 247 possible case 3 situations.) Examples of possible check sum register situations are given by way of example in Figure 16 illustrating the three possible cases.

The decision making and concealment aspects are now described in greater detail with reference to Figure 17. The corrector 64 is shown receiving the 8 inputs from the check sum error registers and the single input from the comparator of the Figure 15 arrangement. The decision maker 96 comprises a read only memory (ROM) which is programmed with decision laws such that the correct decision is reached for all the possible cases to be encountered as explained above. Thus the 9 inputs from the check sum error registers are used to access a certain address within the pre-programmed ROM and the data at that location is output for use in controlling the concealer and also the operation of the corrector 64. The concealer comprises registers 105 to 111, multipliers 120 to 127 and adder 130.To format the data into the desired sequence a pair of RAMs 101 and 102 are provided together with associated switches 100 and 103. Thus assuming no correction, the data passes through corrector 64 in the sequence word 1, word 9, word 17 etc and is written into RAM 101 or 102 so that on read out the sequence becomes word 1, word 2, word 3, etc. The data passes through the registers 103 - 111, which registers are each 8 bits wide x 1 bit long. Thus after 8 words have been read out of the RAM, then the 8 bit word 1 will be present at the output or register 111, word 2 will be present at the output of register 110 and so on with word 8 being present at the output of the RAM. The words are received by the respective digital multipliers 120 - 127 and the respective coefficient for each multiplier is provided by the decision maker 96.

The multiplier outputs are received by adder 130 which provides the summed video output from the concealer.

The operation of the decision maker in combination with the concealer is now described for the three case situations described above.

Case 1 The decision maker receives the output from the check sum error registers and produces binary data such that the corrector is on (i.e. not inhibited) to operate normally and the concealer is off (i.e.

transparent) by selecting one of the coefficients to be 1 and the remainder to be zero so that the video passes through the concealer without modification.

Case 2 The output from the decision maker produces an inhibit signal to the corrector to prevent any correction of data so that it is effectively transparent. One of the coefficients is selected to be 1 and the remainder zero so that the concealer is also transparent.

Case 3 The decision maker output causes the corrector to be inhibited to remain transparent and the concealer to operate to conceal the drop out errors. Thus assuming an error on words 1 and 4 then the scaling coefficients are output to be zero for words 1 and 4 and to substitute for this, by selecting appropriate fractions of other words. The choice of the words to be used as substitutes is governed by the relationship between the sampling rate and colour subcarrier. In the case of 4fsc sampling these are selected to be words 2 and 5 for word 1 and words 3 and 5 for word 4.

The corrector as described can be inhibited under the control of the decision maker. This is achieved by including additional AND gate 120 as shown in Figure 18 so that the comparator output is only allowed to pass to the remaining AND gates when control signal from the decision maker is received.

Although the system has been described as cooperating with an analogue video tape recorder, digital tape recorders are now becoming available and the system may have utility with this latter type of recorder.

Claims (19)

1. A digital data manipulation system for compensating for drop outs on a video recording medium comprising: data receiving means for assigning data to a predetermined format prior to recording; coding means for providing two dimensional coding indicative of assigned data content both prior to recording and following playback; and detector means for identifying any differences between the coding information indicative of drop out errors to allow compensation therefor.

2. A system as claimed in claim 1, wherein the data receiving means is adapted to rearrange the digital data whereby it is assigned to different video lines of a T.V. field, and said coding means includes: first coding means for providing an indication of the data content occurring along each video line for accompanying the data to be recorded; second coding means for providing an indication of the combined data content of a selected number of video lines for accompanying the data when recorded on the video recording medium; third coding means for providing an indication of the data content occurring along each video line on playback; fourth coding means for providing an indication of the combined data content of the selected number of video lines on playback; and wherein said detector means is adapted to compare the played back coded information derived from said first and second coding means with the coded information generated by said third and fourth coding means so as to identify and compensate for any detected error between the coded information indicative of a drop out.

3. A system as claimed in claim 2, wherein the first and second and the third and fourth coding means respectively comprise two common generators.

4. A system as claimed in claim 2 or 3, wherein the first coding means is adapted to provide an indication of the data content of said second coding means assigned to a given video line.

5. A system as claimed in claim 2,3 or 4, wherein the first coding means comprises a check sum generator adapted to indicate the number of bits occurring in a given line.

6. A system as claimed in any one of claims 2 to 5, wherein the second coding means comprises a parity bit generator adapted to indicate whether an odd or even number of bits of a given status occur in a given portion of the selected lines.

7. A system as claimed in any one of claims 1 to 6, wherein the detector means is adapted to compensate for drop out errors by correcting the error by inverting its detected status.

8. A system as claimed in any one of claims 1 to 7, wherein the data receiving means comprises a temporary store adapted to receive sequential data in parallel bit word from and for outputting data on a line by line basis in the form of a single bit stream of a given significance from each sequential word.

9. A system as claimed in claim 8, wherein the temporary store comprises a plurality of RAMs.

10. A system as claimed in claim 9, wherein the RAMs are adapted to receive data at a first rate and read out data at a second and faster rate.

11. A system as claimed in any one of claims 2 to 7, wherein the third coding means is adapted to provide an indication of the content from said second coding means.

12. a system as claimed in any one of claims 1 to 7 or 11, wherein the data receiver means comprises a temperature store adapted to receive sequential data in parallel bit word form and for outputting data on a line by line basis as a bit stream formed by successive, non-sequential words.

13. A system as claimed in claim 12, wherein the temporary store comprises a plurality of RAMs, first ones of said RAMs converting the successive sequential words to non-sequential words still in parallel bit form, and second ones of said RAMs converting the successive words into serial bit form.

14. A system as claimed in any one of claims 1 7, 11, 12 or 13, wherein the detector means includes a concealer for concealing data which cannot be corrected.

15. A system as claimed in claim 14, wherein the concealer includes a summing device for substituting portions of adjacent words to conceal the detected drop out.

16. A system as claimed in claim 15, wherein the summing device is adapted to select words in relationship to the original data sampling rate.

17. Asystem as claimed in claim 14,15 or 16, wherein a control device is provided adapted to decide whether the corrector or concealer should be inhibited or overridden dependent on the coding errors detected.

18. a system as claimed in claim 17, wherein the control device includes a read only memory programmed with decision outputs dependent of the locations accessed as a result of the incoming coding information.

19. A digital data manipulation system for compensating for drop outs on a video recording medium substantially as described herein and with reference to the accompanying drawings.