GB2083963A - Fibre optic receiver - Google Patents

Abstract

In a fibre optic receiver of the type comprising a photodetector, a. preamplifier, a postamplifier and a voltage comparator for quantizing the output to a logic level signal, a symmetrical clamp is interposed between the postamplifier and the voltage comparator. <IMAGE>

Description

SPECIFICATION Fibre optic receiver Data bus applications for fibre optics normally require optical receivers which provide large instantaneous dynamic range capability. Conventional receiver designs for point-to-point links are generally inadequate for these applications since their automastic gain control (agc) function takes too long to respond to large changes in received optical power level, and their ac coupling prohibits fast adaptation to changes in average optical power level. Herein is described a novel receiver design which addresses the problems that are unique to fibre-optic data buses and will service any link in which the data format restricts the maximum pulse width to no more than a few bit-times. The dc content of this data need not be restricted by scrambling or other techniques.The circuitryis simple and eliminates the need for complicated automatic gain or threshold circuitry. Receiver sensitivities can be achieved which are within 2 to 3 dB of what can be achieved for point-to-point, continuous data receivers. The term sensitivity is defined as the average optical power level at which the bit error rate is 10-9.

Figure 1 illustrates two typical bus architectures.

Each receiver on a bus must be capable of faithfully detecting data transmissions from any transmitter on the bus. In some cases, it may have to receive transmissions from its own terminal transmitters.

The optical power level that a receiver will receive from a given transmitter will depend upon the output power from the transmitter and the losses that exist between the transmitter and receiver. These losses may vary by as much as 20 to 30 dB. Figure 2 illustrates the optical signals that a receiver might see. The power level from one transmitter is much larger than that from another transmitter. The data message from the second transmitter will immediately follow that from the first transmitter. If the receiver cannot respond fast enough to receive the second message, the bus protocol will have to be such that the intermessage gap time (IGT) will have to be longer. This would mean that the bus will be less efficient.The dynamic range capability of the receiver will be referred to as the optical signal range (OSR) which is defined as -10 log P,/P2 (dB) where P, and P2 are the average signal powers of a first signal (P,) and a second signal (P2). Conventional accou- pled receiver designs are not capable of delivering the OSR and IGT performance that is required in most fibre optic data buses. The transient response of an ac coupled receiver is shown in Figure 3. When the average signal power increases or decreases instantaneously, it takes a finite amount of time for the analog output of the receiverto restore the signal to a level that can be detected by a threshold detector (such as a voltage comparator).

Prior receiver designs have been proposed and tested which address these problems, but they have sacrificed receiver sensitivity and/or circuit simplicity. For instance, improved agc circuits which have been designed for rapid response have become very complex. Straight ac coupled receivers sacrifice sensitivity as their response time is made smaller.

It is an object of the invention to provide a fibre optic receiver having the ability to respond to larger changes in the power levels of received signals within a few bit times.

It is another object of the invention to provide a fibre optic receiver wherein a minimal degradation in receiver sensitivity is incurred relative to known receivers for continuous data communications.

Yet another object is to achieve the above objectives utilizing a simple circuit and wherein the dc component of the received signal is not restricted.

The design that is discussed herein takes advantage of the fact that most data bus protocols use data formats that restrict the maximum pulse length to two bit times or less. This usually means that a Manchester or delay code is used which gives a lot of timing information along with the data. The design of the present invention can also be used for point-to-point links in which similar codes or returnto-zero (RZ) formats are used. In the latter case, the link can handle data in which the pulses can occur at any rate, thus allowing a dc to X bit-rate link.

The agc circuit of a conventional receiver is replaced by a circuit which operates as a symmetrical clamp. This overcomes the problem of excessive response times since the symmetrical clamp is not subject to the slow response times of known agc circuits.

Fig. 1 illustrates generally "T" and "Star" data bus cofigurations.

Fig. 2 illustrates the significance of inter-message dynamic range.

Fig. 3 illustrates an alternating current coupled signal shift.

Fig. 4 is a functionai diagram of a symmetrical clamp fibre-optic receiver.

Fig. 5 is an equivalent circuit diagram for the receiver at Fig. 4.

Figs. 6 (a) and (b) respectively illustrate waveforms at the post amplifier output and the clamp outlet.

Fig. 7 is a functional diagram of a feedback symmetrical clamp.

Fig. 8 is a circuit diagram for a two-stage cascaded feedback implemented clamp.

Fig. 9 is a representation of the respective preamp output, output of the final symmetrical clamp and the TTL waveform at the output of the voltage comparator.

Figure 4 shows a simple, functional diagram of a receiver incorporating the invention. It differs from conventional designs in that agc circuits are replaced by a symmetrical clamp. The receiver consists of a photodetector (pin photo-diode or avalanche photodiode, APD), low-noise preamplifier (which normally determines the sensitivity of the receiver), a linear postamplifier, the symmetrical clamp, and a voltage comparator which quantizes the signal to a logic level signal.

The schematic in Figure 5 is an equivalent circuit of the symmetrical clamp. The received signal at the output of the postamplifier is represented by vj. The output impedance of this amplifier is represented by Rs, the diode resistance of D, by Rids" the diode resistance of D2 by Rds2, and the output or load resistance byre.

When a large power level signal followed by a small power level signal is received, the waveform at vj may resemble Figure 6A. From t" tot1, no signal is present and v consists of the noise that is generated in the preamplifier. If this were just applied to the symmetrical clamp, the voltage comparator (shown in Figure 4) would quantize the noise and the output data from the receiver would be rubbish. The resistor Rg and voltage -VB supply a small bias current to the clamp which biases D2just into conduction. This voltage -v,2 is below the threshold level of the voltage comparator and therefore keeps the comparator output at zero.At t1, v1 goes positive which takes D2 out of forward bias and the diodes are effec tiveiy out of the circuit during the period prior to the time at which vj exceeds Vf1 due to their large impedance when not biased into conduction. H0 is very large compared to R5 and Xc; thus to follows v1.

When vj reaches the forward bias voltage of Dl (if,), Cl charges through Rdsl and Rsto (Vi-Vf1). The time constant, C1 (Rdsl + Ras), and the rise time of vi determine how long this takes. The output voltage (vO) resembles Figure 6b.Att2, when the voltage across C1 equals (v1 - if1), D, ceases to be forward biased and C, charges through R0 since the impedance of D, is then much larger than RO. RB is typically much targer than RO and can be made much larger than R5 + Rods;; thus the decay in to between t2 and t3 is very small compared to the sum of the forward turn on voltages of D1 and D2 (vet, + Of2). At tor V1 returns to zero, v0 follows vi until D2 becomes forward biased and C, discharges through R5 and Rod52 until the voltage across C, equals (vj + v,2). At this time D2 is biased by the current through Re and V0 equals -Vf (where vf = v,t = van).

When a small signal is received at time t4, vO fol- lows vj. vj never reaches the forward turn on voltage (Vf) of D, and v0 is not clamped. Since H0 is very large, the waveform droops slightly between t4 and t5.

When vi goes negative at tS, D2 becomes slightly forward biased in order to make up for the small amount of charging of C, between t4 and tS. The net effect of this performance is to allow to to recover quickly from very large input signals so that the circuit is ready to detect signals whose power level is at the sensitivity point of the receiver. The clamp causes little distortion in the pulse shape for small signals and distorts the amplitude of large signals to be the same as that of small signals without distorting the pulse width. The small amount of distortion of the small signals permits utilization of the maximum sensitivity available from the preamplifier.

The gain of the preamplifier and postamplifier should be such that a signal at the sensitivity point is amplified to a point whereby D, and D2 are just barely driven into forward bias at the signal peaks.

The circuit values for R,, Rds, C1, and RO should be optimized for the desired performance. Generally, the value of R5 and Rds should be kept as low as possible. The capacitance of C, should be kept as low as possible while keeping the time constant of RoC long compared to a bit time so that it contributes little to the degradation in sensitivity performance.

The circuit described above is used to help explain the circuit theory; however, in practice, the dynamic range required from the postamplifier in the circuit of Figures 4 and 5 is unrealistic. The circuit in Figure 7 solves this problem by putting the diodes in a feedback arrangement, which is termed a feedback complimentary clamp. This restricts the output voltage from the postamplifier to 2v: whiie providing the aforementioned circuit performance. Also, several stages of clamping may be used as in Figure 8 to increase the OSR and decrease the required dynamic range in any one amplifier.

The symmetrical clamp technique described here is particularly useful for fibre optic data bus receivers. It is also very attractive for HZ and Manchaster code point-to-point links. The circuit may also be useful in atmospheric optical links and in wire systems.

While we have described above the principles of our invention in connection with specific apparatus, it is to be clearly understood that this description is made only by way of example and not as a limitation to the scope of our invention as set forth in the objects thereof and in the accompanying claims.

Claims (10)

1. In an optical receiver of the type comprising a photodetector, an amplifier and means for quantizing the output to a logic level signal, the improvement comprising: complimentary clamp means interposed between said amplifier and said means for quantizing.

2. In an optical receiver as described in claim 1 the improvement wherein said complimentary clamp means comprises: first and second diodes, oppositely oriented, connected in parallel between a first node and a second node, said second node maintained at a reference potential, a capacitor having a first terminal connected to said first node, and a second terminal for connection to the output of said amplifier, said first node connected to the input of said means for quantizing.

3. In an optical receiver of the type comprising means for detecting a digitized optical signal, means for producing an electrical signal corresponding to said optical signal, means for amplifying said electrical signal and output means for providing a digital outputthe improvement comprising: complimentary clamp means associated with said output means.

4. In a fibre optic receiver as described in claim 3 the improvement wherein said clamp means comprises: first and second diodes, oppositely oriented, connected in parallel between a first node and a second node, said second node maintained at a reference potential, a capacitor having a first terminal connected to said first node, and a second terminal for connection to the output of said means for amplifying, said first node connected to the input of said output means.

5. In a fibre optic receiver as described in either of claims 1 or 3 the improvement wherein said clamp means clamps the electrical signal at a voltage level slightly above the minimum signal consistent with the sensitivity of the receiver.

6. The optical receiver as described in either claim 2 or4furthercomprising: a resistor having one terminal connected to said first node, voltage source having a positive and a negative terminal, said positive terminel connected to said second node, a second terminal of said resistor connected to said negative terminal of said voltage source.

7. A fibre optic receiver comprising: means for producing an electrical signal corresponding to a received optical signal, means for amplifying said electrical signal and producing an amplified signal, means for clamping said amplified signal, and producing a clamped signal, means for producing a digital output signal from said clamped signal.

8. An optical receiver of the type comprising a photodetector, an amplifier and means for quantizing the output to a logic level signal, the improvement comprising: a feedback complimentary clamp.

9. In an optical receiver as described in any of claims 1,3 or 7 the improvement wherein two stages of clamp means are cascaded.

10. A receiver substantially as hereinbefore described with reference to the accompanying drawings.