GB2081553A - Improvements in or relating to interface units for connection between PCM systems and time division circuit arrangements - Google Patents

Abstract

The transmitting section CT of an interface unit UL receives data DE frames to be sent to a PCM line from a time-division circuit arrangement or terminal T, and replaces, in each frame, the channel O containing terminal-to-interface instructions with the configurations required by the PCM standards and known as word A and word B. The receiving section M1, DEC, EC, TR, ITD extracts the receiving clock CKL from the bit flow received from the line PCM, effects frame alignment and sends the data channels DT and their respective addresses IT timed by the terminal clock to the terminal T by way of elastic memories ME. Upon control by the terminal, the transmitting section forms a loop with the receiving section at the line interface level and the channel O of each frame is used by the interface unit as a service channel toward the terminal. <IMAGE>

Description

SPECIFICATION Improvements in or relating to interface units for connection between PCM systems and time division circuit arrangements The present invention relates to an interface unit for connection between a PCM system and a time-division circuit arrangement which is generally referrred to as a terminal hereinafter.

Among telecommunication systems, those comprising transmitting means of digital type independently of the (analog or digital) kind of information to be transmitted are becoming increasingly important and widly used.

Between the terminal and the apparatus of the transmitting system proper (e.g. a PCM system), some circuits generally termed interface units are usually provided which transform the data generated by the terminal in conformity with the standard requirements for the transmitting system used, or alternatively operate on the data received from the transmitting system so as to allow the terminal to receive them correctly.

Interface units connected to a PCM system and arranged to receive from the line a signal timed by the transmission clock and to transmit the signal timed by the terminal itself back to the terminal together with -the channel addresses, are known in the art. Such interface units receive in the opposite direction, from the terminal, a bit flow by means of which they form a standardized PCM signal.

According to the invention, there is provided an interface unit for connection between a PCM system and a time-division circuit arrangement (referred to as a terminal hereinafter), comprising: a transmitting circuit arranged to receive data to be transmitted and a transmission clock from the terminal, to form and insert the word A or B required by international standards in channel 0 of each frame, to code the data thus modified before sending to the line, and to detect a loop instruction by generating a loop signal or the instruction to form and send remote control messages to the line in the channel 0 of the data to be transmitted; a first multiplexer arranged to be controlled by the loop signal and having a first input connected to the output of the transmitting circuit and a second input arranged to be connected to a line interface of the PCM system;; a decoder connected to the output of the first multiplexerl a circuit arranged to extract the line clock from the data coming from the PCM system; a first timing circuit arranged to receive the line clock and the decoded data, to associate an address with each respective channel of the PCM frame, to generate a writing signal, to detect loss of frame synchronization by generating an alarm signal to be sent to the transmitting circuit and the terminal, to detect malfunctioning conditions in the PCM connection and in the interface unit by sending a plurality of alarm signals to the terminal, and to generate an alarm signal to be sent to the remote terminal;; a channel forming circuit arranged to be timed by the timing circuit and arranged to generate messages to be inserted in the channel 0 of each frame of decoded data to be sent to the terminal, and q an elastic memory arranged to store the data generated by the forming circuit and the addresses associated therewith in response to the writing signal, to send the data and addresses to the terminal in response to a reading signal generated by the terminal, and to generate a signal for informing the terminal when a "slip' occurs.

It is thus possible to provide an interface unit having functions which are not normally available in conventional interface units. Such an interface unit "dialogues" with the terminal in the channel 0 of each PCM frame. More precisely, the terminal can send instructions to transmit line messages having characteristics required by the remote control circuits with which the PCM system is equipped, as well as instructions to loop before the line interface.

Terminal alarms concerning malfunctioning conditions in the PCM connection (loss of synchronization, excessive error rate, etc.) can be detected and messages can be sent to the remote terminal to signal that an alarm has been detected, or a loop has been formed or a remote control procedure has been started.

Such an interface unit can be advantageously used together with any terminal. The interface unit, however, can advantageously act as an interface between a PCM system and a timedivision exchange for switching PCM channels, in particular a buffer exchange in a network designed to effect integrated switching of telephone signals and data signals. Such a buffer exchange is described, for instance, in the Italian Patent No. 1037256.

The present invention will be further described, by way of example, with reference to the accompanying drawings, in which: Figure 1 shows a block diagram of an interface unit constituting a preferred embodiment of the present invention; Figure 2 diagrammatically shows a block ITO of Fig. 1; Figure 3 illustrates a modification of the arrangement shown in Fig. 1 to provide an interface unit suitable for operating together with two terminals (T1, T2) operating according to a masterslave procedure; and Figure 4 shows a circuit designed to detect the phase difference between a line clock and a terminal clock.

Fig. 1 is a block diagram of an interface circuit UL constituting a preferred embodiment of the present invention.

A transmitting section comprises a transmitting circuit CT arranged to receive data DE to be transmitted and the transmission clock CKT from a terminal T, to enter in channel 0 of each frame the configuration required by international standards (word A or B) before data coding, and to send an output signal SU thus obtained to a line interface IL of a PCM system.

The transmitting circuit CT is arranged to detect a possible loop control in the channel 0 of the data DE to be transmitted, by generating a signal L, or a possible control signal to be sent to the remote control message line, by suitably modifying the code adopted for generating an output signal, A remote terminal is informed about both events (loop or remote control) by means of the word B.

In a preferred embodiment, the terminal T controls, by means of a control signal S, the code normally used by the transmitting circuit CT. Moreover, the transmitting circuit CT can signal under control of the terminal T, the loop state to the remote terminal by imposing a constant logic value to all the bits sent to the line. A transmitting circuit CT capable of performing the functions mentioned above is described for instance in Italian patent application No.23105 A/80 filed on 30 June 1980.

The receiving portion of the interface unit UL receives, from the PCM line by way of the line interface IL, the PCM signal SE which is supplied to an input of a first multiplexer M1 controlled by the loop signal L and whose second input is connected to the output SU of the transmitting circuit CT.

The signal SE (SU in the case of a loop) is decoded and the signal DD thus obtained is processed together with the line clock CKL by a timing circuit TR.

In the drawings, a clock extracting circuit EC arranged to obtain a line clock CKL is connected upstream of a decoder DEC. However, it is possible to obtain the line clock CKL from the decoded data DD.

The timing circuit TR performs essentially the following functions: it obtains the group timing from the line clock CKL by allocating a respective address I to each channel of the PCM frame and generating the writing signal W for an elastic memory ME; it detects less of frame synchronization and informs, by means of a signal FAT, the terminal T and the transmitting circuit CT which, in turn, informs the remote terminals; it detects and signals to the terminal T, by means of a plurality of signals generally indicated by ALL in the drawings, malfunctioning conditions in the PCM connection or in the interface unit UL ( e.g. an eccesive error rate, non-detection of the synchronization word A, etc.) as well as the alarm signal ATL sent by the remote terminal.

An embodiment of a timing circuit TR designed to perform the above mentioned functions is described in Italian patent application No.23104 A/80 filed on 30 June, 1980, in which the addresses I and the reading signal W are not specifically indicated as they are included in the timing signal CK.

As mentioned above, the channel 0 of each frame is used by the interface circuit UL as a service channel to signal, to the terminal T, alarm signals detected by the timing circuit TR as well as a possible slip in the elastic memory ME. Thus, the interface unit UL comprises a channel forming circuit ITO arranged to insert into the channel 0 o each frame of the decoded data DD, the messages to be sent to the terminal T before sending the frames thus modified, generally indicated by DL in the drawings, to the elastic memory ME.

According to the diagram of Fig. 1, the forming circuit ITO (illustrated in Fig. 2) is timed by the timing circuit TR from which is also receives alarm signals ALL and FAT, and alternatively generates two messages having, for instance, the following formats: FRAME A X O Y, Y2 Y3 Y4 Y5 Y8 FRAME B X 1 FAT SL X X X X where the bits X are transparent (i.e. they maintain the logic values they have in the data DD), Y1 to Y6 contain the information on the alarms ALL, and SL informs the terminal T that a slip will occur in the frame or biframe (frame A + frame B) of the data DD.

However, it is possible to send the alarm signals ALL directly to the terminal T by using the bits Y, to Y6 for transmitting further information or by adopting a single format, e.g. similar to that specified above for the frame B, in all the frames for the channel 0. It is also possible to cause the forming circuit to generate more than two messages.

The line data DL at the output of the forming circuit ITO are sent, together with their respective addresses I, to the elastic memory ME (comprising a memory for the data MED and a memory for the addresses MEI) in which they are written in response to a writing signal W generated by the timer TR and controlled by the line clock, the line data being read by a reading control signal R which the terminal T obtaines from its internal timing. The output data DT and the addresses IT from the elastic memory ME are then synchronous with the timing of the terminal T.

Elastic memories have been and still are widly used in synchronous data transmitting systems.

Thus, they are well known in the art and also well known in the procedure termed "slip" used for compensating for the effect due to differences between the writing and reading clocks.

Italian patent No.1043981 descloses an elastic memory in which data are written and read in parallel alternately in two similar registers. A logic circuit controls the "slip", i.e. the writing signal exchange when coincidence is found between the reading pulses concerning one register and one of the two control pulse sequences which respectively precede or follow the reading pulses concerning that particular register by sufficient time to permit all the contents of the register to be read before a new writing operation or, respectively, to be written before a new reading operation.

In a preferred embodiment, the elastic data memory MED and address memory MEI are similar to the arrangement disclosed in the patent referred to above and comprise four registers cyclically written or read, each register having a capacity of one channel or one address.

The two memories are timed by the same timing circuit and controlled by the same logic circuit which controls the "slip" when the reading timing has slipped with respect to the writing timing by about 1 6 bits. Recovery of a correct reading-writing relationship is obtained by suppressing (or reading a second time after the channel 3) the channel 0 for two successive frames. Upon control by the terminal T, the amplitude of the margins taken by the logic circuits can be halved and the channel 0 sup suppressed or repeated only once.

Fig. 2 shows a possible embodiment of the forming circuit ITO which comprises a series-toparallel converter SP arranged to receive decoded data DD controlled by a line clock CKL (or a clock strictly related to it). The clock is sent by the timing circuit TR together with a signal To designed to identify the channel 0 and a signal ST designed to identify the frame (A or B). The forming circuit further comprises a multiplexer M2 controlled by the signal To and the signal ST and arranged to form, in the channel 0, the messages previously indicated, whereas it allows the output data from the series-to-parallel converter SP to pass through.

The multiplexer inputs are connected to the converter SP, the timer TR (FAT, ALL) and the slip control circuit of the elastic memory (SL). The output DL is connected to the elastic memory ME to which it sends the bits of each channel in parallel. Should the forming circuit ITO generate sequentially three or more messages, the frame is identified by two or more bits of the signal ST.

The processing and/or operating units are quite often duplicated and operate according to the master-slave procedure to attain better reliability of the system and to assure service continuity.

With minimum variations indicated in Fig. 3, the unit UL can form the interface between a PCM system and the two terminals T1 and T2. To this end, it is sufficient to add a second forming circuit and a second memory ME2 identical to and in parallel with a forming circuit ITO and the memories ME (MED, MEI) of Fig. 1. Data ( DL1, DL2) and the addresses I are written by the writing signal W (or group of signals) in both memories ME1, ME2. Each memory has a respective slip centrol circuit and is connected to a terminal from which it receives reading controls R1, R2 and to which it sends data DT and their respective addresses IT.The input data and the transmission clocks (DE1, CKT1; DE2, CKT2) are connected to the inputs of a third multiplexer M3 controlled by the master-slave control signal M/S and arranged to generate the data signal DE and the timing signal CKT to be sent to the transmitting circuit CT.

The messages sent to the channel 0 by the forming circuits ITO differ only in respect of the slip information SL each forming circuit receives from the memory with which it is associated.

Should such information SL not be required, SL1 = DL2 = DL and the second forming circuit is unnecessary.

According to a possible embodiment of the invention, the interface unit is arranged to communicate to the terminal T the jitter between the line clock CL and the transmission clock CKT independently of the slip. To this end, it is possible at least partly to use, for example, the bits Y1 to Y6 of the message inserted in the frameA by the circuit ITO.

Fig. 4 shows a particularly simple embodiment of a circuit arranged to measure the jitter or phase displacement. Such a circuit comprises a counter C which is enabled to count by a signal MT (generated by the transmitting circuit CT or the terminal T and controlled by the transmission clock CKT) and is stopped by a signal ML generated by the timer T and related to the line clock CKL. By suitably choosing the frequency of the signal F which causes the counter C to step forward, and the signals ML and MT, the bits indicating the jitter can be extracted in parallel from the cells of the counter itself.

By way of example, the case in which the reading signal of one of the four registers forming the data memory MED is used as enabling signal MT, and in which the writing signal for the same register is used as a stop signal ML, and in which the signal F has a frequency double than that of the bit rate, will be briefly described below. If the two clocks CKL and CKT are mutually in phase, the writing signal is to be found in the middle of the interval (32 bits) between two successive reading signals and the counter C counts 32 pulses.

With the above arrangement the counter C counts a number of pulses in any case. The terminal T considers the line clock CKL in advance or with a delay with respect to its internal clock CKT depending upon whether the counter pulses are more or less than 32.

Without departing from the scope of the present invention, the signals MT and ML can mutually exchange their functions.

Claims (11)

1. An interface unit for connection between a PCM system and a time-division circuit arrangement (referred to as a terminal hereinafter), comprising: a transmitting circuit arranged to receive data to be transmitted and a transmission clock from the terminal, to form and insert the word A or B required by international standards in channel 0 of each frame, to code the data thus modified before sending to the line, and to detect a loop instruction by generating a loop signal or the instruction to form and send remote control messages to the line in the channel 0 of the data to be transmitted; a first multiplexer arranged to be controlled by the loop signal and having a first input connected to the output of the transmitting circuit and a second input arranged to be connected to a line interface of the PCM system; a decoder connected to the output of the first multiplexer;; a circuit arranged to extract the line clock from the data coming from the PCM system; a first timing circuit arranged to receive the line clock and the decoded data, to associate an address with each respective channel of the PCM frame, to generate a writing signal, to detect loss of frame synchronization by generating an alarm signal to be sent to the transmitting circuit and the terminal, to detect malfunctioning conditions in the PCM connection and in the interface unit by sending a plurality of alarm signals to the terminal and to generate an alarm signal to be sent to the remote terminal; a channel forming circuit arranged to be timeed by the timing circuit and arranged to generate messges to be inserted in the channel 0 of each frame of decoded data to be sent to the terminal;;and an elastic memory arranged to store the data generated by the forming circuit and the addresses associated therewith in response to the writing signal, to send the data arid addresses to the terminal in response to a reading signal generated by the terminal, and to generate a signal for forming the terminal when a "slip" occurs.

2. An interface unit as claimed in claim 1, in which the alarm signals generated by the timing circuit and the signal generated by the elastic memory are directly sent to the terminal.

3. An interface unit as claimed in claim 1, in which the alarm signals generated by the timing circuit and the signal generated by the elastic memory are sent to the forming circuit which is arranged to transmit the said signals to the terminal by means of messages inserted in channel 0 of each frame.

4. An interface unit as claimed in claim 1 or 3, in which the forming circuit comprises a series-to-parallel converter connected to the output of the decoder and arranged to be timed by the line clock, and a second multiplexer which has inputs connected to the series-to-parallel converter for generating the massages to be sent to the terminal in response to a signal generated by the timing circuit during the channel 0 of each frame, the outputs of the second multiplexer being connected to the elastic memory.

5. An interface unit as claimed in claim 4, in which the forming circuit is arranged to generate sequentially at least two types of message in response to a signal generated by the timing circuit for controlling the second multiplexer.

6. An interface unit as claimed in any one of the preceding claims, further comprising means 3rranged to detect the magnitude of jitter between the line clock and the transmission clock and co signal detected jitter to the terminal by way of the forming circuit.

7. An interface unit as claimed in claim 4 or 5 in claim 6 when dependent on claim 4, in which the jitter detecting means comprises a counter arranged to be enabled to count or be stopped by a first signal related to the line clock and to be stopped or enabled to count, respectively, by a second signal related to the transmission clock, the output of the counter being connected to the second multiplexer.

8. An interface unit as claimed in claim 7, in which the counter is arranged to count a oredetermined number of pulses when the two clocks are in phase, a biunivocal correspondence exting between the number, either greater or smaller than the predetermined number, of counted pulses and the one of the two clocks which is in advance with respect to the other.

9. An interface unit as claimed in any one of the preceeding claims for connection to two terminals operating according to master-slave procedure, comprising a second forming circuit in parallel with the said torming circuit and the elastic memory, which is arranged to be controlled by a reading signal generated by the two terminals, and having an output connected to the transmitting circuit.

10. An interface unit substantially as hereinbefore described with reference to and as illustrated in the accompanying drawings.

11. A PCM time division multiplex terminal including an interface unit as claimed in any one of the preceding claims.