GB2078409A - Digital timing system - Google Patents

Abstract

A system suitable to set spark timing in accordance with engine speed includes a counter (14) to count clock pulses between engine speed reference pulses. A read-only memory (36) has successive memory locations, each storing an addend quantity and a repeats number. An adder unit, including an accumulator (24) operates to add the addend quantities to the contents of the accumulator repeatedly a number of times equal to the respective repeats numbers. A comparator (22) produces an ignition firing pulse when the content of the accumulator corresponds to the reference period number provided by the counter. Memory addressing means (57, 62, 65, 74, 75, 42) is adapted to altering the spark advance in accordance with a sensed condition, such as manifold vacuum, and to conserving memory space. <IMAGE>

Description

SPECIFICATION Digital timing system This invention is directed to producing an output pulse at a time which is a function of the time period between two input pulses.

The invention is particularly useful in a digitial timing system which determines spark advance according to speed of an internal combustion engine.

The timing of the electrical spark in the spark plug of an internal combustion engine is varied, relative to the time the piston is at top dead center, in accordance with engine speed.

The spark advance is increased as engine speed increases. In the past, the increase in spark advance with engine speed has been accomplished mechanically in the distributor by centrifugal means including springs and cams. Recently, the determination of spark advance in accordance with engine speed has been accomplished by electronic means including means for sensing engine speed, and a small computer for computing the proper spark advance at the sensed engine speed.

Even though small computers can be made inexpensively by techniques of large scale integration, there is a powerful competitive necessity to make automotive components as inexpensive as possible. Accordingly, there is a need for a special-purpose electronic digital timing system, useful for spark advance determination, which is less expensive in large quantities than a system including a general purpose microcomputer.

The present invention is used to produce an output pulse (such as may be used to direct firing of an engine spark plug) at a time which is a function of a time period occurring between two input pulses (each of which may mark the occurrence of top dead center of a respective engine cylinder). According to the invention, a counter counts the number of clock pulses from a clock pulse source, where the counting takes place during the time period between the two input pulses; adder / accumulator means repeatedly adds an addend quantity, where that quantity is applied to the adder accumulator means by an addend source; and a comparator, which is coupled to receive the count from the counter and the sum from the adder/accumulator means produces the output pulse when the sum in the adder/accumulator means equals to counted number of clock pulses.

As is brought out in the description which follows, this invention is particularly useful where, in a spark control system, an addend quantity is supplied from one or more tables of such quantities stored in respective locations of a read only memory, and where such a memory location is accessed (to supply the required quantity) as the engine is operated.

In the drawings: Figure 1 is a simplified block diagram of an illustrative timing system constructed according to the teachings of the invention; Figure 2 is a chart showing an example of desired spark advance in crankshaft degrees for various values of engine speed in revolutions per minute; Figure 3 is a chart which will be referred to in describing the operation of the timing apparatus of Fig. 1 in providing the exemplary desired spark advance timing shown in the chart of Fig. 2; and Figure 4 is a table of values corresponding with the example illustrated by the charts of Figs. 2 and 3.

In the description of Fig. 1, it is assumed for purpose of explanation that an engine is being operated at a constant speed. The engine's distributor 1 5 supplies on 1 6 a stream of reference pulses marking respective occurences (for example the time location of top dead center for respective engine cylinders).

In this example, the first-occurring of every two observed pulses marks engine crank shaft movement to top dead center of a first of the cylinders and the second observed pulse marks crankshaft movement to top dead center of the next crankshaft-order cylinder. The spacing of these pulses is inversely proportional to engine speed. Hereinafter, the pulses are referred to as engine speed pulses or input pulses.

In Fig. 1, clock 10 has an output 12 providing pulses at a frequency of 1 MHz (a period of 1 ys) which is connected to the signal input of a period counter 1 4. The counter 1 4 is reset via delay means D every time an engine speed reference pulse is received on input terminal 1 6 from the ignition distributor 15.

The counter 1 4 continues counting until a next input pulse is received at 1 6 and enables an "and" gate 1 8 to transfer the count in counter 1 4 to a period register 20. After a slight delay provided by delay unit D, the input pulse produces a reset signal RESET which resets the counter 14 so that it can count the time period to the next following input pulse while the count reached during the iast period is retained in period register 20.

The engine speed reference period between input pulses from the distributor depends on the speed of the engine in revolutions per minute (RPM), the number of cylinders of the engine, and whether the engine is a fourcycle, or a two-cycle engine. In the case of a four-cycle, four-cylinder engine, the reference period P in microseconds (ys) is equal to 30,000,00 . RPM of the engine. The periods P at six different values of RPM are given in the table of Fig. 4. The number of onemicrosecond spaced clock pulses counted by counter 1 4 between two successive period reference pulses from input terminal 1 6 repre sents the reference period in microseconds at the existing engine speed.

The number in the period register 20 is continuously compared in period count com parator 22 with the number in an adder/accu mulator 24. The number in 24 is produced by adding the number in an addend register 26 to the previous number in 24 every time one of the 1 6-microsecond-spaced clock pulses from clock 10 is applied over line 28 to enable an "and" gate 30. The addend register 26 is loaded over bus 32 from a read-only member 36 at the same time that a repeats register 38 is loaded over bus 40 from the memory. The number supplied to addend reg ister 26 and the corresonding number sup plied to repeats register 38 come from a memory 36 location having the address contained in a presetable memory address counter 42.For the present, registers 26 and 38 are assumed to contain numbers of appropriate value.The manner in which the contents of respective locations in memory 38 are read out (in the process of placing those numbers in 26 and 38) is made apparent in the expianation which follows.

The apparatus of Fig. 1 includes means for jam transferring (jamming) new addresses into the memory address counter 42. A first address may be supplied from a vacuum transducer 57, through an analog-to-digital converter 62 and a jam address multiplexer 65 to the memory address counter 42, when enabled by a reset pulse. Thereafter, the address in counter 42 is incremented by an incrementing signal from a repeats comparator 44, For reasons to be established later in this description, the accessing of numerically sequential memory locations may be interrupted by the accessing of a memory location containing a jump command and a new address anywhere in memory.The jump command is recognized by a jump decoder 74 which provides a signal through "or" gate 75 and line 77 to enable counter 42 to receive a new jumper-to address via bus 32, bus 76, multiplexer 65 and bus 43.

The number in the repeats registers 38 is continuously compared in the repeats comparator 44 with the count in a repeats counter 46 which counts the sixteen-microsecondspaced clock pulses on line 28 from clock 1 0.

When an equality is detected, the repeats comparator 44 increments the count in the memory address counter 42, and resets the repeats counter 46 over path 45, and supplies a control signal over path 47 to a memory access control unit 49, so that the memory 36 is caused to supply new numbers to the addend register 26 and repeats register 38.

When the number in the adder/accumulator 24 equals or is greater than the number in period register 20, the period count comparator 22 provides an output signal at 48 through a multiplexer 85 to an ignition pulse generator 50 to control the leading edge and duration of an ignition pulse applied over path 52 to spark plugs (not shown). If for any reason the period count comparator 22 does not provide a spark advance timing signal at output 48, a time-out circuit 80 acts through line 83 to cause a spark timing signal without advance to be supplied from reference pulse source 1 5 over lines 1 6 and 97 and through multiplexer 85 to the ignition pulse generator 50.

Fig. 2 is an example of desired amounts of spark advance in crankshaft degrees for engine speeds between 1,000 rpm and 7,000 rpm. Specific points on the curve A on the chart are labeled by circled numbers zero through 5 to identify correspondingly-labeled points in the chart of Fig. 3 and the table of Fig. 4. The value of RPM at the identified points in Fig. 2 are translated to corresponding values of reference interval or time period in Figs. 3 and 4. The time period P between ignitions in a four-cycle, four-cylinder engine is given by P = 30,000,000 . RPM, where P is time in microseconds. For example, an engine speed of 1,000 rpm corresponds with an ignition reference period of 30,000 ys, or the time required to count 30,000 pulses of one-megacycle clock.

The crankshaft degrees of spark advance in Fig. 2 can be translated to the time domain by the formula A = crankshaft degrees .

1 80 times P, where A equals spark advance in microseconds. The values of spark advance in terms of degrees and the corresonding values in microseconds are given in the table of Fig. 4.

In Fig. 3, the ordinate is marked with the five values of RPM, from Fig. 2, and the corresponding values of reference time period in terms of a count of one-microsecondspaced clock pulses. The abscissa is marked with the same five values of time in microseconds. The operation of the apparatus of Fig. 1 will be described with reference to Fig.

3. The operation will be understood if it is remembered that the output 1 2 of clock 10 in Fig. 1 provides high-frequency pulses having a period of one microsecond, and that the output 28 of clock 10 provides sub-multiple frequency pulses having a period of sixteen microseconds. The count in period counter 1 4 increases by one every microsecond, and the output of adder/accumulator 24 increases by the amount in the addend register 26 every sixteen microseconds. If the number sixteen is in the addend register, the output of the adder/accumulator reaches the number stored in the period register 20 in the same number of microseconds as were required by the period counter to count to the number latched in the period register.If the number in the addend register is greater than sixteen, the output of the adder accumulator will reach the count latched in the period register in a shorter time. This shorter time is made to be the time to start the spark in the engine to provide a desired amount of spark advance for the speed of operation of the engine.

The operation of the basic apparatus is next described for the condition represented by point 4 in Figs. 2, 3 and 4. Under this condition, the engine is operated at a speed of 4,882 rpm, and the engine speed reference period between two successive pulses at 1 6 from the distributor is 6,145 microseconds.

During this reference time period, counter 14 counts to 6,145, and this count is transferred to, and stored in, the engine period register 20. It is known from Fig. 2 that at the 4,882 rpm engine speed, the spark advance should be 40 degrees. It is known from Fig. 4 that a 40 degree spark advance is equal to 1,365 microseconds, and that the spark should occur at a time of 1,365 microseconds before an engine period reference pulse, or 4,780 microseconds after an engine period reference pulse. The engine period reference pulses are spaced 4,780 + 1,365 = 6,145 microseconds. This is illustrated in Fig. 3 by the time of 4,780 ys to point 4, and the time of 1,365 ,us between points 4 and 4', and the total time to point 4' of 6,145 ys.

In operation, a spark fire signal is generated by period count comparator 22 when the output of adder/accumulator 24 equals the count previously transferred to period register 20 and which represents the 6,1 45 microseconds period between input pulses at an engine speed of 4,882 rpm. The output of the adder/accumulator 24 reaches the count of 6,145 after only 4,780 microseconds because of the value of the addend which is supplied to the addend register 26 from the read-only memory 36, and the frequency with which the addend is added to the sum in the accumulator.In the example being described, the number in the addend register 26 is added to the number in the accumulator every sixteen microseconds as determined by the output 28 from clock 1 0. Therefore, if the number in the addend register is greater than sixteen, the output of adder/accumulator 24 will reach the count in period register 20 in less than 6,145 microseconds between the period reference pulses from the distributor.

In the example, if the number in the addend register is 20.57 the output of adder/accumulator reaches the count of 6,145 after a time period of 4,780 microseconds. When this equality occurs, the output of the comparator 22 causes an ignition spark at a time providing a spark advance of 1,365 microseconds, which is equal to a spark advance of forty crankshaft degrees.

The operation is one in which during the 6,145 microsecond period between input period pulses, the period counter 1 4 counts to 6,145, and during the first 4,780 microseconds of the following period between input period pulses, the output of adder/accumulator 24 reaches the count of 6,145 to determine the time to fire the ignition. This may be visualized as a counting by period counter 14 from the ordinate in Fig. 3 to a count of 6,145 at point 4' in a time period of 6,145 microseconds, and an accumulator in adder/ accumulator 24 from the ordinate to a sum of 6,145 at point 4 after 4,780 microseconds.

The slope of the dotted line from the ordinate to point 4' is unity, and the slope of the solid line from the ordinate to point 4 is 6,145 -: 4,780, or 1.2856. The quantity in the addend register 26 should be 1 6 X 1.2856 or 20.57, and the quantity in the repeats register 38 for the number of times this quantity 20.57 should be repeatedly added in adder 24 is 6,145 . 20.57 or 299 times.

However, it is desirable to limit the size of the addend and repeats numbers to base ten numbers of 255 or less which can be represented by eight binary digits. This can be done by limiting the addend quantities to whole numbers between zero and 255, such as 20 and 21, and by limiting the repeats quantities to numbers below 256. In the example of operation at an engine speed of 4,882 rpm, the count of 6,145 can be reached by adding the number twenty-one in the adder/accumulator 57% of the time, and adding the number twenty 43% of the time.

That is, the quantity 21 is put in addend register 26 and the quantity 1 70 is put in the repeats register 38, so that the quantity 21 is added to itself 1 70 times, to reach a count of 3,570. Then the quantity 20 is put in the addend register 26 and the quantity 1 29 is put in the repeats register, so that the quantity 20 is added 1 29 times to the quantity 3,570 to reach a total of over 6,145, when an ignition spark is started.

The first storage location in read-only memory 36 contains the addend quantity 21 and the repeats quantity 170, and the storage location has the first address, which for now is assumed to be provided by memory address counter 42. When the contents of the firststorage location have been read out and are present in registers 26 and 38, then quantity 21 is added to itself 170 times in adder/accumulator 24, and the contents of repeats counter 46 is advanced to equal the contents 1 70 of the repeats register 38. At this time the repeats comparator 44 provides an output which increments by one the count in the memory address register, resets the repeats counter 46 and stimulates the memory access control 49.Then, the second storage location in read-only memory 36 is accessed and the addend quantity 20 therein is transferred to the addend register 26, and the repeats quantity 1 29 therein is transferred to the repeats register 38. Now, the addend quantity 20 is added to sum 3,570 in the adder/accumula tor, and then added another 1 28 times, until the repeats counter 46 counts up to the figure 1 29 which equals the quantity 1 29 in the repeats register 38. The repeats comparator 44 detects the equality and increments the memory address counter for the accessing of the next or third storage location in memory 36.

However, after the addend quantity 20 is added in the adder/accumulator 34 the 129th time, the output 48 of the adder/comparator equals 6,1 50, which exceeds the quantity 6,145 in the period register 20. This is recognized by the period count comparator 22, which produces an output at 48 that causes the generation of the ignition pulse with a spark advance of 1,361 microseconds or 39.9 degrees, which is close enough to the exact spark advance of 1,365 microseconds or 40 degrees, which is desired for an engine speed of 4,882 rpm.The next input pulse at 1 6 from the distributor initially transfers the 6,145 count in period counter 14 to period regjster 20 through "and" gate 18, and then the slightly delayed reset pulse RESET resets the period counter 14, the add/accumulator 24, the memory address counter 42 and stimulates the memory access control unit 49.

Then, the described procedure repeats of counting the one-microsecond-spaced clock pulses until the next input pulse is received, and adding and accumulating addend quantities from memory 36 until an equality sensed by the period count comparator 22 causes another ignition spark. The process keeps repeating exactly as described, and provides a spark advance of 1,365 microseconds, or 40 degrees so long as the engine operates at a speed of 4,882 rpm.

If, for example, the engine is operating at a speed of 1,953 rpm, corresponding with the points 3 in Figs. 2, 3 and 4, the time between input pulses from the distributor is 15,360 microseconds, and period counter 14 counts to this figure, and stores the number in period register 20 by the time the following input pulse is received. This corresponds with a movement from the origin in Fig. 3 to the circled point 3'.

During the interval until the next input pulse is received, the output of the adder/accumulator 24 increases exactly as has been described to a count of 4,780 (as the result of memory counter having accessed the first and second memory locations in 38 and the consequent performance of repeated additions of addend numbers in adder/accumulator 24).

This increase in the number in adder/accumulator corresponds to a movement from the circled point 5 at the origin in Fig. 3 to the circled point 4. Because: (a) the number in 24 does not yet equal the number in period register 20, (b) another input signal (and consequent rest signal) has not yet appeared on 16, and (c) repeats comparator 44 again has produced a pulse to increment address register 42 (which, in turn, resets repeats counter 46 and activates memory access control 49), the Fig. 1 apparatus is ready to repeat the above-described operations, but using an addend number and repeats number taken from the third location in memory 28.

The operation thus is continued using addends and repeats quantities from third and subsequent storage locations in memory 36, until the circled point 3 is reached. The slope of the line from point 4 to point 3 is 1.1 348 as shown in Fig. 4, and addends should average 1,1348 times 16 or 18.16. This is accomplished by using an addend of 1 9 sixteen per cent of the time and an addend of 1 8 eighty-four per cent of the time. The number at the output of the adder/accunnula- tor 24 reaches the number 1 5,360 in the period register 20 after a time of 1 2,902 microseconds, which is the time to start ignition when the engine speed is 1,953 rpm, and a spark advance of 2,458 microseconds, or 28.8 degrees, is desired.

If the engine speed is 1,395 rpm, the system goes through the counting and adding as described for the higher speeds, 4,882, and 1,953 rpm, for the same reasons given above in connection with the case for 1,953 rpm, the operation of the adder/accumulator 24 continues to the circled points 2 and 2' in Fig. 3; but now uses the addend quantity and repeats number (in registers 26 and 38) reads from the fifth memory 38 location. At 1,395 rpm the Fig. 1 system causes a spark to start after 20,1 31 microseconds, which corresponds with a spark advance of 1,374 microseconds or 11.5 crankshaft degrees.

At engine speeds a trifle lower than 1,395 rpm, the output of the adder/accumulator 24 adds addends from addend register 26 to follow the solid curve in Fig. 3 from the origin through circled points 4, 3 to point 2, where the output count is 20,131, as has been described. Then, in going from circled point 2 to circled point 1, the output count should remain at 20,131. This is accomplished by using an addend (from a memory 360 location) which is equal to zero for 1,374 microseconds, the period of time necessary to go from 20,131 microseconds to 21,505 microseconds. The contents of the addend register is used once every 1 6 microseconds, so the repeats number from memory 36 stored during this time period in the repeats register 38 should be about 86. Thus, the start of ignition spark is delayed until the spark advance is zero.

Then, at all lower engine speeds, more than a trifle less than 1,395 rpm, the spark advance remains at zero. This is accomplished by using an addend from memory equal to 1 6. Then at all lower engine speeds, the output of the adder/accumulator reaches the count in the period register 20 in the same period of time previousy required for the period counter 1 4 to reach the same number.

This is the condition represented in Fig. 3 by the solid line having a slope of unity between circled points 1 and 0.

In the explanation thus far it has been assumed (a) that at the outset of each operation of the Fig. 1 system which ends with the production of an output pulse on 48, when (b) the initial count set into address counter 42 was zero. Recall that under these conditions (a) the addend number and repeats number stored in the first location of memory 38 initially were supplied to addend register 26 and repeats register 38, and (b) as the operation of Fig. 1 system continued, other addend numbers and repeats numbers at succeeding locations were accessed as needed. In other words, there has been described thus far the use of a single table of addend numbers and repeats numbers suitable for controlling spark advance soley as a function of engine speed.

Next described is the use of the abovedescribed system, where spark time is controlled by a parameter other than in addition to engine speed. The other parameter chosen for demonstration is intake manifold pressure. In Fig.1 there are shown vacuum transducer 57 (which is coupled to the intake manifold), analog-to-digital (A/D) converter 62 and jam address multiplexer 65. The use and relationship of those components with respect to components thus far described is presented next.

Under the circumstances now considered, at reset time, the address counter 42 receives the first address of a table in memory 38, which corresponds with a spark advance ver sus engine speed characteristic appropriate for the existing intake manifold vacuum as sensed by the transducer 57. The voltage from trans ducer 57 is translated in analog-to-digital con verter 62 to a digital address which is passed through multiplexer 65 and bus 43 to the preset table memory address counter 42. The address in the counter 42 may then be the first address of one of two or more tables in memory 36, which one table corresponds to the characteristic A in Fig. 2, which one table 36, (depending on the manifold vacuum) corresponds to the characteristic B. Note that characteristic B is the same as characteristic A from circled point C to circled point 0.

If the initial address in counter 42 is the first address of characteristic B, the contents of successive memory locations cause an operation of the system corresponding to the above-described movement to the left from circled point 4 along line B in Fig. 2, and a movement upward and to the right from circled point 5 along line B in Fig. 3. When movement is continued to reach the circled point C, then contents of the most-recently accessed memory location is a jump command and the address of a memory location in the table defining the characteristic A (and not, as previously described, merely the nextfollowing set of addend and repeats numbers in the characteristic B table).

The jump command is recognized by a jump decoder 74, whose consequent output is applied through "or" gate 75 to memory address counter 42. Consequently, the new address (from the accessed memory 36 location) passes over bus 76 and through multiplexer 65 and is jammed into the memory address counter 42. The system then follows the characteristic curve A from circled point C to circled point 1. The described construction and operation using a jump command permits a saving in memory space which otherwise would be needed to duplicate the common portions of the two characteristics (i.e., the coincident portions lying between circled points C and 1 in Fig. 2).

A second way in which memory space may be conserved is by making the system jump to another memory location in the same table.

The jump back may be to the next preceding memory location, so that the system loops around and repeatedly accesses the same addend quantity and corresponding repeats quantity. In this way, the last straight line portion (at the low RPM end) of a characteristics in Fig. 3 may be followed without using all the memory locations otherwise needed.

A third way in which memory space may be conserved is by inserting a jump command in a memory location corresponding with the circled point 1 in Figs. 2 and 3, together with the address of a memory location storing addends equal to zero. When this memory location is reached, the adder/accumulator 24 and comparator 48 never produce a spark advance output, and consequently a zero spark advance signal is provided over line 97 to the ignition pulse generator.

Claims (5)

1. A system for producing an output pulse at a time which is a function of the time period between two input pulses (on 16) comprising: a source of clock pulses; a counter connected to count the number of clock pulses occurring in the period between said two input pulses; a source of an addend quantity; adder/accumulator means to add repeatedly and to accumulate the sums of said addend quantity; and a comparator coupled to receive the count from said counter and said sums from said adder accumulator means for producing said output pulse when said sum provided by said adder/accumulator equals or exceeds the counted number of clock pulses.

2. The system of claim 1, wherein said counter and said adder/accumulator are reset by each of said input pulses.

3. The system of claim 1 or 2, wherein: said source of an addend quantity includes a memory having locations, at each of which is stored one of said addend quantities and a corresponding repeats number; and wherein there are provided: means operative after a count from said counter has been applied to said comparator for accessing a location in said memory and for causing said adder/accumulator means to add a quantity read from said memory a number of times determined by a correspond ing repeats number; and wherein said quantitites and repeats numbers stored in said memory locations are selected so that said output pulse occurs at a time dependent on the spacing of the input pulses.

4. The system of claim 3 adapted to set spark timing in accordance with engine speed, where said input pulses are any two adjacent pulses provided by a source of engine speed reference pulses, where said period between said two pulses corresponds to a speed at which the engine is running; wherein: said counter, in responding to said clock pulses occurring during a time interval of duration AA, provides an engine references period number representing the time period between ignitions; and said addend quantities and said repeats numbers are of values such that the contents of said adder/accumulator reaches a value corresponding to the value reached in said counter at a time providing the spark advance desired at the engine speed.

4. The system of claim 3 adapted to set spark timing in accordance with engine speed, where said input pulses are any two adjacent pulses provided by a source of engine speed reference pulses, where said period between said two pulses corresponds to a speed at which the engine is running; wherein: said counter, in responding to said clock pulses occurring the period between any two engine speed reference pulses, provides an engine references period number representing the time period between ignitions; and said addend quantities and said repeats numbers being of values such that the contents of said adder/accumulator reaches a value corresponding to the value reached in said counter at a time providing the spark advance desired at the engine speed.

5. The system of claim 4 wherein said engine speed reference pulses have a period corresponding with the period between ignitions in cylinders of the engine.

6. A system of anyone of claims 3, 4 and 5 wherein said memory is a read-only memory.

7. The system of claim 4 wherein said adder/accumulator means is operative at a time following the period when the counter counts the clock pulses between two engine speed reference pulses.

8. The system of claim 4 wherein said clock pulse source which provides clock pulses to said counter also provides at a submultiple frequency of said clock pulses other pulses to cause said adder/accumulator to operate.

9. The system of claim 8 wherein said addend quantities have values comparable to the ratio of the frequency of said clock pulses to the frequency of said other pulses.

10. The system of claim 3, wherein: said memory includes a memory address counter and said addend quantities and said repeats numbers, which are stored at respective memory locations, comprise at least two tables; and there is further provided: means dependent on a sensed condition to jam a first address of an appropriate one of said tables into said memory address counter; so that said adder/accumulator means adds said addend quantities the numbers of times determined by corresponding repeats numbers de- termined from said one table.

11. A system of claim 1 0, wherein said means dependent on a sensed condition includes a manifold vacuum transducer.

1 2. A system of claim 10, wherein: at least one of said memory locations includes a jump code and an associated address of a memory location; and said system includes a jump decoder responsive to said jurnp code for causing said associated address to be jammed into said memory address counter.

1 3. The system of claim 12, wherein said one memory location is included among those locations which store one of said tables and said associated address accesses a memory location included in the other one of said tables.

1 4. The system of claim 10 or 1 2 wherein said output pulse from said comparator is advanced in time relative to one of said input pulses, and further includes means operative in response to said one input pulse and to the absence of an output pulse from said comparator to generate a non-advanced output pulse.

1

5. A digital timing system for controlling spark timing in an internal combustion engine, substantially as hereinbefore described with reference to the drawings.

CLAIMS (25 Sep 1981)

1. A system for producing an output pulse at a time which is a function of the duration AA of the time interval between two input pulses (on 16) comprising: a source of clock pulses; a counter connected to count the number of clock pulses occurring during a time interval of duration AA; a source of an addend quantity; adder/accumulator means to add repeatedly and to accumulate the sums of said addend quantity; and a comparator coupled to receive the count from said counter and said sums from said adder accumulator means for producing said output pulse when said sum provided by said adder/accumulator equals or exceeds the counted number of clock pulses.