GB2077536A - Digital to analog converter - Google Patents

Abstract

In one of six embodiments, a digital to analog converter has an input register 101 for receiving base 2 binary digital input signals, including negative integer representation in two's complement form. The input signals on registering in the input 101 are converted into a base 2 binary range representing only positive integers, and are multiplied by three as fractions by a multiply by three unit 103 and a recycle register 105 to produce a serial output of a binary coded ternary number which is converted into parallel form by a serial to parallel converter 106 and clocked into an output register 107. The outputs of the register 107 drive switchable level changers 108 which apply positive and/or negative reference voltages of equal magnitude to ladder network 109 of resistors with base three weighting. The resultant analog output signal has range in which zero is the mid-point, and the operation of the converter is such that whenever a series of digital input signals to the input register 101 requires there to be a departure which is in either direction from the analog zero output, the number of switchable level changers whose states are changed at any stage in the resultant sequence of changes is independent of the direction of the departure from the analog zero. <IMAGE>

Description

SPECIFICATION Digital to analog converter This invention relates to digital to analog converters.

It is an object of the present invention to provide a digital to analog converter which utilises switching means which are controlled by digital inputs to the converter and which is capable of being so constructed and operated that only relatively small numbers ofthe switching means need be operated in order to produce a small change in analog output from a mid-point, regardless of the direction of the change.

According to the present invention there is provided a digital to analog converter having input means for receiving digital signals representing a variable quantity and for converting received digital signals into control signals with a predetermined relationship to the received signals, an arrangement of resistors and controllable switches for controlling current flow in the resistors, the said arrangement being coupled to a common output terminal and the input means being so coupled to the said arrangement as to supply control signals to the controllable switches, and reference means for applying at least one reference analog signal to the said arrangement, the input means and the said arrangement being such that, in dependence upon the states of the controllable switches, an analog output signal can be established by the said arrangement at the common outputterminal having any value allowed by a predetermined resolution error within a range of values having a mid-point from which departures in either direction are effected by changes in the states of selected controllable switches of the said arrangement, each controllable switch controlling a respective contribution to the analog output signal, each contribution having a respective magnitude such that the magnitudes of the contributions constitute at least two sets each of which is representative of an ordered set of numbers formed by the zero power and successive higher powers of a common radix, and the said switches can be so controlled by the input means that pairs of contributions of equal magnitude can be contributed to the analog output signal.

Preferably there are at least two reference analog signals which have opposite polarities and the said arrangement is such that each of the said contributions can have either of the two polarities in dependence upon the state of the respective controllable switch. The said input means can then be so operated that the mid-point of the range of the analog output signal is produced whenever the states of the said switches are such that all the contributions consisting one of the said two sets are of one polarity and all the contributions constituting the other of the said two sets are of the other polarity.

The input means of a digital to analog converter embodying the present invention can be so operated thatwheneverthe input means receives a series of digital signals requiring there to be a departure which is in either direction from the mid-point, a sequence of individual ones and groups, of the controllable switches have their states changed by the input means, the sequence being such that the corresponding sequence of contributions and combined contributions affected by the changes of state is representative of a plurality of successive numbers of increasing magnitude in a numerical system based on the said common radix, and the number of switches whose states are changed at any stage in the said sequence being independent of the direction of the departure from the mid-point.

Preferably, the contributions which constitute a set are such that the ratio of the magnitudes of any member and the neighbour or each neighbour is equal to their said common radix, and the said common radix is two or three.

In a preferred embodiment in which the common radix is three, the said input means is preferably such that the control signals are produced in pairs to control pairs of the switches, each switch of such a pair controlling a contribution having the same magnitude as the contribution controlled by the other switch of the pair, and each said pair of control signals representing a binary coded ternary number.

To convert a digital input signal in base 2 binary form into a binary coded ternary form, the input means may include means for multiplying by three the base 2 number represented by each digital input signal received by the input means.

The switches in a preferred embodiment of the invention are each in the form of a switching unit having two states, the state being determined by a control signal in binary form and the switching unit having an outputterminal atwhich either one of two reference voltages appears in accordance with the state of the switching unit.

The invention will now be described in more detail, solely by way of example, with reference to the accompanying drawings, in which: Figs. 1,2 and 3 are simplified circuit diagrams of respective output stages of first, second and third embodiments of the invention, Fig. 4 is a circuit diagram of a fourth embodiment of the invention, Fig. 5 is a simplified circuit diagram of a fifth embodiment of the invention, Figs. 6 and 7 are circuit diagrams of the respective output stages of sixth and seventh embodiments of the invention, Fig. 8 is a block diagram of the sixth embodiment, Fig. 9 is a circuit diagram of an input/decoder stage of the sixth embodiment, Fig. 10 is a circuit diagram of timing circuitry of the sixth embodiment, Fig. 11 is a set of waveform diagrams illustrating timing relationships in the timing circuitry of Fig. 10, Fig. 12 is a circuit diagram of serial to parallel conversion circuitry of the sixth embodiment, Fig. 13 is a circuit diagram of a reference voltage supply output stage, and Fig. 14 is a circuit diagram of switching circuitry to be connected to the supply output stage of Fig. 13.

Fig. 1 shows the output stage of a digital-to-analog converter in which a high reference voltage is provided at a reference input terminal 11 and can be applied to any one or more of eight summing resistors which are connected to a summing point 12 at the inverting input terminal 13 of a current summing operational amplifier 14 with a feedback resistor 15 coupling itsoutputterminal 16to the inverting input terminal 13. The non-inverting input terminal 17 of the amplifier 14 is connected to ground, and ground potential serves as a second reference voltage. The eight summing resistors are arranged in pairs with equal resistance, the different resistance values in the four pairs being such as to form a binary series, namely R, 2R, 4R and 8R, where R is the resistance of each resistors of the pair of smallest resistors. In Fig.

1, the four pairs of summing resistors are shown respectively connected to four pairs of on-off switches so that the reference input terminal 11 can be connected to R and R by switch S3A and S3B respectively, to 2R and 2R by switches 2A and 2B respectively, to 4R and 4R by switches S1 A and S1 B respectively, and to 8R and 8R by switches SOA and SOB respectively. These eight switches are, in practice, controllable electronic switches adapted to operate in accordance with a relationship with digital input signals supplied to an input stage not shown.

It will be seen that if all the A switches, i.e. SOA, S1 A, S2A and S3A, are open and all the B switches, i.e. SOB, 51 B, S2B and S3B, are closed, the amplifier 14 provides at its outputterminal 16 an analog output signal the value of which is the mid-point of a range of possible values extending from zero, when all the switches are open, to a maximum value given by V.K 2 2 2 - - (2 + - + - R 2 48 where V is the reference voltage at the terminal 11, and K is the resistance of the feedback resistor 15.

When all of the B switches are closed and initially all of the A switches are open, by systematically closing the A switches in a sequence corresponding to the natural binary sequence as applied to the conductances of the resistors associated with the A switches, the analog signal atthe output terminal 16 can be increased in equal steps from the mid-point of the ranges to the maximum value. The resistors and groups of resistors successively connected to the input terminal 11 to reach the maximum analog output signal from the mid-point of the range are therefore: 8R, 4R, 4R+8R, 2R, 2R+8R, 2R+4R, 2R+4R+8R, R, R+8R, R+4R, R+4R+8R, R+2R, R+2R+8R, R+2R+4R, and R+2R+4R+8R.

The corresponding closed A switches and groups of closed A switches are: SOA, S1A, S1A+SOA, S2A, S2A+SOA, S2A+S1A, S2A+S1 A+SOA, S3A, S3A+SOA, S3A+S1 A, S3A+S1 A+SOA, S3A+S2A, S3A+S2A+SOA, S3A+S2A+S1 A, S3A+S2A+S1 A+SOA.

The analog output signal is in this embodiment a voltage atthe output terminal 16 relative to ground, the amplifier 14 operating to establish a virtual earth at the inverting input terminal 13. To reach zero volts at the output terminal 16 from the mid-point of the range, the B switches are systematically opened in a sequence corresponding to the natural binary sequence applied to the conductances of the resistors associated with the B switches, all the A switches remaining open. Consequently the following B switches and groups of B switches are opened in sequence: SOB,S1B,S1B+SOB,S2B,S2B+SOB,S2B+S1B, S2B+S1B+SOB,S3B,S3B+SOB,S3B+S1B, S3B+S1B+SOB,S3B+S2B,S3B+S2B+SOB, S3B +S2B +S1 B and S3B +S2B +S1 B +SOB.

To return the analog output from the maximum value to the mid-point, the B switches are kept closed and the A switches are opened singly and in groups until all of the A switches are open, the sequence of open A switches and groups of open A switches being those given herein before and in the same order, i.e. starting with SOA alone open, S1A alone open, and so on to S3A+S2A+S1A open and then S3A+S2A+S1A+SOA open. Similarly, to return the analog output from zero to the mid-point, all the A switches are kept open and the B switches are closed singly and in groups until all the B switches are closed, the sequence being as given hereinbefore, i.e. SOB alone closed, S1 B alone closed, S1 B and SOB closed, and so on to S3B+S2B+S1B closed and then S3B+S2B+S1 B+SOB closed.

It will be seen that, by operating the A and B switches in the manner just described, the number of switches which undergo changes of state is small when the analog output signal varies about the mid-point of the range with a small amplitude, i.e.

departure from the mid-point, and that the resistors associated with the switches undergoing changes of state for such variation are the larger resistors.

To provide suitable binary control signals for controlling the A and B switches, where, for example, for each switch, a binary 1 control signal shuts the switch and a binary 0 control signal opens the switch, and the digital input signals are in the form of the natural binary code for zero and positive integers from one to thirty inclusive, a decoder (not shown) can be constructed which operates as follows.

The decoder senses whether or not the binary coded input represents an integer greater than fifteen. If the input does not represent such an integer, the decoder supplies the binary coded input directly as control signals to the A and B switches in such a manner that SOB is controlled bythe least significant bit, S3B is controlled by the most significant bit, and the two switches S1 B and S2R are respectively controlled by the intermediate bits in their order of increasing significance.

If the input does represent an integer greater than fifteen, the decoder generates a signal which is applied to hold all the B switches closed, and also subtracts fifteen from the binary coded input and applies the binary coded result of this subtraction to the A switches in such a manner that SOA is control led by the least significant bit of the result, S3A is controlled by the most significant bit of the result, and S1A and S2A are respectively controlled by the two intermediate bits of the result in their order of increasing significance.

Since whenever the digital input represents an integerwhich is less than fifteen, all the A switches are held open, A and B switches which control equal contributions to the analog output, e.g. S1 A and S1B, are in effect controlled by signals having equal significance, the B switches being controlled by the bits used in representing integers which are not greaterthan fifteen, and the A switches being controlled by the bits used in representing the result of subtracting fifteen from integers which are greater than fifteen.

Fig. 2 shows the output stage of a digital to analog converter which is similar to that of Fig. 1, but differs in having a positive reference voltage REF A at a reference input terminal 18, a negative reference voltage REF B at a reference input terminal 19, and two way A and B switches. A current summing amplifier 14 with a feedback resistor 15 and a grounded noninverting inputterminal 17 is again included. The use of two-way A and B switches enables each of the eight resistors to be connected either to the positive reference terminal 18 ortho the negative reference input terminal 19.

The reference voltages REF A and REF B are of equal magnitude so that if all the A switches are set to connect their respective resistors to the terminal 19 and all the B switches are set to connect their respective resistors to the terminal 18, the current contributions controlled by the A and B switches cancel in pairs, the cancelling switches being SOA and SOB, S1A and S1 B, S2A and S2B, and S3A and S3B, so that the analog output is zero.

If all the A switches and all the B switches are set to connect all the resistors to negative terminal 19, the analog output is a maximum positive value because of the inverting effect of the amplifier 14, and if all the A and B switches connect their resistors to the positive terminal 18, the analog output is a maximum negative value. The two maximum values are of equal magnitude since the magnitude of REF A and REF B are equal, and the same resistors are involved in producing the maxima.

Starting from the zero condition, i.e. with all the A switches set to the negative terminal 19 and all the B switches set to the positive terminal 18, so that there is zero analog output, a departure from the zero analog output can be made in either direction by changing over the movable contacts of the A or B switches, the B switches if the analog output is to be positive and the A switches if the analog output is to be negative. The changing over of the movable contacts is carried out systematically in accordance with the natural binary sequence as applied to the conductances of the resistors associated with the A or B switches.For example, to increase the analog output signal from zero to the maximum positive value, the B switches are set to the negative terminal 19 in the following sequence of single switches and groups of switches: SOB,SlB,SlB+SOB,S2B,S2B+SOB,S2B+SlB, S2B+S1B+SOB,S3B,S3B+SOB,S3B+SlB, S3B+SlB+SOB,S3B+S2B,S3B+S2B+SOB, S3B+S2B+SlB,S3B+S2B+SlB+SOB.

The same sequence of single and groups of switches is set to the positive terminal 18 in decreasing the analog output from the maximum positive value to zero. Similarly, starting from the zero condition, the A switches are set in a corresponding sequence of singles and groups to the positive terminal 18 to increase the analog output from zero to the maximum negative output value, and in the same sequence of singles and groups to the negative terminal 19 to decrease the analog output from the maximum negative value to zero.

As for Fig. 1, the sequence of changing the states of the A and B switches in the arrangement of Fig. 2 ensures that the number of switches undergoing changes of state when the analog output signal var iesaboutthe mid-point of the analog range, i.e.

about zero, with a small amplitude is small and that the resistors associated with the switches undergoing changes are the larger resistors.

In a modification ofthe arrangement of Fig. 2, the non-inverting input terminal 17 of the amplifier 14 is connected to receive a reference voltage which is the mean of the two reference voltages REF A and REF B which, in this modification, are not of equal magnitude and may both be positive or negative.

In a further modification of the arrangement of Fig.

2, the current summing amplifier 14 with the feedback resistor 15 is replaced by a voltage amplifier with direct feedback from its output to its inverting input terminal, the commonly connected ends of the eight resistors being connected to the non-inverting input terminal of the voltage amplifier. The polarity of the reference inputterminals 18 and 19 is inverted. A resistive load may be connected between the non-inverting input terminal and ground.

Since the A and B switches of Fig. 2 are two way switches, each can be controlled by a binary control signal. For example, a binary 0 can set the switch in the state in which itconnectsthe positive terminal 18 to its respective resistor, and a binary 1 can cause the switch to connect the negative terminal 19 to the respective resistor. To convert a binary coded input signal having natural binary representation of zero and positive integers upto and including 15 and two's complement representation of negative integers up to and including minus fifteen, into a suitable pattern of such control signals for the A and B switches, a decoder (not shown) is provided. For the input binary zero signal, control signals in the form of binary 1 for each A switch and binary 0 for each B switch are required.For the maximum positive input, all A and B switches must be provided with binary 1, and for the maximum negative input, all A and B switches must be provided with binary 0. For the intermediate input representing positive seven, switches S3A and S3B must receive 1 and 0 respectively, and the remaining A and B switches must all receive 1. For negative seven, the-required control signals are 1 and 0 again for switch S3A and S3B, and 0 for the remaining A and B switches. The decoder (not shown) is therefore such as to apply the binary magnitude of positive integers to the B switches, the least significant bit controlling the switch SOB, and the other bits in order significance controlling the switches S1 B, S2B and S3B, to apply binary 1 to all A switches for zero and all positive integers, to apply binary 0 to all B switches for all negative integers and to apply the inversion of the natural binary magnitude of all negative integers to the A switches, the least significant bit controlling the switch SOA, and the other bits in order of significance controlling the switches S1A, S2A and S3A.To obtain from the two's complement input form of the negative integers the magnitude in inverted form, the sign bit is used to implementthe subtraction of binary 1 from the least significant of the significant bits of the two's complement input form. The result of this subtraction is the required group of control signals. In other words, the required control signals are the significant bits of the one's complement form of the input representing a negative integer.

Fig. 3 shows the output stage of a digital potentiometer embodiment of the invention. The "tapping point" 20 of the potentiometer chain of resistors having the relative values of resistance indicated in Fig.

3 is connected to the non-inverting input terminal 21 of a voltage amplifier 22 having its inverting input terminal 23 connected directly to its output terminal 24. One end 25 of the potentiometer chain is supplied with a positive reference voltage V, and the other end 26 is grounded. Each half of the potentiometer chain is formed by a series of pairs of equal resistors, the equal values of the pairs being in accordance with the binary system, and the values increasing form the grounded end 26 to the tapping point 20 at the middle of the chain, and from the tapping point 20 to the positive reference end 25 of the chain.

Each resistor has a respective openiclosed switch connected in parallel therewith, and these switches are ganged in pairs as shown, each pair being associated with a pair of resistors of equal value taken one in each half of the potentiometer chain.

The ganged pairs of switches are designated SOB for R, SOA for R, S1 B for 2R, S1A for 2R, S2B for4R, S2A for 4R, S3B for 8R, and S3A for 8R. The ganging of each pair of switches is such that when one open/closed switch is open, the other is closed, and vice versea. Conseqquently, however the switch pairs are operated, the total resistance between the end points 25 and 26 remain the same, and therefore the current through each resistor not short-circuited by the switch in parallel therewith always develops the same voltage between its ends, i.e. the voltage across any resistor not short-circuited is given by x +V 30R wherex is the resistance ofthe resistor, and 30R is the constant total resistance between the ends 25 and 26.

Fig. 3 shows the A and B switch pairs in the states which result in the midpoint of the range of analog output signal values appearing atthe output termi nal 24. To decrease the output signal to zero from the mid-point value, the condition shown in Fig. 3 must be altered by operating all the B switch pairs to reduce the resistance between the tapping point 20 and the grounded end 26 to zero. To do this, the same sequence of singles and groups from SOB to S3B+S2B+S1 B+SOB as for Figs. 1 and 2 is operated, and to return the output value from zero to the midpoint the same sequence of groups of B switches is operated again in the same order but in the reverse manner, i.e. so asto reintroduce resistance between the tapping point 20 and the end 26, starting with reintroducing R, then simultaneously shortcircuiting R and reintroducing 2R, and so on.To increase the analog output value from the mid-point to the maximum value, the A switch pairs of Fig. 3 are operated to decrease the resistance between the tapping point 20 and the positive end 25 to zero. The sequence of single and groups of A switch pairs operating to short circuit the respective resistors between point 20 and end 25 is: SOA, S1A, S1A+SOA, S2A, S2A+SOA, S2A+S1A, S2A+S1A+SOA, S3A, S3A+SOA, S3A+S1A, S3A+SlA+SOA, S3A+S2A, S3A+S2A+SOA, S3A+S2A+S1A, S3A+S2A+S1A+SOA. The same sequence of single and groups of A switch pairs operating to include the respective resistors between point 20 and end 25 is used to reduce the analog output signal from maximum to mid-point.

Control signals for the switch pairs can be provided by a decoder (not shown) as described for the embodiment of Fig. 1. The control signals are applied to the A and B switch pairs in accordance with the rules that SOA and SOB are controlled by the least significant digit of the decoder output, and the other A and B switch pairs are controlled by the bits of higher significance in the order of the designation of the switch pairs, so that the most significant bit controls S3A and S3B, a binary 1 control signal causes the controlled switch pairto include the associated resistor between point 20 and end 26, a binary 0 control signal causes the controlled switch to short-circuit the associated resistor between point 20 and end 26, all the A switch pairs receive binary 0 control signals when the digital input represents a number not greater than fifteen, and all the B switch pairs receive binary 1 control signals when the digital input represents a number greater than fifteen.

Fig. 4 shows a digital to analog converter for converting a binary coded input signal into an analog voltage, the binary coded input signal representing zero and positive integers by means of the natural binary system with a binary 0 sign bit, and negative integers by means of two's complement representa tion. In Fig. 4, the digital inputterminals are indi cated by the order of the bit significance, the least significant bit being order 0, i.e. representing 2 , the most significant bit being order 7, representing 27, and the sign bit order 8. The output stage of the converter includes a plurality of switching units A, and a plurality of resistors arranged to form, in a manner which will be explainedhereinafter, an R-2R ladder or lattice. Current distribution in an R-2R lad der is explained at page 111 of Modern Electronic Measuring Systems, edited by P.P.L. Regtien and published by Delft University Press in 1978, in sec tion 7.2.1.2: "DAC with R-2R lattice network".

The R-2R resistor ladder of Fig. 4 has seven 500 ohm resistors connected in series with one another to provide eight junction points JO, J1 to J7 to which eight pairs of 2 kilohms resistors are connected as shown, a 1 kilohm resistor being additionally con nected to the point J7 and a further pair of 2 kilohm resistors being connected to the point JO. Each of the 2 kilohm resistors except one, which is a 2 kilohm resistor 30 in Fig. 4, of the further pair at JO is connected to the output terminal of a respective one of the switching units A, the remaining 2 kilohm resistor being grounded as shown.The 1 kilohm resistor couples the junction point J7 to the inverting input terminal of a current amplifier 27 having an adjustable feedback resistor with a maximum resistance of 4.7 kilohms coupling its output terminal to the inverting input terminal. The non-inverting input terminal of the amplifier 27 is grounded, so that in operation a virtual earth is established at the inverting input terminal of the amplifer 27.

Each of the switching units A has two states of operation: one state in which a positive voltage of +5 volts is present at the output terminal of the unit A, and another state in which a negative voltage of -5 volts is present at the output terminal of the unit A. The output impedance of each unit A is substantially resistive and does not vary when the unit switches from either state to the other.It is arranged that the resistance to ground from the junction point JO contributed by the unpaired switching unit A, indicated by the reference 28 in Fig. 4, in series with the respective 2 kilohm resistor 29 is effectively zero so that the 2 kilohm resistor 29 is effectively in parallel with the grounded 2 kilohm resistor 30 to provide 1 kilohm between the junction point JO and ground to balance the 1 kilohm resistor which couples the junction point J7 to virtual earth.

In operation, each switching unit A is applying either +5 volts or -5 volts to the respective 2 kilohm resistor connected thereto, so that whenever both of the switching units A coupled to the respective one of the junction points J1 and J7 are in the same state, the respective junction point is effectively coupled by 1 kilohm to a +5 volt or -5 volt source. The junction point J0 has three switching units A coupled thereto by respective 2 kilohm resistors, and two of these units A, indicated by reference 31 and 32 in Fig.

4, can be operated as a pair in the same way for the point J0 as the corresponding pair of units A at any of the other points J1 to J7.

If the pair 31 and 32 at JO, or the pair of units A at any other of the junction points, are in opposite states, their effect at the junction point to which they are coupled by their respective 2 kilohm resistors is that of a single kilohm resistor coupled to ground.

Thus the resistors and switching units A of the arrangement in the embodiment of Fig. 4 act as an R-2R ladder in which R=500 ohms.

Before the decoder portion of the embodiment of Fig. 4 and its operation are described, an alternative embodiment will be described. In the alternative embodiment, the switching unit 28 and the resistors 29 and 30 are replaced by a single 1 kilohm resistor to ground and the remaining switching units A are driven by a decoder constructed to operate as described hereinbefore with reference to the embodiment having the arrangement of Fig. 2 as its output stage, but extended to respond corresponding to the additional four more significant bits, so that the switching units 31 and 32 are operated as switches SOA and SOB respectively, the pair of units A coupled to J1 are operated as Sly and S1B respectively, the units A coupled to J2 are operated as S2A and S2B, the units A coupled to J3 are operated as S3A and S3, and the other pairs of units A coupled respectively to J4 JS, J6 and J, are operated in a corresponding manner in accordance with the significance of the bit concerned.

In the embodiment of Fig. 4, the added complication of subtracting one from the binary magnitude of two's complement representations of negative integers is avoided by the inclusion of the switching unit 28 and its control by the sign bit of the digital input to the converter. The paired switching units A are so controlled by a two's complement input that the magnitude of the output of the amplifer 27 would, but for the presence of the switching unit 28, be the analog magnitude corresponding to the binary magnitude minus one of the digital input. For example, the binary magnitude of the two's complement digital input 111111111 is 00000001.However, the decoder portion of the converter of Fig. 4 responds to this digital input by producing control signals which cause the switching units A, apart from the unit 28, to cancel in pairs, which would result in a zero output from the amplifier 27 but for the contribution controlled by the unit 28. To achieve such operation, the decoder portion has eight OR gates 33 to 40 and eight AND gates 41 to 48, each of which has one input terminal connected to the output terminal of an inverter 49 which receives the sign bit of the digital input, and one input terminal arranged to receive a respective significant bit of the digital input, the gates being pair so that one OR gate 33 and one AND 41 receive the order 0 bit, and so on as indicated in Fig. 4, up to the OR gate 40 and the AND gate 48 which both receive the order7 bit.Thus, whenever a two's complement representation of a negative integer is received as the digital input, all the AND gates 41 to 48 receive a binary 0 as one input and therefore produce a binary Oat their respective output terminals, which are respectively connected to control the eight switching units A which are coupled to the junction points To to J7, as shown, and which in this case all produce negative output of -5 volts. The eight switching units A which are paired with those controlled by the AND gates are connected, as shown, to be controlled by the outputs of the eight OR gates 33 to 40.The outputs produced by the eight OR gates are the eight significant bits of the two's complement input, and conse quentlythe switching units A controlled by the OR gates produce a positive output, i.e. +5 volts, wherever a binary f occurs in the two's complement input, and a negative output, i.e. -5 volts, wherever a binary 0 occurs in the two's complement in put. However, since the switching units A controlled by the AND gates are all producing negative outputs of -5 volts, only those switching units A controlled by gates which have binary 0 on their significant bit input terminals contribute to the voltage established at the junction point J7 and thus to the output ofthe amplifier 27. Consequently, the negative voltage established at the point J7 has a magnitude representative of the binary magnitude of the two's complement digital input. Negative vol tagesestablished at J7 in response two's comple ment representations of negative integers are, of course, inverted by the current summing amplifier 27 which produces a positive voltage of proportional magnitude at its output terminal. Whenever a digital input representing a positive integer is received by the decoder, the sign bit is binary 0 and consequently the inverter 49 produces an output of binary 1 which enables all the AND gates 41 to 48 and sets all the OR gates 33 to 40 to produce a binary 1 output.The outputs of the AND gates are in this case the same as the significant bits of the digital input and therefore correspond directly to the binary representation of the magnitude of the digital input. Furthermore, since all the switching units A connected to an OR gate produce a positive output of +5 volts, only those gates having a significant bit input term inal receiving binary 1 contribute to the positive voltage which is established at the junction point J7 and thus to the negative voltages at the output terminal of the amplifier 27.

It will be seen that a digital input of zero, i.e.

000000000, causes the switching units A to cancel in pairs at all the junction points J0 to J7, leaving only the switching unit 28 effective in producing a voltage, which is positive since the output of the inverter 49 which controls the unit 28 is binary 1, at the junction points7. Since the resistor 29 which couples the unit 28 to the junction point to is a 2 kilohm resistor, the unit 28 contributes the negative analog equivalent of bicimal 0.1 i.e. decimal 0.5 to the analog output It will also be seen that a nine bit digital input of the two's complement representation of - 1, i.e.

111111111, causes the switching units to cancel in pairs at J0 to J7 and the unit 28 to contribute the positive analog equivalent of bicimal 0.1 to the analog output. Thus, whenever the digital input changes from zero to -1, the analog output changes from the analog equivalent of +0.1 to-Olin bicimal terms, i.e. increases by the analog equivalent of binary 1.

The additional analog equivalent of bicimal +0.1 is present for all positive integers received since the output of the inverter 49 is binary 1 for all such inputs, and the analog equivalent of bicimal -0.1 is contributed for all negative integers received since the inverter49 produces binary 0 for all two's com plement inputs.

Consequently, the mid-point of the analog output range of the converter of Fig. 4 is the small negative voltage which results from the +5 volts output of the unit 28. The binary magnitude of each positive integer received is converted directly into a positive voltage at J7 by the paired switching units A and adds to the small positive voltage contributed there by the unit 28.The binary magnitude represented by the inversion of the significant bits of each two's complement representation received, which mag nitude is one less than the magnitude of the actual negative integer represented, is in effect used to determine the negative voltage established at J7 by the paired switching units A, and a small negative voltage contributed bythe unit 28 which is produc ing -5 volts is added atJ7. Thus the difference bet ween the analog output produced in response to a non-zero digital input and the analog output produced in response to the zero digital input is directly proportional to the magnitude represented by the non-zero digital input for both positive and negative integers, and has the same rate of change for positive and negative integers so that variation through the mid-point of the analog output range is linear.

Fig. 5 shows the output stage of an analog to digital converter which has an R-2R ladder of resistors used in the reverse manner, as compared with Fig. 4.

A direct current reference input, which may be supplied by a source having any resistance, is provided at a reference input terminal 50. The R-2R ladder, in which all but one of the 2R resistors are replaced by pairs of 4R resistors in parallel, generates eight currents controlled respectively by eight two way switches SOA to S3A and SOB to S3B. The pair of switches SOA and SOB control currents of equal magnitude, and each ofthe pairs S1A and S2B, S2A and S2B, and S3A and S3B controls two equal currents.The two way switches are shown in Fig. 5 as having respective movable contacts connected to the 4R resistors, and pairs of fixed contacts, one contact of each pair being connected directly to the noninverting input terminal 51 of a current summing amplifier 52, and the other contacts of the pair being connected directly to the inverting input terminal 53 of the amplifier 52, the outputterminal 55 of which is coupled to the inverting terminal 53 by a feedback resistor 55 so that the inverting terminal 53 acts as a virtual earth, the non-inverting terminal 51 being connected to ground as shown. Since both input terminals 51 and 53 of the amplifier 52 are effectively at ground, operation of the two way switches does not alter the currents which flow in the resistors forming the R-2R ladder.In practice, the two way switches are not mechanical switches but are controllable electronic switches controlled by a decoder (not shown).

From Fig. 5 it will be seen that the pairs of switches SOA and SOB, S1A and 81 B, S2A and S2B, and S3A and S3B are coupled by the respective 4R resistors to four junction points JO', J1', J2, and J3', respectively.

Three resistors of relative resistance R are connected in series between a 2R resistor and the reference input terminal 50 and define the positions of these junction points. As a result of the relative values of the resistances of the resistors of the ladder, the total resistance between any one of the junction points J0 to J3, and ground presented to current established by the reference source is R. Furthermore, for such current, there are two paths with equal resistance between any junction point and ground. For exam ple, the resistance between JO' and ground is pre sented by the 2R resistor and the pair of parallel 4R resistors connected to the switches SOA and SOB.

Since the total resistance between JO' and ground is R, being the reciprocal of 2 1 - + 4R 2R the resistance between J1, and ground is presented by the pair of parallel 4R resistors connected to the switches S1A and 81 B, and the series combination of the R resistor connecting J1, to J0 and the resistance R to ground from JO'. Consequently, half the total current from the reference source flows through R between J3 and J2', a quarter through R between J2 and J,', an eighth through R between J,' and JO', and a sixteenth through 2R between Jd and ground.The magnitudes of these currents thus form a representation of a binary series, and the current through 2R can be used as a representation of 21.

Accordingly, the magnitude of the currents through the 4R resistors connected respectively to the switches SOA, S1A, S2A and S3A are representative of 20,21,22, and 23, and similarly the magnitudes of the currents through the 4R resistors of the switches SOB to S3B are representative of the same set of quantities.

With all the A and B switches of Fig. 5 set as shown, there is no current input to the inverting terminal 53, and the analog output at the output terminal 54 of the amplifier 52 is zero. If the movable contacts of all the A and B switches are set to connect the respective 4R resistors to the inverting terminal 53, the analog output at the terminal 54 is a maximum value. The mid-point of the range is produced at the terminal 54 when all the A switches connect their 4R resistors to the non-inverting terminal 51, and all the B switches connect their 4R resistors to the inverting terminal 53. Hence the decoder used to control the A and B switches can be as described hereinbefore in connection with Fig. 1.

Referring again to Fig. 1, it will be seen that a similar further embodiment controllable by the same decoder can be constructed by exchanging the positions of the A and B switches with their respective resistors between the reference input terminal 11 and the summing point 12.

Other resistance ladders than the R-2R ladder can be constructed. In general, solutions for the voltages produced at junction points in the ladder can be provided by using the general equation,

where Ej is the voltage at the junction point, R1, R2 and R3 are the resistances radiating from the junction point, and E1, E2 and E3 are the voltages at the ends of resistances R1, R2 and R3 respectively.

For an R-2R ladder terminated at each end by a grounded 2R resistor and having n junction points, (n-1) resistors of value R in series between the terminating 2R resistors, andn resistors of value 2R connected respectively to then junction points and supplied respectively with voltages VO, V1, and soon to Vn~1, the voltages produced at then junction points are UO, U1, and soon to Us~1, where for O < jsn-1

Taking Un1 as the output voltage of the ladder, this expression simplifies for Un~1 to

so that each input voltage Vj contributes to the output voltage Urn~1 in accordance with its respective binary weighting, namely 2cj.

The general expression for the voltage at a junction point in a ladder which hasn junction points, is terminated at each end by a grounded 6R resistor, has a (n-1) resistors of value 4R in series between the terminating 6R resistors, andn resistors of value 3R connected respectively to then junction points and supplied respectively with voltages VO, V1, to Van~1, is

and the output voltage Un1 is given by

so that each input voltage Vj contributes to the output voltage Un-1 in accordance with a respective ternary weighting, namely 3i.

Furthermore, it is a characteristic of ternary weighting that, if both positive and negative polarities are used, any positive or negative integer can be represented by a group of powers of the base 3 with each member of the group having as coefficient of +1 or -1 or 0. In such a system, zero is represented by all powers of 3 having 0 as coefficient, and the pattern of +1, -1 and 0 coefficients is symmetrical about zero since for any positive integer thus represented, the negative integer having the same magnitude is represented by the inversion of the group of coefficients for the positive integer. For example, plus ten is represented by +1.32+0.31+1.30, and minus ten is represented by -1.32+0.311.3 , or, more concisely, by +0+ and -0- respectively.Another feature of a base 3 system is that fewer digits are required to express any magnitude greater than two than are used by a base 2 system. In fact, the ratio of the logarithm to the base 2 to the logarithm to the base 3 of any number is substantially 1.585. In other words, the base 2 system uses about one and half times as many digits in representing a number than the base 3 system does.

Fig. 6 shows the output stage of a digital analog converter which employs a base 3 weighting system in the form of a ladder terminated by 3 kilohms at each end and having twelve junction points PO, P1, P2 to P", eleven 2 kilohm resistors in series between P0 and P", and twelve input resistance combinations of effectively 1.5 kilohms each, and each formed by a 500 ohm resistor coupling the respective junction point to two 2 kilohm effectively in parallel. Each 2 kilohm resistor is connected to the output terminal of a respective switching unit A which in operation supplies +5 volts or -5 volts to the resistor. The junction point P" is coupled as shown to the inverting terminal 56 of a current summing amplifier 57 having its non-inverting input terminal 58 grounded and its output terminal 59 coupled to the inverting terminal 56 by an adjustable resistor of 10 kilohms maximum resistance.

Each pair of switching units A coupled to a respective junction point is controlled by a pair of binary digits applied respectively to the two switching units A so that (i) when the binary pair (0,0) is applied, both switching units A produce positive outputs of -5 volts, (ii) when the binary pair (1,0) is applied, one switching unit A produces a positive output of +5 volts and the other switching unit A produces a negative output of +5 volts, and (iii) when the binary pair (1,1) is applied, both switching units A produce positive outputs of +5 volts. The weighted effects at Pt, of the output voltages provided by a pairof switching units A are inverted bythe amplifier 57.

The respective pairs of switching units A coupled to the points P0 to P,1 are indicated in Fig. 6 by reference numerals 60 to 71. The mid-point of the analog output range at the output terminal 59 appears when all of the unit pairs 60 to 71 receive a binary pair (1,0), the maximum negative value of the analog output appears when all the pairs 60 to 71 receive (1,1) and the maximum positive value appears when all the pairs 60 to 71 receive (0,0). It will be realised that in terms of the concise ternary notation used above, the binary pair (1,1) represents +, the pair (1,0) represents 0, and the pair (0,0) represents -.

It can be shown that the pattern of +, - and 0 terms in a representation of a positive integer can be obtained by replacing 2 by +, 1 by 0 and 0 by - in a ternary notation using 2, 1 and 0, and representing the positive integer by the sum of that integer with the positive integer represented by 111 . . . . 1 in the former notation, where the number of ternary 1 digits is equal to number of ternary digits representing the former positive integer. For example, eleven is represented by 102. Adding 111 gives 220 which becomes +±, i.e. 32+31 30 9+3-1 = 11.Similarly, the pattern of +,-and Terms in a representation of a negative integer can be obtained by replacing 2 by -,1 by 0 and 0 by + in the ternary notation using 2, 1 and 0, and prepresenting the negative integer by the sum of that integer with the negative integer rep resanted by 111.... 1 in the former notation, as before, so that, for example, minus eleven is represented by minus 102 to which minus 111 is added given minus 220 which becomes --+, i.e.

-3i -31 +30 = -11. However, the same result for negative integers can be obtained simply by adding the negative integer to plus 111 .... 1 and replacing 2 by +, 1 by 0 and 0 by provided the negative integer is not of greater magnitude than 111.... 1.

For example, 111-102 = 002 in ternary, which becomes --+.

Since digital information is usually conveyed in natural binary coding or two's complement, it is necessary to providethe output stage shown in Fig.

6 with a decoder capable of converting binary base 2 and two's complement coding into the binary coded ternary code which must be applied to the switching unit pairs 60 to 71. It will be noted that in terms of the 2,1,0 ternary notation, the number represented by 111.... 1 can serve as the mid-point for a range which extends from zero to twice 111.... 1. The mid-point of an input of positive and negative integers represented by binary base 2 digits and two's complement digits respectively is zero, i.e.

000.... 0 for however many digits, including the sign digit, there are. Such a binary base 2 range of representation can be converted into a correspond ing all positive integer range with a mid-point of 1000 . . . 0 with the same number of digits as the converted zero by inverting the sign bit, i.e. by adding 2n-1 whereon is the number of bits, including the sign bit, in the digital input, to the input pdsitive integers and subtracting 2"-' from the two's com plement representation of the input negative integers.

Furthermore, the mid-point of the all positive base 2 range can be made to coincide with the mid-point of the ternary base three range by setting the base 2 representation 100.... 0 equal to the ternary base 3 representations 111 ... 1. This equivalence can be achieved by treating the base 2 representation 100 .... O . . B as a half, since the ternary representation of a half is .i, i.e. 1/3 + 1/9 + 1/27 + . . Alternatively, a constant can be added to each representation in the all positive base 2 range, the value of the constant being such that the binary sum of the constant and the mid-point value 100.... 0 represents the same number as a ternary base 3 representation 111 . . . 1, where the number of ternary digits is sufficient for such equality.The output stage of a further digital to analog converter is shown in Fig. 7 which can operate in accordance with either a base 2 or a base 3 system depending in the relative values of eight resistors 72 to 79. The pairs of resistors 72 and 73,74 and 75,76 and 77 and 78 and 79 are pairs of equal resistors. For a base 2 system, the relative values of the resistors 72,74,76 and 78, and of the resistors 73,75,77 and 79 are respectively 8R, 4R, 2R and R, and for a base 3 system they are 27R, 9R, 3R and R.Current through each of these resistors is set at a level determined by a respective NPN transistor 80 having its emitter connected to the respective resistor, its base connected to a source of reference voltage VREF applied across the series combination of the base-emitterjunction and the respective resistor, and its collector connected to a respective one of eight two way switches SOA, SOB, S1 A, 81 B, S2A, S2B, S3A and S3B each formed by a pair of NPN transistors 81 and 82 having their emitters connected to the collector of the respective transistor 80.

The bases of each transistor 81 of each A switch and each transistor 82 of each B switch are connected to a source of LOGIC REF voltage art a reference terminal 83. The bases of the transistor 82 of the A switch and the transistor 81 of the B switch of each pair of switches coupled to equal resistors, i.e. the pairs SOA and SOB, S1A and S1 B, S2A and S2B, and S3A and S3B, are connected to respective control input terminals d,, d1, d2, or d3 as shown. A decoder (not shown) supplies binary coded base 2 control signals or binary coded ternary control signals, according to which set of relative values the resistors 72 to 79 have. The collectors of all the transistors 81 are connected to the inverting input terminal 84 of a current summing amplifier 85 having a feedback resistor 86 coupling its output terminal 87 to the inverting input terminal 84, and having its non-inverting inputterminal 89 connected to a positive supply rail 90 which is also connected to the collectors of all the transistors 82. The amplifier 85 operates to hold the inverting input terminal 84 at the same voltage as the sup ply rail 90 by producing sufficient output current to supply the current drawn through the feedback resis tor 86 to the transistors 81. Consequently, the vol tage at the output terminal 87 is proportional to the total current drawn by all the transistors 81.The levels of the binary control signals 1 and 0 applied to the bases of the transistors 81 and 82 are such that binary 1 holds the transistor on and binary holds the transistor off. Consequently, where the base of a transistor 81 receives the control signal binary 1, there is a corresponding contribution to the current flowing through the feedback resistor 86 in accor dance with the conductance of the associated one of the resistors 72 to 79. Conversely, where the base of a transistor 82 receives the control signal binary 1, there is a corresponding absence of contribution to the current flowing through the feedback resistor 86 in accordance with the conductance of the associ ated one of the resistors 72 to 79 since whenever a transistor 82 is on, the transistor 81 of the same switch is off.For example, if the base of the transistor 82 of the switch S2A receives binary 1,thistrans- istor 82 is on and passes substantially all the current allowed by the transistor 80 connected to the resistor 77, thereby starving the transistor 81 of S2A.

A digital to analog converter which includes the output stage shown in Fig. 6 will now be described in more detail with reference to Figs. 8 to 14.

Fig. 8 is a block diagram illustrating the operations effected in the converter.

Atwenty-three bitbinarycoded parallel digital input is clocked into an input register 101 by an input clock pulse train and is loaded in parallel at times determined by a timing and clock pulse generator 102 into a multiply-by-3 unit 103, the pulse generator 102 acting on a selector device 104 which determines whether the multiply-by-3 unit 103 receives its input from the input register 101 or a twenty-three bit recycle register 105 which is loaded in parallel by the multiply-by-3 unit 103 attimesdetermined by the pulse generator 102.Under the control of the pulse generator 102, the input register 101, the selector device 104, the multiply-by-3 unit and the recycle register cooperate to convert each digital input into a binary coded ternary serial output from the multiply-by-3 unit 103 which is converted into a binary coded ternary parallel output by a serial to parallel converter 106 which is controlled by the pulse generator 102 and supplies a resetting pulse to the pulse generator 102 when the converter 106 is fully loaded. The contents of the converter 106 are loaded into an output register 107 which, under the control of the pulse generator 102, drives a set of level changers 108 supplied with positive and negative reference voltages, and constituted by the pairs 60 to 71 of switching units A of Fig. 6.As shown in Fig. 6, the level changers 108 are connected to an analog summing network 109 constituted by the resistance ladder of Fig. 6 which is connected to the output amplifier 57.

The multiply-by-3 unit 103 and the recycle register 105 carry out the repeated multiplication by 3 which is necessary to convert the binary base 2 input regarded as a fraction into the corresponding binary coded base 3 fractions. For example, using only four digits, the base 2 binary coded fraction .1101, which represents 1/2 + 1/4 + 0 + 1/16 = 13/16 = 0.8125. To convert the base 2 binary coded fraction into a base 3 binary coded fraction, multiplication by 3 of the fraction, then the fractional part of the first product, then the fractional part of the second product, and so on, is carried out to generate a series of pairs of digits, namely the integral parts of the successive products, which constitutes the binary coded base 3 fraction.Thus, from .1101 .0111 .0101 .1111 .1101 .0111 .0101 .1111 01.1010 .1110 .1010 1.1110 1101 .0111 .0101 .1111 10.0111 01.0101 00.1111 10.1101 the binary coded base 3 fraction is. (10) (01) (00) (10) recurring as a whole. Using 2, 1 and 0, this becomes .2102210 approximately, i.e. 2/3 + 1/9 + 0/27 + 2/81 +2/243 + 1/729 = 592/729 = 0.8121. The accuracy of the conversion increases with the number of digits involved.

Fig. 9 shows the input register 101, the multiply by-3 unit 103 and the recycle register 105 in more detail, the manufacturing codes of integrated circuits being indicated.

The input register 101 is formed by three inte grated circuit registers R1, R2 and R3 arranged to receive eight, eight and seven bits. The sign bit is inverted by an inverter 110 to convert the twenty-two bit positive integers and twenty-three bit two's com plement negative integers into a range of all positive integers having a mid-point at 222. The digital input is updated at a rate of once every 20 microseconds and is sampled by the input register 101 at the rising edge of each input clock pulse, the input clock pulses occurring once every 20 microseconds.A selection pulse is supplied to the respective inverted output enable input terminals of the registers R1, R2 and R3 by an output connection 111 from the timing and clock pulse generator 102 once every 20 mic rosecondsto load the contents of the input register 101 into six integrated circuit ladders Al to A6 which form the multiply-by-3 unit 103. The multiplication by 3 is effected by multiplying the input to the unit 103 by two and adding the resulttothis input. The fractional part of the result of the multiplication by three is loaded into the recycle register 105 which is formed by three integrated circuit registers R4, R5 and R6, the register R4 receiving the first seven most significant bits of the fractional part, the register R5 receiving the intermediate eight significant bits, and the register R6 receiving the eight least significant bits. The loading of the recycle register 105 occurs at a signal supplied by the pulse generator 102 on an output connection 112 which is connected to the respective clock input terminals of the registers R4, R5 and R6.A further output connection 113 from the pulse generator 102 supplies an enabling pulse to the inverted output enable input terminals of the registers R4, R5 and R6 during the time that the enabling pulse on the connection 111 to the input register 101 is not present. The data output terminals of the registers R1 to R6 are three state terminals, i.e.

each is in a high data output state or a low data output state or a high impedance state, the high impedance state occurring whenever the respective register is not enabled to provide data output signals. Thus the selector device 104 of Fig. 8 is constituted by the registers 101 and 105 themselves and the connections shown in Fig. 9 between the data output terminals ofthese registers 101 and 105 and the data input terminals of the six adders Al to A6 The integral portion of the output of the multiplyby-3 unit 103 appears as the most significant data output bit and the carry output bit of the adder Al, the output terminals 114 and 115 respectively for these bits being connected respectively to the input terminals of a two input NOR gate G2, and the terminal 115 being connected to an inverter G1.The inverter G1 and the gate G2 therefore transform binary output pairs (1,0), (0,1) and (0,0) at the terminals 115 and 114 into (0,0), (1,0) and (1,1) respectively. The latter binary pairs are subsequently transformed by inversion into (1,1), (0,1) and (0,0) respectively for use as control signals to be applied to the switching unit pairs 60 to 71 of Fig. 6. Twelve binary pairs are generated from each sampled digital input.

Fig. 10 shows the timing and clock pulse generator 102 in detail and two, three-input NAND gates G9 and G10 to which the inverter G1 and the NOR gate G2 of Fig. 9 are connected respectively and by which, under the control of timing pulses appearing at the input terminal 116 and the outputterminal 117 of an inverter G5, to which terminals 116 and 117 the gates G10 and G9 are respectively connected as shown, each parallel binary output pair of bits, produced by the inverter G1 and the NOR gate G2 is transformed into the required serial binary bit pair.

Input and output pulses for the pulse generator 102 are illustrated graphically in Fig. 11.

Fig. 12 shows the serial to parallel converter 106 and the output register 107. The serial to parallel converter 106 is formed by three, eight bit shift registers S1,S2 and S3. When the serial to parallel converter 106 is fully loaded, the shift register S1 contains the four binary digit pairs representing the four most significant ternary digits, the shift register 82 contains the four binary digit pairs representing the intermediate four ternary digits, and the shift register S3 contains the four binary digit pairs representing the four least significant ternary digits.

Each of the shift registers S1, S2 and S3 has a dual input gate 118, 119 or 120 respectively. The output terminal for the most significant output bit of the shift register S2 is connected to both input terminals of the input gate 120 of the shift register S1, and the output terminal for the most significant output bit of the shift register S3 is connected to both inputter minals of the input gate 119 of the shift register S2.

The input gate 118 of the shift register S1 has one input terminal 121 connected to the output terminal of the NAND gate G9, and the other input terminal 122 connected to the output terminal of the NAND gate G10.

The clock input terminals of the three shift regis ters S1, S2 and S3 are connected to the output ter minal of a two input NOR gate G7. One input to the NOR gate G7 is supplied by the Output terminal of a D-type bistable circuit F1, and the other input to gate G7 is supplied by the Q output terminal of a D-type bistable circuit F3 to which the first bistable circuit F1 is coupled by another D-type bistablecir- cuit F2 as shown in Fig. 10.The three bistablecircuits F1, F2 and m are connected as a shift register which receives clock pulses in the form of a clock train at 25.6 Megahertz, and data pulses as a result of the gating of another input train of pulses designated SYNC 1 by a NAND gate G4 after inversion by an inverter G3. The NAND gate G4 is controlled by a D-type bistable circuit F4 which receives the Qout- put of circuit F1 as clock pulses, and is in turn con trolled by an inputtrain of pulses designate SYNC 2 twice inverted by successive inverters G11 and G8, and a flag output connection 123 from the shift regis ter S1 of the serial to the parallel converter 106.

The clock train at 25.6 megahertz, SYNC 1 and SYNC 2, the Q outputs of the four bistable circuits F1 to F4 and of two further bistable circuits F5 and F6, the output of the NOR gate G7, and the output of another NOR gate G6 are illustrated in Fig. 11. In Fig.

11, the left and right hand portions of the figure are on a smaller scale for time than the central portion of the figure, the same horizontal distances in the three portions representing substantially 32 times the duration in the left and right portions than in the central portion. The 25.6 megahertz clock train is shown only in the central portion of Fig. 11. The SYNC 1 pulses are high pulses with a duration of substantially 39 nanoseconds and occur once every 1.25 microseconds. It will be seen that the duration of a SYNC 1 pulse is substantially equal to one period of the 25.6 Megahertz clock train. The SYNC 2 pulses are low pulses which occur once every 20 microseconds and last for substantially 300 nanoseconds. The SYNC 2 pulses are arranged to occur after every sixteenth pulse in SYNC 1.

From Fig. 11, it will be seen that each SYNC 1 pulse is clocked into the circuit F1 and is shifted through F2 and F3 by the 25.6 megahertztrain. Since the inputs to the NOR gate G7 are the Q outputs of F1 and F3, the gate G7 in effect selects Q of F1 and Q of F3 to produce a pair of shift clock pulses spaced by sub stantially 39 nanoseconds for the serial to parallel converter 106.

The NOR gate G6 has its input supplied by Q of F1 and Q of F2 respectively and therefore produces a pulse starting shortly after the leading edge ofQ of F1 and ending shortly after the leading edge of Q of F3 as shown in the central portion of Fig. 11. The output terminal of the gate G6 is connected to the input terminal of the inverter G5, so that, when the NAND gates G9 and G10 are enabled by the Q output of the bistable circuit F5, the gate G9 is opened by the output of the inverter G5 before the first shift i clock pulse produced by the gate G7, and is closed throughout the interval between the leading edges of the shift clock pulse pair, the gate G10 being opened during this interval and closed at other times. Consequently the output ofthe gate G1 is inverted and entered into the serial to parallel con verter 106 at the first shift clock pulse of a pair of such pulses, and the output of the gate G2 is inverted and entered into the converter 106 at the second shift clock pulse.

Atiming sequence by the generator 102 in initiated by the arrival of a SYNC 2 pulse. This pulse resets the three bistable circuits F4, F5 and F6. The resetting of the bistable circuit F4 opens the NAND gate G4 and allows SYNC 1 pulses to enter the bistable circuit F1. The resetting of the bistable circuit F5 causes the first pair of shift clock pulses generated by F1 and F3 to enter a flag pair (1, 1) into the serial to parallel converter 106, since both gates G9 and G10 have binary 1 at their output terminals whenever F5 is in its reset state. At the end of the first shift clock pair of pulses, F3 resets automatically and thereby clocks F5 which sets and thus enables the NAND gates G9 and G10. The bistable circuit F5 then remains set until the arrival of the leading edge of the next SYNC 2 pulse.

The bistable circuit F6 is reset at the same times as the bistable circuit F5, but does not set until F3 resets while F5 is set, the Q output of F5 being supplied as the D input to F6.

In the reset state of F6, the low Q output of F6 is supplied on the output connection 111 to the input register 101 to load the contents of the input register 101 into the six adders Al to A6 of the mu Itiply-by-3 unit 103. When F3 resets afterthe flag pair (1,1) and the first ternary digit have been clocked into the serial to parallel converter 106, F6 sets and the resultant lowO signal of F6 appears on the output connection 113 and causes the contents of the recycle register 105 to be loaded into the six adders Al to A6 continually while F6 remains set, i.e. until the arrival of the leading edge of the next SYNC 2 pulse.

The bistable circuit F4 remains reset until the signal on the flag output connection 123 from the shift register S1 goes high, whereupon F4 is set by the arrival of the next occurring low Q output of F1.

The setting of F4 closes the gate G4 and thus prevents further shift clock pulses from being generated by F1 and F3 until F4 is reset by the arrival of the next SYNC 2 pulse. The signal on the flag output connection 123 goes high when the flag pair (1,1) clocked into the serial to parallel converter 106 immediately after the previous SYNC 2 pulse reaches the most significant data output terminal of the shift register S1.Since the serial to parallel converter 106 has a capacity of twelve binary pairs, and the timing of SYNC 1, SYNC 2 and Q of F4 are such that thirteen shift clock pulse pairs and a corresponding thirteen high outputs from gate G6 are generated between one SYNC 2 pulse and the next, as the last ternary digit, i.e. twelfth binary pair, is clocked into the shift register S1 by the thirteenth shift clock pulse pair, the flag pair (1,1) clocked in by the first shift clock pulse pair emerges from the most significant digit output terminal of the shift register S3.

Each SYNC 2 pulse, through the inverters G11 and G8, clears the shift registers S1, S2 and S3 of the serial to parallel converter 106 by being applied to their respective clear input terminals 124. The leading edge of each inverted SYNC 2 pulse supplied by the inverter G11 to the respective clock input terminals of the registers R7, R8 and R9 of the output register 107 through a clock output connection 125 of the generator 102 loads the parallel outputofthe serial to parallel converter 106 into the output register 107 just before the serial to parallel converter 106 is cleared.

Each of the registers R7, R8 and R9 has an inverted, output-enable input terminal OE which is connected permanently to ground so that the contents of the output register 107 appears continually at its twenty four data output terminals which are connected respectively to the twenty four switching units A of Fig. 6 which formed the level changes 108.

Fig. 13 shows the filtering circuitry which provides two reference voltages, VDD and Vss for each switching unit A. These reference voltages are thereby held steady substantially at +5 volts and -5 volts respectively. Fig. 14 shows the circuitry that each switching unit A is constituted by. The respective outputtermi- nal of the output register 107 is connected to an input terminal 126 coupled by a 4.7 kilohm resistor to the base of PNP transistor 127 having its emitter connected to a positive supply rail at +5 volts and its collector coupled by a 4.7 kilohm resistor to a negative supply rail at -5 volts. Base bias is provided by a 1 kilohm resistor coupling the base of the transistor 127 to the position supply rail.The voltage at the collector of the transistor 127 is coupled by a 10 kilohm resistor to both input terminals of a CMOS NAND gate 128 supplied with the reference voltages VDD and Vss. The output terminal of the NAND gate 128 is connected to the non-inverting input terminal of an operational amplifier 129 provided with feed backto its inverting input terminal from its output terminal 130 through the movable contact 131 of an adjusting potentiometer 131 with a maximum resistance of 220 ohms connected in series with a 10 kilohm resistor to ground.The high input impedance of the operational amplifier 129 imposes substantially no load on the output of the NAND gate 128 which can therefore switch precisely to VDD or V The adjusting potentiometer 131 allows the gain of the operational amplifier 129 to be varied by t 1% about a nominal gain of 1.01, i.e. between 1.00 and 1.02. This adjustment of gain in each switching unit A enables any inaccuracies in the analog resistor ladder connected to the switching units A to be compensated for.

Each of the pairs 60 to 71 of switching units A together with the two 2 kilohm resistors and single 500 ohm resistor coupling the units to the respective junction point acts as a three level switch having an output resistance of 1.5 kilohms, the three levels being VDD, 0 and Vss volts.

The digital to analog converter described herein before with reference to Figs. 6 and 8 to 14 is especially suitable for use in converting digitised audio signals into analog signals. The linearity and resolution of the analog output of this converter at the middle region of its range for digital input signals, which is the result of the small number of switching units A affected by variations about the midpoint, enables a large dynamic range to be provided for audio application. It has been shown experimentally that audio signals need be quantised to not more than substantially thirteen significant bits.

Consequently subjectively good performance can be obtained from the present digital to analog converter by trimming the gains of the switching units A to this accuracy.

Although in the embodiments described hereinbe fore in which the switching units A are used the reference voltages are maintained at fixed levels, in other embodiments the reference voltage or voltages, or currents may be arranged to be variable so as to provide a means of varying the overall gain of the digital to analog converter

Claims (8)

CLAIMS:

1. A digital to analog converter having input means for receiving digital signals representing a variable quantity and for converting received digital signals into control signals with a predetermined relationship to the received signals, an arrangement of resistors and controllable switches for controlling current flow in the resistors, the said arrangement being coupled to a common outputterminal and the input means being so coupled to the said arrangement as to supply control signals to the controllable switches, and reference means for applying at least one reference analog signal to the said arrangement, the input means and the said arrangement being such that, in dependence upon the states of the controllable switches, an analog output'signal can be established by the said arrangement at the common outputterminal having any value allowed by a predetermined resolution error within a range of values having a mid-point from which departures in either direction are effected by changes in the states of selected controllable switches of the said arrangement, each controllable switch controlling a respective contribution to the analog output signal, each contribution having a respective magnitude such that the magnitudes of the contributions constitute at least two sets each of which is representative of an ordered set of numbers formed by the zero power and successive higher powers of a common radix, and the said switches can be so controlled by the input means that pairs of contributions of equal magnitude can be contributed to the analog output signal.

2. A digital to analog converter according to claim 1, wherein there are at least two reference analog signals which have opposite polarities and the said arrangement is such that each of the said contributions can have either of the two polarities in dependence upon the state of the respective controllable switch, and the said input means is operable so that the mid-point of the range of the analog output signal is produced whenever the states of the said switches are such that all the contributions constituting one of the said two sets are of one polarity and all the contributions consisting the other of the said two sets are of the other polarity.

3. A digital to analog converter according to claim 1 or 2, wherein the input means is such that whenever the input means receives a series of digital signals requiring there to be a departure which is in either direction from the mid-point, a sequence of individual ones and groups of the controllable switches have their states changed by the input means, the sequence being such that the corresponding sequence of contributions and combined contributions affected by the changes of state is representive of a plurality of successive numbers of increasing magnitude in a numerical system based on the said common radix, and the number of switches whose states are changed at any stage in the said sequence being independent of the direction of the departure from the mid-point.

4. A digital to analog converter according to any preceding claim, wherein the contributions which constitute a set are such thatthe ratio of the magnitudes of any member and its neighbour or each neighbour is equal to the said common radix, and the said common radix is two orthree.

5. A digital to analog converter according to claim 4, wherein the common radix is three, and the said input means is such that the control signals are produced in pairs to control pairs of the switches, each switch of such a pair controlling a contribution having the same magnitude as the contribution controlled by the other switch of the pair, and each such pairofcontrol signals representing a binary coded tenary number and to convert a digital input signal in base 2 binary form into a binary coded tenaryform, the input means includes means for multiplying by three the base 2 number represented by each digital input signal received by the input means.

6. A digital to analog converter according to any preceding claim, wherein the switches are each in the form of switching unit having two states, the state being determined by a control signal in binary form, and the switching unit having an outputterminal at which either one of two reference voltages appears in accordance with the state of the switching unit

7. A digital to analog converter substantially as described hereinbefore with reference to any one of Figs. 1 to 5 or7 of the accompanying drawings.

8. A digital to analog converter substantially as described herein before with reference to Figs. 6 and 8 to 14 of the accompanying drawings.