US3510868A

US3510868A - Non-linear decoder

Info

Publication number: US3510868A
Application number: US577896A
Authority: US
Inventors: Andre Edouard Joseph Chatelon
Original assignee: International Standard Electric Corp
Current assignee: International Standard Electric Corp
Priority date: 1965-09-15
Filing date: 1966-09-08
Publication date: 1970-05-05
Anticipated expiration: 1987-05-05
Also published as: FR1460676A; NL6612942A; ES331206A1; CH454221A; GB1105717A; BE686332A; DE1462704B2; DE1462704A1

Description

May 5, 1970.

Filed Sept. 8, 1966 Fig.1 (0) Fig.1(d)

A. E. J. CHATELON 3,510,868

NON-LINEAR DECODER 5 Sheets-Sheet 1 Fig.1(b) Y Fig/1(0) Fi .1(e)

Fig.1(f)

I inventor ANDRE E. J. CHATELON May 5, 1970 A. E. J. CHATELON NON-LINEAR DECODER Filed Sept. 8. 1966 5 Sheets-Sheet 2 Illlulllil'llilll'lll'lllll'lll-llllllllii.

I n ventor ANDRE 6. J. (f/A TLON KQSW R United States

Patent

3 ,5 Int. Cl. H03k 13/04 US. Cl. 340347 7 Claims ABSTRACT OF THE DISCLOSURE A non-linear PCM decoder wherein the digits of a code group to be decoded are first stored in stages of a register. A preliminary decoder is coupled to the stages of the register storing the x most significant weight digits of the code group to provide a first control signal indicating the straight line segments of the input-output characteristic which are represented by the stored code group. A first signal generator coupled to the preliminary decoder and the stages of the register storing the most significant weight digits of the code group acts to produce a second control signal indicating the lowest voltage of the segments. A second signal generator operated responsive to said first control signals and the stages of the register storing the m least significant weight digits of the code group to produce a third control signal indicating a position along the segment indicated by the second control signal. A ladder attenuator and current generators are provided which respond to the second and third control signals to produce the analog signal represented by the stored code group at the output of the attenuator.

The present invention concerns a non-linear decoder for converting binary numbers into analog quantities.

Such non-linear digital to analog decoder may be used on the one hand as a decoder-expanser and on the other hand as a decoder associated to a coder-compressor, the coding being carried out by the feedback comparison method.

Feedback coding consists in comparing the analog value representing a number stored in a register to the signal to be coded, thus enabling to determine whether the number is too big or too small. In the first case, this number is reduced, in the second case, it is increased. These comparison operations are carried out up to the time when the voltages compared do not differ at the most by the value of one quantization step.

When the used decoder is not linear, the coding is carried out according to a non-linear characteristic curve. Since the same decoder may be used for coding and for decoding, the compression and expansion characteristics are then perfectly complementary if said decoder presents reproducible characteristics.

Non-linear decoders which make use of a resistance network and which enable to obtain an hyperbolic characteristic are known. These resistances, the extreme values of which are in the ratio 2, must be switched in accordance with the value of the number to be decoded. But it is known that any resistance presents a certain reactance which depends upon its value. If the switching frequency is high, the effect of this reactance becomes important, and the value of the corresponding complex impedance depends upon the number to be decoded. It is thus realized that a decoder which comprises resistances having such different values is difficult to achieve and cannot provide a high accuracy. Besides, when an electronic switch is used for sampling the signal to be coded, the said switch pre- 3,510,868 Patented May 5, 1970 sents, when it is conducting, a series resistance (saturation resistance in the case of a transistor) which is not negligible in respect to the small value resistances of the network, and which introduces a new source of errors.

To overcome the difiiculties of obtaining a continuous non-linear characteristic, the U8. Pat. No. 3,298,017 entitled Non-Linear Decoder, which issued Jan. 10, 1967 and is assigned to the assignee of this invention, has described a decoder achieved in such a way that its characteristic curve is constituted by a series of straight line segments of different slopes; these slopes can be chosen in such a way as to be, for instance, approximately tangent to a logarithmic curve.

The operation of this decoder will be briefly reviewed by recalling an example wherein the numbers or codes which are applied to it comprise n=7 digits, and that the voltages corresponding to the zero and to 2 codes are equal respectively to zero and Ed, the codes 2 -1 and 2 being located on both sides of the voltage Ed/2 which characterizes the mean value of the signal in the case where the codes represent alternating voltages. Each one of these voltage ranges of amplitude Ed/Z is divided into three coding zones C1, C2, C3, to which correspond, respectively, 32, 16 and 16 codes, and in which the values of the quantization steps are different. Thus, in the zone C1 which corresponds to the lowest voltages in absolute value on both sides of the origin, the value of this step is equal to V. In the zone C2, it is equal to 8 v., and in the zone C3, it is equal to 64 v. A characteristic curve is thus defined, constituted by six segments, the slopes of which are proportional to the different values of the quantization steps.

In order to obtain the analog voltage corresponding to a given code, the zone to which it belongs is first determined, this operation being carried out easily by decoding a group of its more significant digits, for example, its four more significant digits, since each zone comprises a number of codes equal to an integral power of two. The zone signal thus obtained is used on the one hand for elaborating a base voltage or pedestal equal to the voltage which corresponds to the maximum code of the immediately preceding zone, and on the other hand, a complementary voltage representing the position of the code in the zone to which it belongs; this voltage being obtained by decoding linearly the less significative digits with a weighting corresponding to the value of the quantization step in the zone. These two voltages are then added in order to obtain the analog voltage corresponding to the code.

In a transmission system using this circuit, for feedback coding and for decoding, a substantial increase of the distortion level is observed at the connection between the adjacent zones. Obviously, the distortion is the more important as the ratios between the consecutive slopes of the compression curve are higher, i.e. when the number of zones is smaller.

In order to take full advantage of the compression, it is thus necessary to smooth the characteristic curve, i.e. to increase the number of slopes. It will be noted that if it is required to set up a non-continuous characteristic curve in which the ratios between the consecutive slopes are all equal, the envelope of this curve is a true logarithmic function.

The object of the present invention is thus to realize a non-linear decoder with a non-continuous characteristic which yields low distortion values when used for the feedback coding, and for the decoding of low frequency signals.

The present invention will be particularly described with reference to the accompanying drawings in which:

FIG. 1 represents a certain number of symbols used in FIG. 3,

FIG. 2 represents the characteristic curve of the decoder according to the invention,

FIG. 3 represents the detailed diagram of this decoder,

FIG. 4 represents the same characteristic curve as that of FIG. 2 using a non-linear scale on the abscissae axis,

FIG. 5 represents the elaboration circuit of the control signals of the complementary voltages.

Before starting the description of the invention, one will briefly remind the principle of notations in logical algebra which will be used in certain cases, in order to simplify the writing in the description of the logical operations. The subject is treated extensively in numerous papers and in particular in the book Logical Design of Digital Computers by M. Phister (J. Wileypublisher).

Thus, if a condition characterized by the presence of a signal is written A, the condition characterized by the absence of said signal will be written K. These two conditions are linked by the well known logical relation A Z=0, in which the sign X is the symbol of the coincidence logical function or AND function.

If a condition C appears only if the conditions A and B are simultaneously present, one writes A B=C and this function may be carried out by means of a coincidence or AND circuit.

If a condition C appears when at least one of two conditions E and F is present, one writes E+F=C and this function is carried out by means of a mixing gate or OR circuit.

Since these AND and OR logical functions are commutative, associative and distributive, one may write:

Last, a function of two variables A andB may present four possible combinations and, if one writes A B,the three other combinations are globally represented by the expression AXB.

One will also specifiy, in relation with the FIG. 1, the meaning of some particular symbols used in the drawings which come with the description of the invention. Thus:

FIG. 1a represents a simple AND circuit,

FIG. 1b represents a simple OR circuit,

FIG. represents a bistable circuit or flip-flop to which a control signal is applied over one of its input terminals 92-1 or 92-0 in order to set it in the 1 state or to reset it in the 0 state. A voltage of same polarity as that of the control signal is present, either on the output 93-1 when the flip-flop is in the 1 state, or on the output 93-0 when it is in the 0 state. If the flip-flop is referenced B1, the logical condition which characterizes the fact that it is in the 1 state will be written B1 and that characterizing the fact that it is in the 0 state will be Written F1,

FIG. 1d represents a group of several conductors, ten in the considered example,

FIG. 1e represents a decoder which, in the case of the example, transforms a four-digit binary code group applied over the group of conductors 94a into a 1 out of 16 codes, so that a signal appears on only one among the sixteen conductors 94b for each one of the code groups applied at the input,

FIG. 1 represents a current generator supplied by a voltage source +V. This generator, which is triggered by a control signal applied to its input terminal 940, delivers a constant current of amplitude I in the resistor R of very low value compared to the internal impedance of said generator.

The generators shown on FIG. 3 are not referenced but one understands that they can be referenced unambiguously by their control signals.

One will characterize by a particular expression the position of a given digit in a binary code group and, by extension, the position of the flip-flop, in a counter or a register, which stores said digit. One will thus say that the most significant digit of a code group is the digit of rank 1, the next significant digit being then the digit of rank 2, etc. One will note that this notation is independent from the utilized code which may be weighted or not.

The FIG. 2 represents the characteristic curve e=f(N) of the decoder according to the invention, designed to make correspond to N codes comprising at least four digits, voltages the average value of which, in the case of sinusoidal voltages, is equal to Ed/ 2 and the peak amplitude of which is equal to The codes formed by the four most significant digits have been shown between parentheses on the ordinate axis NIN, and the range of decoded voltages which extends from zero volt to Ed has been represented on the abscissae axis OIe.

This characteristic curve is discontinuous as it is constituted by a succession of straight line segments of different slopes. It is symmetrical with respect to the point I and presents, in each one of the first and third quadrants, seven coding zones, the ratios between the slopes of the adjacent zones in each one of these quadrants being equal to 2, as it may be seen from Table I hereafter. In this table, the column 1 is assigned to the zones C1 to C7, the column 2 to the slope in each one of these zones (in volts per code), the column 3 to the number of codes per zone, the column 4 to the number of unit quantization steps V in each zone, and the column 5 to the fraction of the voltage range Ed/ 2 occupied by each zone.

On FIG. 2, the coding zones concerning the codes of which the digit of rank 1 is 0 have been referenced C1 to O7, and those concerning the codes for which this digit is 1 have referenced C"1 to C7. Since the characteristic curve is symmetrical with respect to the origin I of the coordinates, it is understood that the zone 01, for instance, of the Table I corresponds to the zones U1 and C"1 of FIG. 2. The construction of the characteristic curve in each one of the quadrants it occupies may be easily deduced from the indications given in the column 5 of Table I.

TABLE I Number of quantizing Number of steps in Fraction codes the zone of Ed/2 Norm-Total number of quantizing steps=1,024.

FIG. 3 represents the general diagram of the decoder according to the invention which comprises: the register RG comprising the flip-flops B1 to B7 for the storage of codes comprising n=7 digits, the zone decoder ZD, the generator of pedestal signals PC, the generator of complementary signals LD, and the averaging and summation circuit WR which supplies, on its output X, a voltage characterizing the value of the codestored in the register RG.

The outputs of the flip-flops B1 to B4 are applied to the zone decoder which comprises the twenty-one following outputs:

G1 to O7 and C"1 to C7 characterizing the zones defined by the digits of rank 1 to 4 represented on FIG. 2,

C1 to C7 characterizing the homologous zones of the two parts of the characteristic curve such as they are defined in column 1 of Table I.

The role of the generators PC and LD is to supply to the circuit WR control signals which characterize, re-

spectively, the decoded minimum voltage of each coding zone, and the code position in the zone.

The averaging and summation circuit WR comprises a ladder attenuator supplied by current generators the type of operation of which, well known in itself, has been described in the patent mentioned hereabove.

Since the terminating shunt resistors of this attenuator have a value R, by choosing values 2R and R respectively for the other shunt and series resistors, an attenuator is obtained having a characteristic impedance 2R/3 which brings an attenuation of two per cell.

It results therefrom that if a current I is injected at the point Q0, a voltage appears between the point X and ground, and that, if the injection point is moved towards the left of the figure, the voltage Vx decreases each time by a ratio of two. It is 6 C6 and to the value of the quantization step of this zone are added to this voltage U'o.

At each zone change, the operation is carried out in a similar way, at least up to the zone C1 the pedestal of which is constituted by the sum of the voltages U'o, U'l, U2, U'3, U4, U'S, respectively equal to 512 v., 256 v., 128 v., 64 v., 32 v. and 16 v.

Table II hereafter represents the different pedestal voltages used. It comprises the

lines

1, 2, 3, reserved respectively to the value-given in quantization unit stepsof the voltage, to the reference of the voltages, and to the reference of the current generator set into operation in the circuit WR.

This table comprises also the columns a and b assigned respectively to the fourteen coding zones and to the four most significant digits of the codes which characterize said zones.

In this table, the generators set into operation for the ditferent zones are represented by crosses located at the cross-points of the corresponding columns and lines.

TABLE I1 1 Weightin 512 256 12s 64 32 1e 32 64 12s 256 512 2 Zone l Z decoding UO Ul W2 W3 U4 u's U"4 U3 U2 U1 U0 one a B1 B2 B3 B4 PO Pl P2 P3 P4 P'5 1 4 P3 P2 P1 P0 o 0 0 0 0 1 X o 1 0 X X 0 1 1 X X 1 0 0 X X 1 a (1 X 1 1 1 X X 0 0 1} X X o 1 0 X X 0 1 1 X X 1 0 o X X 1 0 1 X X 1 1 0 X X 1 1 1 X X X thus seen that the attenuation ratio is a negative power of two, the exponent of which is given by the digit associated to the reference letter of the injection point. Thus, a current injected at point Q2 generates a voltage attenuated by the ratio 2F A with respect to the same current injected at the point Q0.

Besides, if currents supplied by two identical generators of high internal resistance with respect to the characteristic impedance are injected in a given point, the currents add and the output voltage is doubled.

The method used for the choice of the pedestal voltages will be first studied, in relation with FIG. 4. This figure represents the same characteristic curve as that of FIG. 2, but it is set up by using a non-linear scale on the abscissae axis. The abscissae values corresponding to the zone changes are shown between brackets, and it is seen that the scale used enables to assign the same length, on

the abscissae axis, for each coding zone.

The decoding voltages corresponding to the codes of the zone 07 range between zero volt for the code the decimal equivalence of which is zero, and

for the code the decimal equivalence of which is 7. These are complementary voltages elaborated as it will be seen further on under the control of the signal supplied by the circuit LD.

As it has been seen previously, the pedestal for the zone 01 is constituted by the sum of the voltages UO to U'5.

In order to obtain the pedestal of the next zone C"-1, a voltage of amplitude equal to 16 v. may be added to the pedestal of the zone C1 and so on, until thirteen added voltages are obtained for the zone C"7. Nevertheless, the number of components used would thus be increased uselessly. Since it is required mainly to keep a relative constant accuracy, the pedestal voltages for the zones C"1 to C"7 are chosen in a particular way.

Thus, the pedestal of the zone C1 is obtained by adding the voltages UO to U4 plus a voltage U"4 of amplitude 32 v. The other pedestals used for the zones C"2 to C"7 are obtained in a similar way as it may be seen in Table II and FIG. 4. This last figure has been drawn in order to show how the pedestal voltages add up and if one examines, for instance, the dotted line ending at the reference C"4 written in the column C at the left of the figure, one sees that the pedestal for this zone is obtained by adding the voltages U'O, U'l, U2, U3 and U"2.

The circuit PC supplies, in accordance with the indications given in Table II, a certain number of signals for the control of the generators in the circuit WR.

The logical conditions of elaboration of these signals are deduced immediately from Table II. Thus, it is seen that the signal P'0, used for triggering the generator hearing the same reference, must appear when at least one of the flip-flops B1 to B4 is in the 1 state, viz.:

In the same way, the signal P 8 The Table III hereafter gives the whole of the logical elaboration of signals of control of complementary voltconditions set up in the generator PC. ages.

TABLE In FIG. represents a part of the circuit LD which receives the signals C1 to C7, B4 to B7, and which com- Control signal: Logical conditions prises twenty-two AND circuits in a matrix arrangement P5a C'1+C2 and which supplies the twenty-two output signals repre- P4 C1+C2+C"3+C"7 sented on the right side of the figure. P4a C"7+C"1+C"2 In order to simplify the figure, the AND circuits have P'3 P4-l-P'3a (P'3a=C'3+C"4 not been referenced, though it is realized that they carry P"3a C"3 10 the same references as the output signals. PZ P'3+C'4+C"'5 The digits associated to the reference F of the output P"2a C4 signals have an accurate meaning: thus, the first digit, P'l B2+B3+B4 from 1 to 7, characterizes the zone for which this signal P"1a C"'5 appears, and the second digit, from 4 to 7, characterizes P'tl B1+B2+B3+B4 the rank of the flip-flop which has controlled the genera- P0 C6+C"7 tion of the signal when setting in the 1 state. When a reference such as P5 is followed by an index Thus in the Zone the eohdihon B5XBQXB7 a or b, this means that the generator P5 may be controlled, (cede 211-1) does not control the generation of y 5181131,

through an OR circuit, either by a signal P5a or by a the condition X X (Code E the signal PSb, this signal being supplied by a circuit LD the generation of the signal F17, the condition B5 B6 B7 operation of which will be studied now. induces the generation of the signal F16, etc.

' TABLE IV 5 Injection Point Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q Q Weighting As it has been seen previously, the role of this circuit Table IV presents a classification of these signals F in is to supply to the circuit WR control signals for the cur accordance with the zones to which belong the codes, and rent generators, in order to elaborate a complementary with the current injection points controlled by these sigvoltage which characterizes the code position in the zone, 40 nals. The last line carries the reference of the control this voltage being added-in the ladder attenuator-to the signal elaborated by the mixing, in the OR circuits, of the pedestal voltage. signals F carried in a same column, these OR circuits be- For the zone C"1, the value of the quantization step ing placed in the circuit LD.

is V, and it will be noted that the complementary voltage One has thus, for instance:

is obtained by the decoding of the flip-flops B4 to B7,

since this zone comprises sixteen codes whereas the com- P9=F17 plementary voltage related to the other zones which com- P8=Fl6+F27 prises only eight codes is supplied by the decoding of the 7=F15+FZG+F 7 flip-flops B5 to B7. In this zone C1, the code 2 (logical condition: BZXEXBTXBT) controls the generation of the pedestal voltage UO-l- U'4+U"4. The next The control signals shown in the left side column of code 2 +1 (logical condition: B IXKEXE 'B Z) m t Table III and in the lowest line of Table IV are applied, control the elaboration of a complementary voltage V, in the Circuit WR t0 the control inputs of the that the code 2 +2, the elaboration of a complementary current generators. Two generators are connected to each voltage 2 v., etc. Since one of the points Q0, Q1, Q2, Q3, Q4, the first one of these being controlled by a signal Whose reference is fol- V lowed by the sign and the second by a signal whose =2- reference is followed by the sign Besides, some of these generators are controlled by a two-input OR circuit. 0 This case occurs when two signals written in the Tables the h 2n 1+1 will trigger the e 'e connected to III and IV bear, on the one hand, the same reference the point, P9, the code 2 +2 will trigger a gene digit-this meaning that they control the injection of a connected to the Pomt current at the same point of the attenuator-and on the In the h clz h Va h1e Pi unit Step is 2 50 other hand, 'difierent small letters a and b. It will be that the logleal cohdltloll B5 X X controls the elaho- 5 noticed in fact that these two signals cannot appear simulrition of a complementary voltage 2 the condition taneously: thus, the signal P3a is elaborated for the B5 |B6 B7 the elaboration of a voltage 4 v., etc zone C"3, and the signal P"3b is elaborated for one of As the zones C5, C6, C7.

2V It has been shown, in the patent mentioned hereabove,

=2- that if the last generator set into operation was replaced,

at the passage from the zone Cl to the zone C1, by a generator connected to an injection point of lower index, the first one of these conditions will trigger a generator an amplitude distortion of the decoding signal takes place connected to the point P8, etc. together with an amplification of the noise. Thus, in the FIG. 5 and Table IV hereafter concern the mode of decoder just described, the generator P5 is replaced by TABLE V Control signal: Logical conditions Pa C1+C"2 P ls Clll P'4 C1+C2+C3+C"7 P"4a C"2+C7 While the principles of the above invention have been described in connection with specific embodiments and particular modifications thereof it is to be clearly understood that this description is made by way of example and not as a limitation of the scope of the invention.

' I claim: a

1. A non-linear decoder for translating n-digit binary code groups into voltages represented thereby having a non-linear code group input vs. voltage output characteristic formed from a plurality of successive straight line segments each having a different slope and extending from a different lower value of voltage to a difierent higher value of voltage comprising: register means for storing the digits of each of said code groups; zone decoder means coupled to said register means and operated responsive to the x most significant weight digits of a stored code group to produce zone control signals indicating the segments of said characteristic represented by said stored code group, where x is an integer less than n; pedestal signal generator means coupled to said register means and said zone decoder means for providing first control signals indicating the lower value of the voltage of the segments; complementary signal generator means coupled to said register means and said zone decoder means operated responsive to at least the m least significant weight digits of said stored code group to produce a second control signal indicating the position along said segment indicated by said first control signal, where m is an integer less than n; and weighting circuit means coupled to said pedestal signal generator means and said complementary signal generator means operated responsive to said first control signals to produce a first voltage equal to said lower value of voltage of said segment indicated by said first control signal, operated responsive to said second control signals to produce a second voltage corresponding to said position indicated by said second control signal, and operated to sum said first and second voltages to produce an output analog voltage represented by said stored digital code group.

2. A decoder according to claim 1 wherein said register means includes n bistable devices each storing a digit of said stored code group and having a 1 output and a 0 output; said zone decoder means coupled to both said 1 output and said 0 output of said bistable devices storing said x most significant weight digits of said stored code group; said pedestal signal generator means coupled to said 1 output of said bistable devices storing said x most significant weight digits of said stored code group; and said complementary generator means coupled to said 1 output of said bistable devices storing said In least significant weight digits of said stored code group.

3. A decoder according to claim 2 wherein said weighting circuit means includes a plurality of current generators, a weighting and summing means having a plurality of current injection points, each of said current injection points coupled to appropriate ones of said current generators, and logic circuit means coupled to control said current generators responsive to said first and second control signals to activate appropriate ones of said current generators to produce said output voltage at the output of said weighting and summing means.

4. A decoder according to claim 3, wherein said weighting and summing means includes a ladder attenuator.

5. A decoder according to claim 1, wherein said weighting circuit means includes a plurality of current generators, a weighting and summing means having a plurality of current injection points each coupled to appropriate ones of said current generators, and logic means coupled to operate said current generators, responsive to said first and second control signals to activate appropriate ones of said current generators to produce said output voltage at the output of said weighting and summing means.

6. A decoder according to claim 7, wherein said weighting and summing means includes a ladder attenuator.

7. A decoder according to claim 1, wherein n equals seven;

x equals four; and

m equals four.

References Cited UNITED STATES PATENTS 3,290,671 12/1966 Lamoreux 340-347 3,298,017 1/1967 Avignon et a1 340-347 3,305,855 2/1967 Kaneko 340-347 3,305,857 2/1967 Barber 340-347 3,345,505 10/1967 Schmid 340-347 MAYNARD R. WILBUR, Primary Examiner I. GLASSMAN, Primary Examiner