GB2077002A - Electronic timepiece comprising a control circuit of the motor - Google Patents

Abstract

An electronic timepiece comprises a stepping motor having a winding 50, a discriminator 101 for analysing at a determined instant of time during the motor driving pulse the voltage drop across power transistors 10 or 13 controlling flow of drive current in the motor. The voltage drop is transmitted through transmission gates 16 or 15 to a capacitor 17 at the input of the discriminator. The capacitor memorizes this input voltage and the discriminator delivers an output signal according to the comparison of the value of the input voltage with its release threshold. Transistors 22, 23 controlled by control means are connected in parallel with the power transistors for adjusting the release threshold of the discriminator in such manner that the discriminator interrupts the driving pulse when the value C' Fig. 2 of the driving current is reached indicating that the rotor will achieve its step. <IMAGE>

Description

SPECIFICATION Electronic timepiece comprising a control circuit of the motor BACKGROUND OF THE INVENTION The present invention relates to an electronic timepiece with a stepping motor and a control circuit for delivering driving pulses to the coil of the motor.

In timepieces comprising a stepping motor it is desirable to be able to supervise the passage of the rotor during the driving pulse either for interrupting the driving pulse when the passage of the rotor is ensured or in order to check other important parameters related to the working of the motor. Known systems achieve this supervision by analysing the current in the motor coil during the driving pulse. Such analysis systems are not well adapted either to the characteristics of the motor or to be produced by the tehnologies of the integrated circuits. In order to detect a determined point of the characteristic of the current in the coil of the motor during the driving pulse, known systems utilize a detector of the level of the current with a fixed release threshold.

Such a method is particularly critical because of the considerable dispersions which occur during the manufacturing of the driving coil and also during the one of the integrated elements of which the detector is comprised. Moreover, these integrated elements are very sensitive to the temperature so that working disturbances are likely to arise.

One object of the present invention is to realize a timepiece with a stepping motor and a control circuit analysing the current in the driving coil and controlling the motor, which is exempt of the above mentioned drawbacks, that is presenting a great reliability of service and permitting an easy integration of its constituents.

SUMMARY OF THE INVENTION According to the present invention there is provided an electronic timepiece with a stepping motor having a coil and a control circuit for delivering a driving pulse to said coil, said control circuit comprising means responsive to the current level in said coil for providing an output signal when said current level becomes higher than an adjustable threshold, means responsive to said current level for adjusting said release threshold and responsive to said current level at a given instant of time during said driving pulse, and means responsive to said output signal for controlling the duration of said driving pulse.

BRIEF DESCRIPTION OF THE DRAWINGS The invention will be described further, by way of examples, with reference to the accompanying drawings in which: Figures 1 and 2 illustrate the characteristic of the current in the coil of the motor during the driving pulse in the case of small and heavy load of the motor respectively, Figure 3 is a block diagram of a circuit according to one embodiment of the invention, comprising a memory capacitor, and Figure 4 is a block diagram of another circuit according to another embodiment of the invention, comprising logic memorization means.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Fig. 1 shows the characteristic of the current of the coil of a stepping motor during the driving pulse when the motor is slightly loaded. At the beginning, the current increases exponentially in accordance with the time constant L/R of the coil of the motor, where L and R are the inductance and the resistance of the coil respectively. Then, going toward the inflection point A, the current increases more slowly under the influence of the counterelectromotive voltage induced in the coil by the motion of the rotor. When the rotor has effected the greater part of its step, the counterelectromotive voltage decreases which results in a further increase of the current (beginning at point B) which at that time tends rapidly toward its maximum value.The driving pulse may be safely interrupted at point C corresponding to the time at which the current reaches again the value corresponding to the one at point A, or even better at point C' corrresponding to the time at which the value of the current is 1.5 times the level at point A.

Due to the strong slope in this section of the characteristic of the current, the points C and C' are very near to each other so that the consumption of the motor is approximately the same in both cases. Fig. 2 shows the characteristic of the current when the motor is heavily loaded. The rotor moves much more slowly than in the precedent case so that the counterelectromotive voltage has a small amplitude. The points A and B are less accentuated and the point C does not correspond with certainty to the time at which the rotor has effected most of its step but actually to an intermediate, non well determined state in which the rotor may as well terminate its step or move back to its initial starting position. Therefore, it would not be advisable to interrupt the driving pulse at that time.On the other hand, the point C' corresponding to the time at which the current reaches 1.5 times its value at point A is in a zone in which it is possible to interrupt safely the driving pulse.

For detecting this point C' with- a certain accuracy one uses a detector sensing the level of the current in the coil of the motor. Figs. 3 and 4 illustrate two embodiments of circuits for detecting the level of the current, both having an adjustable release threshold according to the invention.

In Fig. 3, a quartz oscillator 1 applies a signal having an accurate frequency, e.g. 32768 Hz, to the input "a" of a frequency divider 2 delivering signals of frequencies .5 Hz at its output "b", 1 Hz at its output "c", 256 Hz at its output "d", 2 kHz at its output "e" and 32 Hz at its qutput ''f''. The output "c" (1 Hz) of the frequency divider 2 is connected to the clock input "a" of a D-type flip-flop FF3 having its reset input "b" connected to the output "d" (256 Hz) of the divider 2 and its programming input "c" connected to the positive pole ( + ) of an electronic power supply not shown in the drawing. The direct output "d" of FF3 is connected to the set input "a" of a RS-NOR gates flipflop FF4 whose output "b" is connected to the set input "a" of a second RS-NOR gates flip-flop FF5.The reset input "c" of FF4 is connected to the output "e" (2 kHz) of the divider 2 and the reset input "c" of FF5 is connected to the output "a" of an OR gate 6 whose input "b" is connected to the output "f" (32 Hz) of divider 2. . As explained thereafter, the flip-flops FF3, FF4 and FF5 form a circuit 100 for producing the driving pulses of the stepping motor.

For the following of the description it is admitted that the stages of the frequency divider 2 are actuated on the negative going edge of their clock pulses and that the flip-flops and the qounters are actuated on the positive going -edge of the clock pulses. Moreover, it is known that in the RS-NOR gates flip-flops the set input has priority upon the reset input. Each second, the signal of frequency 1 Hz at the output "c" of the divider 2 actuates FF3 whose output switches over from the logic state "0" to the logic state "1", which produces the successive switching over to the state "1" in the first time of FF4 and then of FF5. The set input having priority, FF4 cannot switch back to the state "0" as long as FF3 has not switched back to the state "0" and the FF5 cannot switch back to the state "0" as long as FF4 has not switched back to the state "O".

After a half period of the signal 256 Hz, that is 2 ms after the beginning of the signal 1 Hz, the output "d" (256 Hz) of the divider 2 changes to "1" which resets FF3. FF3 being again at "0", FF4 may switch back to "O" at the next half period of the signal 2 kHz at the output "e" of divider 2, that is after .25 ms. Finally, FF4 being again in the state "0", FF5 may in its turn switch back to "0". If there is no signal at the input "c" of gate 6, the reset of FF5 is determined half a period later by the output "f" (32 Hz) of divider 2, that is 1 6 ms after the appearance of the signal 1 Hz at the clock input "a" of FF3.In this way, the flip-flops FF3, FF4 and FF5 change each second one after the other first to the state "1" and then to the state "0", that is FF3 2 ms, FF4 2.25 ms and FF5 no later than 1 6 ms after the appearance of the signal 1 Hz at the input "a" of FF3.

The signal delivered by the output "b" of FF5 controls the stepping motor. In the described example this motor is of the bipolar type, receiving pulses of alternate polarity. This is achieved by connecting the output "b" of FF5 to the inputs "a" of two NAND gates 7- and 8. The input b" of gate 7 is connected to the output "b" (.5 Hz) of divider 2 as well as to the input of inverter 9 whose output is connected to the input "b" of gate 8. The gates 7 and 8 are therefore alternately conducting and negative or zero level control pulses appear alternately at their outputs. The output "c" of gate 7 is connected to a power inverter comprising MOS transistors 9 and 10 as well as to the input "a" of an AND gate 11.The output "c" of gate 8 is connected to a second power inverter comprising MOS transistors 1 2 and 1 3 as well as to the input "a" of an AND gate 14.

The coil 50 of the motor is connected between the respective butputs of these inverters, that is between the drains of transistors 9 and 10 on the one hand and the ones of transistors 1 2 and 1 3 on the other hand according to a well known configuration. When a negative pulse appear at Output "c" of gate 7, the current flows from the positive to the negative pole of the electric power supply through transistor 9, driving coil 50 and transistor 1 3. The transistor 1 3 has a low but non negligible internal resistance so that a voltage appears at its drain which is proportional to the current in the driving coil.This voltage is delivered through a transmission gate 1 5 whose control input "a" is connected to output "b" of divider 2 and to input "b" of the AND gate 7 and further through a capacitor 17 at input "a" of an amplifier 18.

When a negative pulse appears at output "c" of gate 8, the current flows through the transistor 12, the driving coil 50 and the transistor 1 0. A voltage drop proportional to the current in the coil appears then across transistor 1 0.

This voltage is in its turn applied to the input "a" of amplifier 18 through the capacitor 17 and a second transmission gate 16 whose control input "a" is connected to the output of inverter 9 and to input "b" of the AND gate 8. In this way, there is a voltage of constant polarity at the input of amplifier 1 8 which is representative of the current in the driving coil 50.

The amplifier 1 8 is formed in a manner well known in the art by a single pair of complementary MOS transistors. The output "b" of this amplifier is connected to the input of a second amplifier inverter 1 9 matched with amplifier 1 8 and whose output is connected to the input "c" of gate 6. The output "b" of amplifier 1 8 is connected to its input "a" through a transmission gate 20 whose control input "a" is connected to the output "d" of FF3. The output "d" of FF3 is also connected to the input of an inverter 21 whose output is connected to the inputs "b" of the AND gates 11 and 14. The outputs "c" of these gates are connected to the gates of the transistors 22 and 23 respectively which are connected in parallel with the transistors 10 and 13 respectively.

The elements 17, 18, 19 and 20 form a discriminator circuit 101 comparing the level of the current in the coil 50 with an adjustable release threshold and delivering at its output 101a a logical level "1 " whenever this current becomes greater than said threshold. Circuit 101 comprises means for memorizing the value 12ms of the current in the coil 50 at a predetermined time, e.g. 2 milliseconds, after the beginning of each driving pulse produced by circuit 100, and for setting the release threshold value of circuit 101 at the level Ril2mst Ri being the internal resistance of either power transistors 10 or 1 3. The input voltage Ue at terminal "a" of capacitor 17 is proportional to this current according to the relation:: Ue = Ril Ue = input voltage = = current in the coil 50 If Va = input voltage of amplifier 1 8, Va 1 = input voltage of amplifier 18 for which the output voltage Us is equal to Va, p = gain of the amplifier, and Vc = voltage across capacitor 17, the voltage Us at the output of amplifier 19 is given by: Us = (Va-V'a1)+V'a1,whern Va = Vc + Ue, so that Us = (Vc+Ue-Va1)P+Va1 If ss is very high, the second term may be neglected and the threshold of the detector is given by: Ud = Val - Vc, where Ud = release voltage At the beginning of a driving pulse, FF3 is at "1", the outputs of the AND gates 11 and 14 are at "0" and the transistors 22 and 23 are blocked.On the other hand, the transmission gate 20 is conducting which short-circuits the amplifier 18 and fix the value of the input voltage Va to Va1, independently of the value of Ue. The voltage across capacitor 17 is given by: Vc = Val - Ue, or Vc = Val - Ril When, after 2 ms, FF3 switches back to "0", gate 20 changes its state and the charging circuit 18, 20 of capacitor 17 in interrupted.The capacitor 17 cannot charge or discharge so that the voltage between its terminals remains constant: Vc = Val - Bil2, 12,P5 = value of the current after 2 ms Introducing this value of Vc in the previous relation for Ud: Ud = Va - Vc = Va 1 + R i 1 2ms Ud = Ril2ms At the time a . which FF3 switches back to "0", the inputs "b" of the AND gates 11 and 14 change to "1" and one of the transistors 22 or 23 becomes conducting which changes the input voltage of the discriminator 101. This input voltage is then given by: Ue = aRil,wherea1 By making an adequate choice of the geometrics of the transistors 10 and 1 3 on the one hand and 22 and 23 on the other hand, the coefficien a may be established with a certain accuracy.

Let us examine now to which current correspond; the release threshold: Ud = a riled = Ril2ms, so that: 12ms Id = ~~~~~ a The preceding shows that the release threshold with respect to the current, here: Id, may be adjusted as a function of the.value of current in tne coil 50 at a predetermined instant of time, here: 12my, and that it is also possible to fix the desired ratio between these two parameters.

Considering again Figs. 1 and 2, it is to be seen that if a is choosen equal to 2/3, the threshold will be approximately fixed at 1 5 times 1A (in Fig. 2, the current 12ms is approximately equal to the current IA) which guarantees the best security as explained previously. It is clear that the value of time (2ms) which has been choosen in this example may be changed in order to be adapted to any type of stepping motor.

FF3 having switched back to "0" after 2 ms, then FF4 after 2.25 ms, FF5 may switch back to "O" as soon as the output of the amplifier 1 9 changes back to "1", that is at the time at which the current in the coil 50 increases over the threshold value Id in the-neighbourhood of points C' of the Figs. 1 and 2. When FF5 has switched back to "0", the driving pulse is interrupted. It is to be seen that the duration of the driving pulses is automatically adapted.to the time required for the passage of the rotor, time which precisely determines the points C'.

In the example of Fig. 3 the capacitor 1 7 and the transistors 22 and 23 are utilized for fixing and adjusting the release threshold of the discriminator 101. The capacitor 1 7 permits to memorize the level of the current in the coil 50 at a predetermined time after the beginning of the driving pulse so that it can be integrated without any difficulties. The transistors 22 and 23 are connected in parallel with the transistors 10 and 1 3 in the feeding circuit of the driving coil 50.

The conductance of these parameters 22 and 23 is in a known ratio with respect to the one of the transistors 10 and 1 3 respectively. Hence, the switching on of these transistors 22 and 23 permits to vary in the same known ratio the input voltage of the discriminator and consequently to fix the release threshold in relation with the previously memorized level of the current at a determined instant of time of the driving pulse.

It is also possible to fix the threshold by means of a resistive network which delivers a voltage or a current of reference. However, it is difficult to integrate accurate resistive elements. This difficulty may be avoided by placing at the outside of the integrated circuit a resistance'which is choosen in function of the characteristics of the motor and the ones of the feeding circuit of the driving coil.

Another solution presented in relation with Fig. 4 makes use of a self adjustable resistive network.

Fig. 4 shows again the ctscillator 1 of Fig. 3 as well as the frequency divider 2 and a circuit 102 for producing the drii ing pulses of the motor, this circuit comprising the D-type flip-flop FF3 which switches over to "1" '' during 2 ms during each driving pulse having a repetition frequency of 1 Hz in the described example. The circuit 102 comprises five further D-type flipflops FF24, FF27, FF30, FF33 and FF36.

The output "d" of F3 is connected to the set input "a" of the flip-flop FF24, to the reset input "a" of a D-type flip-flop FF25 and to the input "a" of an OR gate 26. The direct output "b" of FF24 is connected to the set input "a" of the flip-flop FF27, to the reset input "a" of a D-type flip-flop FF28 and to the input "a" of an OR gate 29. The direct output "b" of FF27 is connected tQ the set input 'a" of the flip-flop FF30, to the reset input "a" of a D-type flip-flop 31 and to the input "a" of an OR gate 32.The direct output "b" of FF30 is connected to the set input "a" of the flip-floF FF33, to the reset input "a" of a D-type flip-flop FF34 and to an input "a" of an OR gate 35 The direct output "b" of FF33 is connected to the set input "a" of the flip-flop FF36 whose direct output "b" is connected to inputs "a" of AND gates 37 and 38 and whose reset input "c" is connected to the output of an OR gate 39 of which an input "a" is connected to the output "f" of the divider 2 (32 Hz), and an input "b" to the inputs "d" of the FF25, FF28, FF31 and FF34. The clock inputs "c" of the FF24, FF27, FF30 and FF33 are connected to the output "a" (frequency 32768 Hz, period 30 ss) of the oscillator 1 while the inputs "d" of FF24, FF27, FF30 FF33 and FF36 are connected to the negative pole of the power supply.

The flip-flop FF25, FF28, FF31 and FF3'- constitute a part of a level discriminator circuit 103, as explained thereafter.

The direct outputs "b" of FF25, FF28, FF31 and FF34 are connected respectively to inputs "b" of the OR gates 26, 29, 32 and 35 while the clock inputs "c" of FF25, FF28, FF31 and FF34 are connected respectively to the inverted outputs "e" of FF24, FF27, FF30 and FF33.

A second input "b" of AND gate 37 is connected to the output "b" (.5 Hz) of divider 2 as well as to the control, input of a transmission gate 40 and to the input of an inverter 42. The output of this inverter 42 is connected to an input "b" of an AND gate 38 and to the control input of a transmission gate 41. The outputs of AND gates 37 and 38 are connected each to a terminal of the driving coil 50 and to the input of one of the gates 40 and 41 whose outputs are connected together to the input of the level discriminator circuit 103.

Each second, FF3 switches over to "1" which produces the switching over to "1" of FF24, FF27, FF30, FF33 and FF36 and the reset of FF25, FF28,-FF31 and FF34. Hence, the outputs of the OR gates 26, 29, 32 and 35 are at state "1". The inputs "a" of the AND gates 37 and 38 are at "1" and, depending on the state at the output "b" of divider 2, the output of one of the AND gates 37 ad 38 changes to "1" while the other remains at "O".

Hence, the driving coil 50 is fed in the direction corresponding to the state of output "b" of the divider 2 and the corresponding transmission gate (40 or 41) transmits to the input of the level discriminator 103 a voltage which is proportional to the current in the driving coil 50, this voltage resulting from the voltage drop due to the circulation of the current of the motor in the internal resistance of the gates 37 and 38 comprising power transistors for feeding the coil.

2 ms after the beginning of the driving pulse, FF3 switches back to "0" and the FF24, FF27, FF30, FF33 and FF36 switch back successively to "0", each one every 30 lis, under the control of the clock pulses. Hence, after an interval of time of 1 25 ms, FF33 switches back to "0" and FF36 is ready to switch back in its turn to "O" This will occur no later than 1 6 ms after the beginning of the. driving pulse (1 /2 period of the signal at output "f" of divider 2).

The reset of FF36 sets to "0" the inputs a of the AND gates 37 and 38 which interrupts the driving pulse. Hence, the driving pulses have, as in the circuit of Fig. 3, a maximum duration of 1 6 ms but they may be interrupted sooner by an adequate signal at the output of the level discriminator circuit 103 delivered to the input "b" of the OR gate 39 which transmits it to the reset input "c" of FF36.

The level discriminator circuit 103 is arranged in accordance with the following.

The input voltage is delivered to the source "a" of a N-type MOS transistor N1 the drain of which is connected to the drain of a P-type MOS transistor P1 the source of which being connected to the positive pole of the power supply. The transistors N1 and P1 form an amplifier inverter with complementary MOS transistors whose output is connected to the input of an amplifier inverter 43 which is followed by an amplifier inverter 44 whose output is connected to the input "b" of the OR gate 39 and to the inputs "d" of FF25, FF28, FF31 and FF34. The amplifiers 43 and 44 are similar to the amplifier comprising the transistors N1 and P1 and their transistors are matched. The gates of the transistors N1 and P1 are connected to a common point A of a resistive network, whose resistance is constituted by drain-sources path of MOS transistors as explained hereunder.

To the point A are connected the gates and the drains of the N-type MOS transistors N 1 ' and N0.5 as well as the ones of P-type MOS transistors P1', P2, P4 and P8 the sources of which being connected to the outputs of the OR gates 35, 32, 29 and 26 respectively. The source of transistor N 1 ' is connected to the negative pole of the power supply while the source of transistors N0.5 is connected to the inverted output "e" of FF33.

It is well known that the drain-source conductance of a MOS transistor depends on its gatesource and drain-source voltages and on its geometry. By suitably combining the geometries of transistors one can realize transistors having conductances in determined ratios among themselves. In Fig. 4, the conductances of the transistors P8, P4 and P2 are respectively 8 times, 4 times and 2 times greater than the ones of the transistors P1 and P1'. Similarly, the conductance of transistors NO. 5 is 2 times smaller than the one of transistors N1 and N 1 '.

These N and P transistors form a resistive network permitting to adjust and fix the release threshold of the level discriminator approximately to zero because the transistors P1', P2, P4 and P8 may be blocked by a state "0" delivered to their sources and the transistor NO. 5 by a state "1" on its source.

Let us assume for example that only the transistors P1' and N1'are conducting. These transistors form a pair which is identical to the pair of transistors N1, P1. The voltage on their gates corresponds to a release threshold "0" on the input "a" of N1: N1a = N1'a = 0 If transistor P2 is rendered conducting instead of transistor P1' the current in N1' will increase due to the fact that the conductance of P2 is greater that the one of P1'. The voltage on the gates of the transistors will accept a slightly higher value resulting in a corresponding increase of the release threshold. If the four transistors P1' to P8 are rendered conducting the cònductance is increased by 1 5 times and the voltage on the gates is increased in the same proportion.Thus, by utilizing X transistors it is possible to obtain 2x steps of voltage. In the described example with four transistors, there are 1 6 steps of voltage. The maximum threshold voltage corresponding to 2x steps must obviously be greater than the desired threshold voltage.

This condition being fulfilled, it is possible by an adequate search system to search the desired binary combination corresponding to the desired threshold value.

It has been seen previously that when FF3 switches over to "1" the outputs of the gates 26, 29, 32 and 35 change to "1" while the inverted output "e" of FF3 is at "0". Hence, the transistors P1', P2, P4, P8 and NO.5 are conducting. The voltage on the gates of these transistors and consequently the release voltage is at its maximum value. Therefore, the output of the pair N1, P1 is at "O" as well as the output of the amplifier 44. After 2 ms the output of FF3 changes back to "0" as well as the output of the OR gate 26, FF25 being still at "0".

The transistor P8 becomes non-conducting and the voltage of the gates is reduced of eight steps as well as the release voltage. If this voltage falls below the input voltage, the output of amplifier 44 changes its state from "0" to "1". After 30 ps the FF25 receives a clock pulse and memorize the state at the output of amplifier 44 at this time. Thus, when the transistor P8 is rendered non conducting, the threshold falls below the value of the input voltage, the conduction of this same transistor being reestablished a short instant of time later which determines again a threshold having a value greater than the input voltage.

This action of successive approximations is repeated every 30 lis for rendering the transistors P4, then P2 and P1 non conducting and by reestablishing if required the conduction of these transistors.

Let us assume for example that after 2 ms the input voltage of the amplifier is fixed at 10 steps of voltage, this voltage being proportional to the current in the driving coil.

At the beginning the 4 transistors P8, P4, P2 and P1' are all conducting so that the threshold is fixed at 1 5 steps of voltage (8 + 4 + 2 + 1). By rendering P8 non conducting the threshold changes to 7 steps of voltage (4 + 2 + 1). This threshold is obviously too low (7 < 1 0) so that the output of the amplifier 44 changes to "1" as well as FF25 which determines again the conduction of P8 and reestablish the threshold at 1 5 steps. Then P4 is rendered non conducting. The threshold change to 11 steps (1 5 - 4). This threshold is obviously too high (11 > 10). The output of amplifier 44 remains at "O" as well as FF28. The threshold remains at 11 steps.

Then P2 is rendered non conducting. The threshold changes to 9 steps of voltage (11 - 2).

This threshold is too low (9 < 1 0) so that the output of amplifier 44 changes to "1" '' as well as FF31, which reestablish the conduction of P2 and brings back the threshold to 11 steps. Then P1 is rendered non conducting. The threshold changes to 10 steps (11 - 1). If it is assumed that the output of amplifier 44 remains at "O" as well as the one of FF34, the value of the threshold is then fixed and memorized by FF34, FF31, FF28 and FF25 which are respectively in the states "0", "1", "0" ''O'' and "1" '' corresponding to 10 steps of voltage, the transistors P8 and P2 only being conducting. The search operation of the threshold voltage takes place between 2 ms and 2.125 ms after the appearance of the signal 1 Hz at FF3.During this short laps of time the voltage at the input of the discriminator has practically not changed so that the value of the current in the driving coil at a determined instant of time of the driving pulse is really memorized. After this time of 2.1 25 ms the inverted output' 'e" of FF33 changes to ''1 "1" so that the transistor N0.5 becomes non conducting. In consequence, the current delivered by the transistors P8 and P2 must pass in totality through transistor N 1 ' which produces in this transistor an additional voltage drop. The voltage on the gates of the transistors increases which increase the release threshold of the discriminator.

It is seen that, as in the case of Fig. 3, a threshold corresponding to the current in the driving coil at a determined instant of time is memorized and then this threshold is varied in known proportions by controlling transistors having values of conductances suitably choosen. However, in the case of Fig. 4, one acts directly on the threshold of the discriminator while in the case of Fig. 3 the action took place indirectly in that the input voltage of the discriminator was changed by modifying the internal resistance of the feeding circuit of the driving coil. Both embodiments are possible and they lead to the same result.

The two above described circuits realize a discriminator of the level of the current in the driving coil with an adjustable threshold according to the present invention. This type of circuit permits to analyse the shape of the current in the coil during the driving pulse with a maximum of efficiency. It is visible that after -2.125 ms the output of the amplifier 44 is at "0". This output changes to "1" as soon as the input voltage increases above the fixed threshold. At this time, FF36 switch back to "0" and interrupts the driving pulse. It is to be noted that in the case of Fig. 4 the release threshold may also be adjusted, after memorization of the value of the current at a determined time, by modifying with logic means the outputs of the OR gates 26, 29, 32 and 35 controlling the conduction of the transistors P8, P4, P2 and P1' respectively.

Thus, by inserting an additioner between the inputs of these OR gates and the direct outputs "b" of FF25, FF28, FF31 and FF34 it is possible to increase the release threshold by a given number of steps. By inserting a multiplier in the same place it is possible to multiply the value of the threshold by a known factor.

In the above described cases the output of the level discriminator is utilized directly for interrupting the driving pulses but this is in no way an absolute necessary condition. It is also possible to utilize more sophisticated analysing means of the signal delivered by the discrimina tor which act only indirectly on the duration of the driving pulse or even permitting, for reason of security only, to check parameters related to the operation of the motor and to act on the duration of the driving pulse only if necessary.

Finally it should be noted that the determined time at which the release threshold is fixed must not necessarily be fixed in the time. While in the described example a fixed time (2 ms) after the beginning of the driving pulse has been choosen, it is also possible to choose any other instant of the time corresponding for example to a determined point of the characteristic of the current, like the inflection point A or the point B where the current starts again to increase.

These points A and B may move with respect to the begining of the driving pulse due either to variations of the load of the motor or of the supply voltage. These points A and B occur at the time at which the derivative of the current goes through 0 and they may be detected in this way.

Claims (11)

1. Electronic timepiece with a stepping motor having a coil and a control circuit delivering a driving pulse to said coil, said control circuit comprising means responsive to the current level in said coil for providing an output signal when said current level becomes higher than an adjustable threshold, means responsive to said current level for adjusting said release threshold and responsive to said current level at a given instant of time during said driving pulse, and means responsive to said output signal for controlling the duration of said driving pulse.

2. Timepiece according to claim 1, wherein said adjusting means comprise means for memorizing the current level at said given instant of time.

3. Timepiece according to claim 2, wherein said memorizing means comprise logic memori zation means.

4. Timepiece according to claim 2, wherein said memorising means comprise at least one memory capacitor.

5. Timepiece according to claim 1, wherein said adjustment means comprise at least a plurality of semiconductor elements having such geometries that their conductances are in predetermined ratios.

6. Timepiece according to claim 5, wherein the conductances of said semiconductor elements are in geometrical progression among themselves.

7. Timepiece according to claim 5, further comprising logic memorization means, said semiconductor elements being at least indirectly connected to said logic memorization means.

8. Timepiece according to claim 5, wherein said semiconductor elements are included in a resistive network for determining a voltage of reference.

9. Timepiece according to claim 8, wherein said resistive network determines a current of reference.

1 0. Timepiece according to claim 1, wherein said controlling means are means responsive to the output signal of said means responsive to the current level for interrupting said driving pulse.

11. Electronic timepiece substantially as hereinbefore described with reference to and as illustrated in the accompanying drawings.