GB2073525A - Divide by two charge divider - Google Patents

Description

1

SPECIFICATION

Divide-by-two charge divider A 10 GB 2 073 525 A 1 The invention relatesto a device forthe division of 70 an electric charge into equal halves, for us in analog-to-digital or digital-to-analogue converters, employing clock pulse controlled charge transfer devices.

The IEEE J1. SSC of December 1975, page 371 etal and December 1976, page 722 etal, described devices for analog-to-digital (ADC) and digitaltoanalog (DAC) conversion, in which it is attempted to repeatedly divide a charge into halves by means of a series of capacitors with binary weighted values. This presents problems in accurately realising the correct capacitance values, which is decisive forthe accuracy with which the relevant charge devision is effected.

The invention is characterised in that said electric charge is distributed between two parallel branches, which branches each comprise a charge transfer device and a storage capacitance, which capaci tances can each acquire half the said electric charge by means of the related charge transfer device with an inaccuracy which is determined by the inequality of the charge transfer devices, each of the storage capacitances being coupled to a respective two further alternately operative charge transfer devices, of which one further device transfers the charge 95 stored in the storage capacitance of one of said branches to a collecting capacitance situated in the same branch, whilstthe other one of the further charge transfer devices transfers said charge to a collecting capacitance situated in the other branch. 100 The invention is based on the conceptthat for converting a digital signal into an analog signal with the aid of a charge transfer device (M), such as a bucket brigade device (BBD) or a charge coupled device (CCD), it is simply possible to distribute charges among parallel branches with for example equal capacitors (known perse frorll IBM Techn.

Disci. Bull., January 1976, page 2540) and to obtain a series of binary weighted charges according to this principle. The charges of this series, of which the bit 110 corresponding weight of the digital input signal is for I % are added so that an overall charge is obtained which is the analog equivalent of the digital signal.

For the conversion of analog signals into digital - signals the output of a DAC as described in the fore- 115 going may be compared with the analog input signal and from the difference of the two the digital control of the charge transfer devices may be derived, which then yields the digital signal.

A major advantage of the use of parallel branches 120 in comparison with the prior art known from the aforementioned articles in WEE J]. SSC., is that now if desired, capacitors with equal or nearly equal capacitance values may be used, so that the number of bits of the DAC or ADC, in comparison with the said known devices, could be extended substantially. However, the conversion accuracy then also remains dependent on the accuracy with which the charge transfer devices in the two parallel branches are identical to each other. However, said inequality 130 has no consequences owing to the use of the aforementioned further charge transfer devices, as will become apparent hereinafter.

The invention will now be described in more detail by way of example with reference to the accompanying drawings, in which:- Figure 1 shows a device which illustrates the principle of the invention; Figure 2 represents voltage-time diagrams of the clock pulses employed in Figure 1 and, Figure 3 illustrates the combination of devices in accordance with Figure 1 to form a digital-to-analog converter.

In the device of Figure 1 a source of constant vol- tage Vo charges a capacitor C,, via a transistor 1 which is controlled by a clock pulse 0, and which is specifically an insulated gate field-effect transistor (IGFET), so that a given reference charge Q is stored in the capacitor Co. By means of a charge transfer device, in this case a transfer gate, comprising a transistor 2 controlled by a clock pulse 02, most of this charge Q is transferred to a storage capacitance C1, from which it is applied to two parallel branches A and B, respectively, each comprising an isolating transistor 3a and 3b, respectively, operated in cascode, a transfer gate, comprising a transistor 4a and 4b, respectively, and a storage capacitance C2a and C21J, respectively. The transistors 4a and 4b are also controlled by the clock pulse 0, If the transistors 3a and 3b and 4a and 4b had exactly the same properties, specifically the same threshold voltages and channel resistances (the capacitances C2a and C2b need not be exactly equal), then atthe instant at which by means of the clock pulse 01 the charge Q on the capacitance C1 is transferred to the capacitances C2a and C2b, via the transistors 4a and 4b, respectively, each of the last-mentioned capacitances would acquire exactlythe charge!Q. However, in practice this requirement cannot be met, especially not by means of an integrated circuit version, where it is alrady difficult to obtain mutual property differences below 1%.

Via isolating transistors 5a and 5b, respectively, which are operated in cascode, the capacitances C2a and C2b, in accordance with the further characteristic feature of the invention, are followed by a respective two transfer gates comprising transistors 6a and 7a and 6b and 7b, respectively, and collecting capacitances Ma and C3b, respectively. Clock pulses 03 an ' d 04 applied to these transfer gates, and the clock pulse 0, which is simultaneously applied to the lower side of the capacitances Ma and C3b, respectively, ensure that either the transfer gates 6a and 6b or the transfer gates 7a and 7b are operative. (Thus, in contradistinction to the said article in IBM-TDB no direct connection is established between the upper sides of the capacitances C2a and C2b). As a result of this, the charges on the capacitances C2a and C2b are transferred to the collecting capacitances C3a and C3b, respectively, during the clock pulse phase 03 and to the collecting capacitances C3b and C3a, respectively, during the clock pulse phase 0,. If the first-mentioned charges are 1Q(1 +x) and WO -x) respectively, in which x represents the charge deviation as a result of the inequality of the transfer and 2 isolating transistors specifically of the transistors 3a and 4a, respectively, and 3b and 4b, respectively, each of the collecting capacitances C3a and C3b will alternately receive the charges -2'Q(l +x) and 1Q0 -x).

The capacitance C3a, via an isolating transistor 8a operated in cascode, is connected to a transfer gate comprising a transistor 9a connected to a storage capacitance C4a, which is also controlled by the clock pulses 0, Thus, the sum of the two above mentioned charges, i.e. a charge Q, will be transfer- 75 red to the capacitance C4a.

Thus, the steps described so far apparently seem to have no effect, because from the reference charge Q on the capacitance C, an equal charge on the capacitance C4a has been derived. However, from the following itwill appearthat actually some prog ress is made. The capacitance C3b, in its turn, is fol lowed by two parallel branches B'and C which are identical to the branches A and B, i.e. the capacitance C31J is connected to transfer gates via isolating trans- 85 istors 8b and 8c, respectively, which correspond to the previously described transistors 3a and 3b, respectively, which transfer gates comprise transis tors 9b and 9c (corresponding to the transistors 4a and 4b, respectively) and are connected to storage capacitances C4b and C4c, respectively (correspond ing to capacitances C2a and C2b, respectively) etc.

This is schematically represented in Figure 3.

In this Figure the block 1, 2 corresponds to the circuit elements 1 and 2 of Figure 1, by means of which the charge Q is derived from the voltage VO.

The branches 4a and 4b, corresponding to the relev anttransfer gates of Figure 1, divide said charge into approximately equal halves jQ, whilstthe branches 6a, 6b, 7a and 7b correspond to the relevant 100 "further" transfer gates of Figure 1. If the errors introduced in the charge division by the gates 3a, 4a, 3b, 4b and 8b, 9b, 8c, 9c, are x, and x2, respectively, a charge -j'Q(1 +xj), say, will arrive atthe capacitance C3b during the clock pulse phase 03 and a charge 10(i -xi) during the clock pulse phase 04. Under the influence of the clock pulse 01 on the transfer gates 9b and 9c, this charge is again divided into approximately equal halves with an error x2, so that during the clock pulse phase 0, a charge 1W +xj -x2) will arrive atthe capacitance C4b, and a charge I 01 +xj +xj atthe capacitance C4c, whilst during the clock pulse phase 04 a charge 1Q(1 -xi -x2) will arrive at the capacitance CO and a charge WO -xi +x?) at the capacitance C4c. The transfer gates 10b, 11b and 10c, 11c, respectively, (corresponding to the tranfer gates 6a, 7a and 6b, 7b, respectively) following said capacitances ensure that during the clock pulse phase 03 the charges then present are further transferred alternately. The result is that the chargesa" 0(1 +x, -xj and,!,Q(l -xi +x?) are collected the capacitance C5b and then transferred to the storage capacitance C6b of the branch B': thus an error free'2Q is obtained (when ignoring second- ordereffects).

-in a similar way the branch C is followed by two further parallel branches (corresponding to the branches B'and C1 etc., by means of which error free charge values 0/4,-0/5, etc., can be obtained. These charges are apoiedto a sunwning device S control- 130 GB 2 073 525 A 2 led by a digital input signal DI, which device S comprises a plurality of electronic two-way switches, each of which depending on the value of the signal DI transfers the relevant charge eitherto the analog output AO orto earth. (in Figure 1 one of these twoway switches is represented bythe transistors 13 and 14, the clock pulse 03 being applied to the transistor 13 or 14 depending on the value of the signal DI).

Where in the foregoing there is mention of capaci tances, itwill be evidentthat forthese capacitances it is possible to utilise internal capacitances of a semiconductor body, such as occur in CCD's, PCCD's, etc.

The use of IGFET's operated in cascode, (2,3a, 3b, 5a, 5b, etc.), i.e. the source electrode used as input (on the left in the Figure), the gate electrode at a fixed potential (earth) and the drain electrode as output (on the right in the Figure), has the advantage of a better charge transfer efficiency: the cascode IGFErs 5a, 5b, etc., preceding the "further" charge transfer devices moreover have the advantage that any errors introduced by, for example, threshold voltage differences of the transistors 6a and 7a, or 6b and 7b, are avoided. The charge transferred from the capacitance C2a to the respective capacitances C3a and Ob by the transfer gates 6a and 7a, respectively then virtually depends only on the threshold voltage of the transistor 5a and is no longer influenced by the efficiency of the transfer gates 6a and 7a, respecitvely. The same applies in respect to the capacitance C2b, transistor 5b and transfer gates 6b and 7b.

Claims (4)

In general, the steps described will be mainly applied to the more significant bits of a digital-toanalog converter, because for the less significant bits, i e. the bits which differ by a great division factor from the charge Q, the said errors are no longer of significance. CLAIMS

1. A device for the division of an electric charge into equal halves, for use in analog-to-digital or digital-to-analog converters, employing clockpulse controlled charge-transfer devices, characterised in that said electric charge is distributed between two parallel branches, which branches each comprise a charge transfer device and a storage capacitance, which capacitances can each acquire half the said electric charge by means of the related charge transfer device with an inaccuracy which is determined by the inequality of the charge transfer devices, each of the storage capacitances being coupled to a respective two further alternately operative charge transfer devices, of which one further device transfers the charge stored in the storage capacitance of one of said branches to a collecting capacitance situated in the same branch, whilstthe other one of the further charge transfer devices transfers said charge to a collecting capacitance situated in the other branch.

2. A device as claimed in Claim 1, characterised in that at least the further charge-transfer devices are preceded by transistors operated in cascode.

3. A device for the division of an electric charge into equal halves substantially as hereinbefore described with reference to Figures 1 and 2 of the accompanying drawings.

i1 1; 1 3 Ik GB 2 073 525 A 3

4. An arrangement for the repeated division of an electeic charge into equal halves for producing binary weighted charges, substantially as hereinbefore described with reference to Figure 3 of the accompanying drawings.

Printed for Her Majesty's Stationery Office by The Tweeddale Press Ltd., Berwick-upon-Tweed, 1981. Published at the Patent Office, 25 Southampton Buildings, London, WC2A 'I AY, from which copies may be obtained,