GB2072983A - Circuit for Generating a Line Deflection Current - Google Patents

Abstract

A line deflection circuit has a first controllable switch T1, D1 and a first inductance L1 connected in parallel with a second controllable switch T2, D2 and a second inductance L2 between a supply terminal +V and ground. A deflection network comprising a line deflection coil (L) and a trace capacitor C is connected between the junctions of the inductances with their switches which conduct during the trace period. Retrace capacitors C1 and C2 are connected in parallel with the respective first and second switches. The peak voltage produced during the retrace period is distributed over both switches and so reduce the stress placed on these switches. <IMAGE>

Description

SPECIFICATION Circuit For Generating A Line Deflection Current The invention relates to a circuit for generating a sawtooth-shaped deflection current having successive trace and retrace periods through a line deflection coil which coil is part of a deflection network one end of which network is operationally coupled to an inductance, said inductance being serially connected with a controllable bidirectional switch which is capable of conduction in both of two directions to form a supply network, one end of the supply network being connected to a point for conveying a d.c.

voltage whilst its other end is directly connected to a point of reference potential, the switch, in operation, being conductive during the said trace periods and non-conductive during the said retrace periods.

Such a circuit for the electromagnetic deflection of one or more electron beam(s) in for example, television display tubes or television camera tubes is generally known. In prior art circuits the deflection network includes a trace capacitor the voltage of which, the trace voltage, is equal in the steady state to the d.c. voltage which is used as the supply voltage for the circuit.

During the trace or scan period of the deflection current the deflection coil is connected to the trace voltage by means of the switch. This results in the sawtooth deflection current which reverses its direction approximately in the middle of the trace period. During the retrace period in which the switch is kept in the non-conductive state, a reasonant circuit is formed with a retrace capacitance, a cosinusoidal oscillation being produced in the ideal case across this resonant circuit; this is the retrace or flyback pulse.

The amplitude of the retrace pulse is equal to the voltage of the power supply source multiplied by a factor which depends on the ratio of the retrace period to the overall period and may therefore be rather high. This is particularly the case for high-resolution picture display tubes which are used to display digitally generated pictures. A relatively high deflection frequency and, consequently, a relatively short deflection period is chosen for the horizontal deflection, which requires a high supply voltage.

Furthermore, the retrace period must be relatively short so that the above-mentioned fact is high.

For these reasons, the retrace pulse has a high amplitude. This imposes high requirements on the switch which consists of, for example, the parallel arrangement of a switching transistor and a diode, the direction in which the diode conducts being the opposite of the direction of conduction of the collector-emitter path of the transistor. The same applies to prior art circuits having a seriesbooster diode, the trace voltage across the deflection coil being higher than the supply voltage.

It is an object of the invention to provide a circuit of the above-mentioned type in which the peak voltage across the switch may be reduced.

while the remaining properties of the circuit may be maintained.

The invention provides a circuit of the type described in the opening paragraph which is characterised in that the other end of the deflection network is operationally coupled to a second inductance, said second inductance being serially connected to a second controllable bidirectional switch which is also capable of conduction in both of two directions to form a second supply circuit one end of the second supply network being connected to a point conveying a second d.c. voltage whilst its other end is. connected to the said point of said reference potential and wherein, in operation, the second switch is also conductive during the said trace periods and non-conductive during the said retrace periods.

With the present circuit the peak voltage produced during the retrace period is distributed over two switches. In addition, it appears that the capacitive radiation of the deflection coil to other portions of the device of which the present circuit form part is considerably reduced.

The circuit according to the invention may be characterized in that the first and the second d.c.

voltages may have the same polarity, a terminal of the first circuit as well as an end of the second inductance being connected to the said point of the reference potential or that the first and the second d.c. voltages may be of opposite polarity when a terminal of the first swtich as well as a terminal of the second switch may be connected to the said point of reference potential.One such case where the deflection network includes retrace capacitance, may be characterised in that the first and the second d.c. voltages may have the same absolute values,, the retrace capacitance consisting of a first retrace capacitor arranged in parallel with either the first switch or the first inductance, and of a second retrace capacitor arranged in parallel with either the second switch or the second inductance the first and the second retrace capacitor each having substantially the same capacitance, or where the first and the second d.c. voltages have unequal absolute values the retrace capacitance may consist of a first retrace capacitor arranged in parallel with either the first switch or the first inductance, and of a second retrace capacitor arranged in parallel with either the second switch or the second inductance, respectively, the ratio between the capacitance of the first retrace capacitor to the capacitance of the second retrace capacitor being substantially equal to the ratio between the value of the second d.c. voltage to the value of the first d.c. voltage.

Advantageously, the circuit may be further characterised by the first and second inductances being at least partially magnetically coupled and may be further characterised by winding coupled to one of the inductances, a rectifier being connected to this winding for deriving a d.c.

voltage therefrom. In order to correct picture display geometry, the circuit may be further characterised by the first and the second d.c.

voltages being of equal value and originating from the same source and containing a component which varies with field frequency.

The invention will now be further explained by way of non-limitative example with reference to the accompanying drawing in which: Figure 1 shows a first embodiment of the circuit according to the invention; Figure 2 shows a waveforms occurring therein, and Figure 3 shows a second embodiment of the circuit according to the invention.

In Figure 1 L, represents an inductance. One end A thereof is connected to the collector of an npn-switching transistor T1 while the other end is connected to the positive terminal of a d.c.

voltage source V. The emitter of transistor T, and the negative terminal of source V are connected to ground. A diode D, is arranged in parallel with the collector-emitter path of transistor T1 with the reverse direction of conduction.

The colllector of an npn-switching transistor T2 is connected to the positive terminal of source V while the emitter thereof is connected to an end B of an inductance L2. The other end of inductance L2 is connected to ground. A diode D2 is arranged in parallel with the collector-emitter path of transistor T2 with the reverse direction of conduction. In known manner diodes D1 and D2, respectively, may be omitted when transistor T, and2, respectively, can conduct in the reverse direction.

The series arrangement of a trace capacitor C and a deflection coil L is included between points A and B, a terminal of capacitor C being connected to point A and an end of coil L being connected to point B. Coil L is, for example, the line deflection coil for the electromagnetic deflection in the horizontal direction of one or more electron beam(s) generated in a picture display tube, not shown. In addition, the circuit of Figure 1 comprises a retrace capacitance which is arranged, for example, in parallel with coil L or the series arrangement L, C. Alternatively, the retrace capacitance may consist of the winding capacitance of coil L or of inductance Lr and L2, respectively, or be arranged in parallel therewith.

In Fig. 1, the retrace capacitance consists of a capacitor C,, which is arranged in parallel with diode Da, and capacitor C2, which is arranged in parallel with diode D2, capacitors C, and C2 having the same capacitance. The deflection coil, the trace and the retrace capacitance form part of a deflection network of a known type, which may comprise other, known elements which for simplicity have not been shown in Fig. 1. A centering circuit and a linearity control are such elements.

in operation, when the steady state has been reached, both switches T,, D, and T2, D2, conduct during the trace period of the deflection current.

As a result thereof voltage V is present across inductance L, as well as across inductance L2. Consequently, there flows through each inductance a sawtooth current i, whose slope di dt in a loss-less circuit and at an infinitely large capacitance for capacitor C is constant and whose mean value is zero. This current reverses its direction at the centre instant of the trace period.

Prior to this instant the current flows through diodes D, and D2, respectively, to source V and after this instant it is supplied by source V and flows through transistors T, and T2, respectively.

To this end the two transistors are previously rendered conductive, namely by control signals applied suitably to their bases.

At the end of the trace period, transistors T, and T2 are cut-off, which introduces the retrace period. In this period of time coil Forms a resonant network with capacitors C, and C2, which were short-circuited during the trace period, and with inductances Lr and L2 and capacitor C. The currents which flow downwards in Fig. 1 through inductances L, and L2 prior to the start of the retrace period, continue to flow in this direction, but now through the resonant network.

The variation thereof is substantialy sinusoidal and is determined by one of the tuning frequencies of the resonant network. The current through inductances L, and L2 and the resonant network reverses its direction at the centre instant of the retrace period and consequently flows upwards, that is to say to source V.

During the trace period point A has substantially ground potential, while point B has substantially the potential of source V. During the retrace period the voltage at point A increases in accordance with a cosine function to above the ground potential, while the voltage at point B decreases to below voltage V in accordance with a similar function. At the centre instant of the retrace period, the first-mentioned voltage reaches a maximum and the second voltage a minimum. At a determined instant the voltage at point A becomes zero again whereafter diode D1 is rendered conductive. This is the end of the retrace period and the start of a new trace period.

At the same instant the voltage at point B becomes substantially equal to V as a result of which D2 becomes conductive. A decreasing current now flows upwards to inductance L, and L2, respectively.

Fig. 2a shows the variation of the voltage at point A as a function of time and Fig. 2B shows the variation of the voltage at point B. Since point A is d.c. connected to source V via inductance L1, the average value of the voltage at this point is equal to voltage V. The amplitude of the cosinusoidal retrace pulse at point A is equal to voltage V multiplied by a factor which depends on the retrace ratio of the retrace period to the overall period.

In a similar manner the average value of the voltage at point B as well as at the junction point of deflection coil L and capacitor C is equal to zero.

The $amplitude of the retrace pulse at point B is equal to the amplitude of the pulse at point A. The capacitance of capacitor C is then assumed to be infinitely large. Capacitor C is charged to voltage V, the terminal connected to point A being positive and the other terminal being negative.

From this it appears that the voltage at the junction point of coil L and capacitor C is equal during the trace period to -V (Fig. 2c) and consequently that the voltage across coil L is equal to 2V in the same period of time. In these circumstances there flows through coil L a sawtooth deflection current I having a constant slope dl 2V dt L whose mean value is zero and which therefore reverses its direction at the centre instant of a trace period. Prior to this instant it flows through diodes D, and D2 and after this instant it flows through transistors T, and T2.

During the retrace period the deflection current first flows through coil L and capacitor C from point B to point A and further through capacitors C, and C2 via source V, the variation being sinusoidal with the tuning frequency of the above-mentioned resonant network. After the centre instant of the retrace period the deflection current flows through the same elements in the opposite direction and at the end of the retrace period it assumes the same absolute value as at the beginning thereof. Fig. 2d shows the variation of current 1.

The foregoing applies to the ideal case where the circuit has no losses and the capacitance of capacitor C is infinitely large. In practice this capacitance is given a finite value, so that the voltage across coil L does not remain constant during the trace period. In this manner S correction is obtained for the deflection current.

Without losses, the same amount of current flows back to source V as is supplied by it, so that the total energy consumption of the circuit is zero. In reality, more current is derived from source V than flows back to it, owing to the losses. Therefore a direct current component is added to the current flowing through inductance L, and L2, respectively. This implies that the total current through inductance L, and L2, respectively, does not reverse direction at the centre instant of the trace period but shortly before that instant and that the absolute value thereof at the beginning of the trace period is lower than at the end of this period.

In the ideal case, in the circuit of Figure 1, the same voltage is present across the trace capacitor as across the trace capacitor in the prior art circuit, namely the voltage supplied by the supply source, and in the retrace period the same peak voltage is present across each switch as across the single switch in the known circuit. In contrast therewith, a trace voltage which is twice as high as the voltage across the trace capacitor is present across the deflectron coil in the circuit of Figure 1, compared with the known circuit, the trace voltage across the deflection coil and consequently also the amplitude of the deflection current therethrough is thus doubled. For the same amplitude of the deflection current it is therefore sufficient to use a supply voltage which is half the previously used when the peak voltage across the switches it is also half the previous value.This is an advantage, particularly for display arrangements having a high-resolution picture display tube for displaying digitally generated pictures when the horizontal deflection frequency may be relatively high, namely of the order of 1 5 to 60 kHz, while the retrace period is short, namely of the order of 3 to 5 ,us, as at higher frequency a shorter dt and consequently a higher V go together in the fornfula dl 2V=L--.

dt In addition, a shorter retrace period implies a higher peak voltage.

A further advantage of the present circuit is the fact that the voltages at the ends of the deflection coil (Figures 2b and 2c) are equal in absolute value but have opposite signs, so that the central point of the deflection coil has ground potential. The capacitive radiation of the coil to other portions of the arrangement of which the described circuit forms part is reduced thereby with respect to the radiation in prior art circuits.

As high-voltage transistors usually have comparatively long turn-off time, advantageous use can be made for transistors T and T2 of gate turn-off switches can be turned off in a much shorter period ot time, in less the 1 ,us.

Alternatively, one transistor or both transistors may be replaced by pnp transistors; for example, transistor T2 may be of the pnp type, the emitter being connected to source V, while the collector is connected to point B. In all cases the control circuits of T, and T2 are of known types.

From the foregoing it appears that there is a large freedom in dimensioning inductances L, and L2. Of course, the maximum permissible current through switches Tt, D and T2, D2 is a limitation During operation th'e difference between voltage V and the voltage at point A (Fig. 2a) is present across inductance L1,while the voltage at point B (Fig. 2b) is present across inductance L2. The voltages across the inductances are equal.

Therefore, inductances Lr and L2 may be magneticdlly coupled, namely such that the voltage induced across one inductance by the other inductance as a result of the coupling is equal to and has the same polarity as the voltage produced by the action of the circuit across the considered inductance in the absence of a coupling. The inductances would then be in the form of two windings provided on one and the same core of magnetic material. This measure has the evident advantage that there is only one component, namely a transformer, instead of two components, while the currents flowing through inductances L, and L2 and, consequently, through switches T,, D, and T2, D2 are reduced. To avoid short-circuit currents, the two windings must have the same number of turns.As owing to tolerances the numbers of turns may be unequal, a leakage inductance may be built-in for safety's sake. Other windings may be provided on the transformer core, pulse-shaped voltages being present across these windings. Rectifying these voltages results in d.c. voltages. However, this last measure is generally not possible when the deflection current for the so-called east-west correction is subjected to a modulation of field frequency. This said modulation can be obtained in a simple manner by superimposing a voltage which varies at field frequency on the voltage of source V, in response to which the wdveforms of Fig. 2 vary also at field frequency. This variation is, for example, in the form of a parabola.

In accordance with a variant, not shown of the circuit of Fig. 1 inductance L, is connected to a d.c. voltage V,, while the collector of transistor T2, the cathode of diode D2 as well as the terminal, which is not connected to point B, of capacitor C2 are connected to a d.c. voltage V2. Herein V, and V2 are two unequal positive d.c. voltages. So Fig.

1 represents the case where V,=V2. In a similar manner as above it can be demonstrated that the voltage across capacitor C is equal to V, and that the trace voltage across coil L is equal to V,-, V2. It can also be demonstrated that the capacitances of capacitors C, and C2 must be unequal in the case, where V, and V2 are different, namely such that the ratio C C2 must be equal to the ratio V2 V,.

Otherwise, the periods of time in which the switches T,, D, and T2, D2 are non-conductive would be unequal, that is to say diodes D, and D2 would not start conducting at the same instant.

For the same reason the capacitances must be equal for the case where V,=V2.

Fig. 3 shows a further variant having a positive V, and a negative supply source -V2. This circuit has the same properties as the circuit outlined; above and has the additional advantage that the control circuit (not shown) of transistor T2 is electrically connected to ground instead of to a supply voltage. Transistor T2 is then of the pnptype, its emitter being connected to ground, while diode D2 has the conductivity direction shown.

Further variants are possible, in which network L, C is operationally coupled to inductances L, and/or L2 by means of a tap or a magnetic coupling. When the absolute values of the supply voltages are unequal then the voltages across inductances L, and L2 are also unequal, so that a magnetic coupling is only possible between portions thereof, unless the number of turns thereof have been adapted.

Claims (9)

Claims

1. A circuit for generating a sawtooth-shaped deflection current having successive trace and retrace periods through a line deflection coil which coil is part of a deflection network the end of which network is operationally coupled to an inductance, said inductance being serially connected with a controllable bidirectional switch which is capable of conduction in both of two directions to form a supply network, one end of the supply network being connected to a point for conveying a d.c. voltage whilst its other end is directly connected to a point of reference potential, the switch, in operation, being conductive during the said trace periods and non conductive during the said retrace periods, characterised in that the other end of the deflection network is operationally coupled to a second inductance, said second inductance being serially connected to a second controllable bidirectional switch which is also capable of conduction in both of two directions to form a second supply circuit, one end of the second supply network being connected to a point conveyivg a second d.c. voltage whilst its other end is connected to the said point of said reference potential and wherein, in operation, the second switch is also conductive during the said trace periods and non-conductive during the said retrace periods.

2. A circuit as claimed in Claim 1, characterised in that the first and the second d.c.

voltages have the same polarity, a terminal of the first switch as well as one end of the second inductance being connected to the said point of reference potential.

3. A circuit as claimed in Claim 1, characterised in that the first and the second d.c.

voltages are of opposite polarity, a terminal of the first switch as well as a terminal of the second switch being connected to the said point of reference potential.

4. A circuit as claimed in Claim 2 or 3, in which the deflection network includes retrace capacitance, characterised in that the first and second d.c. voltages have the same absolute values, the retrace capacitance consisting of a first retrace capacitor arranged in parallel with either the first switch or the first inductance and of a second retrace capacitor arranged in parallel with either the second switch or the second inductance, the first and the second retrace capacitor each having substantially the same capacitance.

5. A circuit as claimed in Claim 2, or Claim 3, in which the deflection network includes retrace capacitance, characterised in that the first and second d.c. voltages have unequal absolute values the retrace capacitance consisting of a first retrace capacitor arranged in parallel with either the first switch or the first inductance and of a second retrace capacitor arranged in parallel with either the second switch or the second inductance, the ratio between the capacitance of the first retrace capacitor to the capacitance of the second retrace capacitor being substantially equal to the ratio between the value of the second d.c.

voltage to the value of the first d.c. voltate.

6. A circuit as claimed in any of the preceding Claims, characterised in that the first and the second inductances are at least partially magnetically coupled.

7. A circuit as claimed in any of the preceding Claims, characterised in that a winding is coupled to one of said inductances, a rectifier being connected to this winding for deriving a d.c.

voltage therefrom.

8. A circuit as claimed in Claim 1 or 2, characterised in that the first and the second d.c.

voltages are of equal value and originate from the same source and contains a component which varies at field frequency.

9. A circuit for generating a sawtooth shapeddeflection current substantially as herein described with reference to the accompanying drawing.