GB2072900A - Data processing system - Google Patents
Data processing system Download PDFInfo
- Publication number
- GB2072900A GB2072900A GB8107277A GB8107277A GB2072900A GB 2072900 A GB2072900 A GB 2072900A GB 8107277 A GB8107277 A GB 8107277A GB 8107277 A GB8107277 A GB 8107277A GB 2072900 A GB2072900 A GB 2072900A
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- United Kingdom
- Prior art keywords
- group
- elements
- processing elements
- data processing
- adjacent
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/006—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation at wafer scale level, i.e. wafer scale integration [WSI]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
- G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
- G06F15/8023—Two dimensional arrays, e.g. mesh, torus
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Computing Systems (AREA)
- Multi Processors (AREA)
Abstract
An array processor in which each sub-array of processing elements has a group of check-bit processing elements associated with it. The check-code processing elements have north-south interconnections, but have no east-west connections. Instead, the northernmost element of each group is connected diagonally 20 to the southernmost element of the neighbouring group, via a respective switch 22 so as to permit serial transfer of check codes, over the north-south connections and the diagonal connections, between adjacent groups in the east-west direction. <IMAGE>
Description
SPECIFICATION
Data processing system
Background to the Invention
This invention relates to data processing
systems of the kind comprising a plurality of processing elements logically arranged in rows
and columns so that each element has four
nearest neighbouring elements. Such a system is .described for example in British Patent
Specifications Nos. 1445714, 1 536933, 2020457, 2019620 and 2037042.
In such a system, it is usually desired to allow
each element to send information to, and receive
information from, any of its four nearest
neighbours. In the specifications referred to above,
this is achieved by connecting each element to its
four neighbours by means of a separate
connection path. One object of the present
invention is to reduce the number of connection
paths required to transfer information between
neighbouring elements.
Summary of the Invention
According to the invention there is provided a
data processing system comprising a plurality of
processing elements logically arranged in rows
and columns, characterised in that each column is
divided into a plurality of groups of elements, the
elements within each group being connected
together to permit information to be transferred
northwards and southwards between adjacent
elements within the same group, and
characterised by a plurality of switching circuits
each having two states, wherein
(a) in the first state the switching circuits
connect the northernmost element of each group
to the southernmost element of the adjacent
group in the northern direction, thereby permitting
information to be transferred northwards and
southwards between adjacent groups in the same
column, and
(b) in the second state the switching circuits
connect the northernmost element of each group
to the southernmost element of the adjacent
group in the western direction, thereby permitting
information to be transferred eastwards and
westwards between adjacent groups in different
columns.
It can be seen that the invention replaces a
plurality of east-west connections between
members of an adjacent pair of groups by a single
"diagonal" connection between the northernmost
element of one group and the southernmost
element of the group to the west of it. Shifting of
information eastwards or westwards is achieved
by placing the switching circuits in their second
states, and then performing a sequence of
northward or southward shifts over the diagonal
connections. It can be seen that the invention
significantly reduces the number of connection
paths.
In a particular embodiment of the invention to
be described, the system comprises a plurality of
data processing elements and plurality of check
code processing elements, each check code
processing element holding a check code (e.g.
parity bits) in respect of a predetermined plurality
of data processing elements. In the described
embodiment, the invention is used to reduce the
number of connections between the check code
processing elements. However, the data
processing elements are connected in the
conventional manner i.e. each having a separate
connection path to each of its four neighbours.
It should be appreciated that the phrase
"logically arranged" is intended to imply that the
arrangement of the elements in rows and columns
is not necessarily an actual physical arrangement.
In practice, the elements could be mounted on
printed circuit boards in any convenient physical
configuration, with suitable electrical connections
to form the required logical arrangement.
Similarly, it should be appreciated that the terms
"north", "east", "south" and "west" are used in this specification merely to describe the logical
relationships between the elements and should
not be taken to imply any particular physical arrangement.
Brief Description of the Drawings
One data processing system in accordance with the invention will now be described by way of example with reference to the accompanying drawings of which:~
Figure 1 is an overall block diagram of the system;
Figure 2 shows the connections between the data processing elements, parity processing elements, and parity checking circuits;
Figure 3 shows the interconnections between the data processing elements;
Figure 4 shows a circuit in one of the data processing elements for selecting data inputs from neighbouring elements;
Figure 5 shows the interconnections between the parity processing elements;
Figures 6 and 7 show two possible states of a switching circuit;
Figure 8 shows a circuit in one of the parity processing elements for selecting parity bit inputs from neighbouring elements; and
Figures 9 and 10 illustrate possible ways of connecting parity processing elements consisting of LSI (large scale integrated circuit) chips.
Description of the Preferred Embodiment of the
Invention
Figure 1 shows a data processing system comprising 4096 identical data processing elements D arranged in 64 rows and 64 columns.
Each element may be of the form shown in the published patent specifications referred to above, and will therefore not be described in detail herein.
Briefly, however, each element D contains a data store having a large number of individually addressable bit locations, various single-bit internal registers, a single-bit binary adder, and various gates for controlling the movement of data between the store, registers and adder. The elements D are controlled by signals which are broadcast to all the elements in parallel, so that all the elements perform basically the same operations, but on different data.
The array of elements D is shown as being subdivided into sixty-four square sub-arrays 10, each containing 8 x 8 elements. Each sub-array has a group 12 of eight parity processing elements
P associated with it, one for each row. As described in British Patent Specification No. 2037042, the parity processing elements P are substantially identical with the data processing elements D, and are controlled by the same control signals, so that each parity processing element performs basically the same manipulations or the parity bits as the data processing elements perform on the data. For example, if a data bit is transferred from the store of each data processing element to one of its internal registers, the corresponding parity bit is transferred from the store of each parity processing element to the corresponding internal register in that element.
Figure 2 shows one of the rows of data
processing elements in a sub-array, and the
corresponding parity processing element Output data bits from the eight data processing elements are fed to a parity checking circuit 14, where they are checked against the corresponding parity bit from the parity processing element. If there is an error, the checking circuit 14 generates an error signal. Parity checking is well known, and so it is
not necessary to describe the circuit 14 in detail.
Figure 3 shows the way in which the data
processing elements are connected together to permit transfer of data between them. Each data processing element D is connected to its four
nearest neighbours in the north, east, south and west directions. The exception to this is at the
boundaries of the array where, of course, the
elements have fewer than four neighbours.
However, the elements along the north edge of
the array may be connected to those on the south
edge so that each column consists effectively of a
loop of elements. Similarly, the rows may be
connected as loops.
The direction of transfer of data between the
elements is governed by a routing code which is
broadcast to all the elements in parallel. The
routing code consists of two bits, the significance
of which is as follows:~
Routing code Direction
CO North
01 East
10 South
11 West
Referring to Figure 4, each data processing
element contains a multiplexer 16 having four
inputs 0, 1, 2, 3 connected to receive data from the four neighbouring elements in the south, west, north and east directions respectively. The multiplexer 16 is controlled by the routing code, so that it selects one of its four inputs in accordance with the binary value of the code. For example, if the routing code is 00, input 0 is selected, so that each element accepts data from its southern neighbour. As a result, data flows northwards.
Figure 5 shows the way in which the parity processing elements P are interconnected. Within each group 12 they are interconnected by northsouth connections 18. However, there are no eastwest connections. Instead, transfer of parity bits between adjacent groups of parity processing elements in the east-west direction is achieved by diagonal paths 20 which connect the northernmost element in each group with the southernmost element in the adjacent group to the west. Switching circuits 22 are provided to determine whether the parity bits are to be shifted between adjacent groups in the north-south direction or over the diagonal paths 20.
Each switching circuit 22 has two states and is controlled by the second bit of the routing code.
When the routing code denotes north or south (i.e.
the second bit =0) the switching circuit makes the connection shown in Figure 6 i.e. it connects the northernmost element in each group to the southernmost element in the adjacent group to the north. When the routing code denotes east or west (i.e. the second bit = 1) the switching circuit makes the connection shown in Figure 7 i.e. it connects the northernmost and southernmost elements to the respective diagonal paths 20.
Although the switching circuits 22 are represented symbolically in the drawings as mechanical switches, in practice they are electronic switches constructed in a conventional manner from known logic components.
Referring to Figure 8, each parity processing element P contains a multiplexer 40 having four inputs 0, 1, 2, 3 and controlled by the routing code in a similar manner to the multiplexer 1 6 in
Figure 4. However, in this case, there is no connection from eastern and western neighbours.
Instead, the input from the southern neighbour is connected to inputs 0 and 3, and the input from the northern neighbour is connected to inputs 1 and 2.
Thus, when the routing code denotes west 1), the parity bits are shifted northwards within the groups of elements and are shifted over the diagonal paths 20 (because of the switching circuit connections shown in Figure 7) between groups. It can be seen that after eight such shifts have been performed the contents of each group of parity processing elements will have been shifted westwards into the adjacent group of parity processing elements, corresponding to the westward shift of data from one of the sub-arrays
10 (Figure 1) into the adjacent sub-array.
Similarly, when the routing code denotes east (01) the parity bits are shifted southwards within the groups and over the diagonal paths 20
between groups, so that after eight such shifts the
contents of each group of parity processing
elements will have been shifted eastwards into the
adjacent group of parity processing elements.
In summary, it can be seen that whenever data
is shifted by a multiple of eight steps between the .data processing elements D, the corresponding
parity bits are shifted between the parity
processing elements so as to maintain them in the correct relationship to the data.
The data processing elements and parity
processing elements are preferably implemented
in the form of LSI (large-scale integrated circuit)
chips. Conveniently, four processing elements may
be incorporated in each LSI chip, providing a 2 x 2
portion of the array. However, it can be seen from
Figure 5 that the parity processing elements must
be connected in a linear manner rather than in a 2-dimensional array.
The way in which this problem is solved is
shown in Figure 9. This shows two LSI chips 40
and 42, each containing a 2 x 2 configuration of
parity processing elements. The south-western
element on each chip has its southern connection
44 wired to the northern connection 46 of the
north-eastern element on the same chip. Also, the
southern connection 48 from the south-eastern
element on the upper chip 40 is wired to the
northern connection 50 from the north-western
element on the lower chip 42. The effect is to join
the eight elements in series, by way of their north
south connections, thus forming one of the groups
12 of parity processing elements shown in
Figure 5.
In the above-mentioned Patent Specification
No. 2020457 there is described a way of reducing
the number of terminals on an LSI chip by
combining adjacent pairs of terminals. The present
invention could equally well be implemented using
chips of the form described in that specification.
Figure 10 shows the way in which two of these
chips 52 and 54 would be connected to achieve
the same effect as in Figure 9.
In the arrangement described above, there are
different data connections to the routing
multiplexers in the data processing elements and
the parity processing elements, as shown in
Figures 4 and 8. However, in an LSI
implementation, it would probably be more
convenient to make these connections identical Ai.e. to make them all as shown in Figure 4) and
instead to vary the address inputs to the routing
multiplexers, so that the parity processing
elements would receive only "north" and "south"
routing codes.
In another variation of the system described
above, the array could be divided into rectangular
sub-arrays instead of square sub-arrays. In such
an arrangement, it is clear that the number of
steps needed to shift the parity bits in the east
west direction between adjacent groups, over the
diagonal paths, would be different from the
number of steps needed to shift the data bits
between adjacent sub-arrays. It would therefore
be necessary to introduce additional control circuits to inhibit some of the clock pulses to (or generate some extra clock pulses for) the parity processing elements during the east-west shifts to ensure that the parity bits were kept in the correct relationship to the data.
Claims (6)
1. A data processing system comprising a plurality of processing elements logically arranged in rows and columns,
characterised in that each column is divided into a plurality of groups of elements, the elements within each group being connected together to permit information to be transferred northwards and southwards between adjacent elements within the same group,
and characterised by a plurality of switching circuits each having two states, wherein
(a) in the first state the switching circuits connect the northernmost element of each group to the southernmost element of the adjacent group in the northern direction, thereby permitting information to be transferred northwards and southwards between adjacent groups in the same column, and
(b) in the second state the switching circuits connect the northernmost element of each group to the southernmost element of the adjacent group in the western direction, thereby permitting information to be transferred eastwards and westwards between adjacent groups in different columns.
2. A data processing system comprising a plurality of data processing elements logically arranged in rows and columns, each data processing element being connected to each of the four neighbouring data processing elements to permit transfer of data between them,
a plurality of check code processing elements, each of which holds a check code in respect of a predetermined plurality of said data processing elements, the check code processing elements also being logically arranged in rows and columns,
characterised in that each column of check code processing elements is divided into a plurality of groups of check code processing elements, the elements within each group being connected together to permit check codes to be transferred
northwards and southwards between adjacent elements within the same group,
and characterised by a plurality of switching circuits each having two states, wherein
(a) in the first state the switching circuits connect the northernmost check code processing element of each group to the southernmost check code processing element of the adjacent group in the northern direction, thereby permitting check codes to be transferred northwards and southwards between adjacent groups in the same column, and
(b) in the second state the switching circuits connect the northernmost checking code processing element of each group to the southernmost check code processing element of the adjacent group in the western direction, thereby permitting check codes to be transferred eastwards and westwards between adjacent groups in different columns.
3. A system according to Claim 2 wherein a routing code having four values representing north, south, east and west respectively is broadcast to all the check code processing elements and data processing elements in parallel.
4. A system according to Claim 3 wherein each data processing element has a selection circuit controlled by the routing code for selecting data from its northern, southern, eastern or western neighbours according to whether the routing code represents south, north, west or east, and each check code processing element has a selection circuit also controlled by the routing code for selecting a check code from its northern neighbour if the routing code represents south or east and from its southern neighbour if the routing code represents north or west.
5. A system according to Claim 3 or 4 wherein the switching circuits are controlled by the routing code such that they are in the said first state when the routing code represents north or south and in the said second state when the routing codeg represents east or west.
6. A data processing system substantially as hereinbefore described with reference to the accompanying drawings.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB8107277A GB2072900B (en) | 1980-03-28 | 1981-03-09 | Data processing system |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB8010574 | 1980-03-28 | ||
GB8107277A GB2072900B (en) | 1980-03-28 | 1981-03-09 | Data processing system |
Publications (2)
Publication Number | Publication Date |
---|---|
GB2072900A true GB2072900A (en) | 1981-10-07 |
GB2072900B GB2072900B (en) | 1984-02-22 |
Family
ID=26275019
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB8107277A Expired GB2072900B (en) | 1980-03-28 | 1981-03-09 | Data processing system |
Country Status (1)
Country | Link |
---|---|
GB (1) | GB2072900B (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0186150A2 (en) * | 1984-12-24 | 1986-07-02 | Hitachi, Ltd. | Parallel processing computer |
-
1981
- 1981-03-09 GB GB8107277A patent/GB2072900B/en not_active Expired
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0186150A2 (en) * | 1984-12-24 | 1986-07-02 | Hitachi, Ltd. | Parallel processing computer |
EP0186150A3 (en) * | 1984-12-24 | 1988-06-22 | Hitachi Ltd | Parallel processing computer |
Also Published As
Publication number | Publication date |
---|---|
GB2072900B (en) | 1984-02-22 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
732 | Registration of transactions, instruments or events in the register (sect. 32/1977) | ||
PCNP | Patent ceased through non-payment of renewal fee |