GB2071868A - A process controller - Google Patents

Abstract

A process controller includes electronic memory units M1-M8 for storing respective programs. Either a manual operable programmer initially programs each unit or the units are reprogrammable and the manually operable programmer comprises part of the controller. Each memory unit has N memory channels, each storing M steps. A circuit selects a particular unit and thereby its program. A circuit generates clock pulse signals to determine the interval between program steps. A binary counter stepped by the clock pulses, advances the units through the program steps. An interface buffer having N channels produces operation signals for controlling the ON/OFF condition of a process parameter. An address Display indicates the program step being effected. <IMAGE>

Description

SPECIFICATION A process controller This invention relates to a process controller for controlling a series of time related process parameters and more especially to a process controller including electronic memory units.

Process controllers are known in which a series of time related process parameters are controlled by the passage of a programme card through a viewing mechanism. Typically, such a programme card is divided into a series of 32 parallel tracks and the discrete steps on each track correspond to a window which is either translucent or opaque to the passage of a viewing beam to be sensed photo-electrically. The programme card is stepped incrementally and the interval between steps determines the basic time interval of the programme. Usually, each track will have a series of 1 28 windows giving the same number of possible programme changes for each track. The major problem encountered with these programme cards is the problem of distinguishing one track from its neighbour.Experience has shown that the optical inspection of a track is subject to errors due to illumination incident from windows of adjacent tracks. Furthermore, the programme card is a permanent form of process control data carrier. Once the windows are selected to be translucent or opaque according to an initial programme of process parameters., if the process parameters are to be altered it is troublesome for the user to alter the programme card and usually a new programme card will be required. In order to change from one process control programme to another, it is necessary to complete the run of a programme card and replace that programme card manually with another programme card.

The present invention seeks to provide a process controller in which: (a) a series of separate process control programs are electronically stored; (b) each programme is capable of controlling a series of process parameters; (c) each program has a selectable time interval between steps in its program of time related process control steps; (d) each program may be interrupted or terminated: (e) each program may be initiated at will through an electronic signal; (f) the controller generates electrical output signals for the control of process parameters via operating components.

In its broadest aspect the process controller includes memory units for storing programs.

Each memory unit may contain a stored program. A manually operable programmer unit may be provided for initially programming each memory unit. Alternatively, the memory units may be reprogrammable and the manually operable programmer unit may comprise part of the process controller. In such a controller the manually operable programmer unit is used to store the initial programs in the memory units and to edit or update the programs in accordance with changes required in the process being controlled.

According to one aspect of the invention there is provided a process controller comprising a plurality of memory units each with N memory channels and each channel storing M steps, a memory unit select circuit operable to select one of said memory units and thereby the program stored therein, a clock pulse circuit generating at least one clock pulse signal, whereby the time interval between steps of the memory unit is controlled, a binary counter stepped by the clock pulse circuit and generating a binary count for advancing the memory units through the program steps, and, an interface buffer unit having N channels operable to receive binary output signals from individually associated ones of the N memory channels and produce operation signals for controlling the ON/OFF condition of a process parameter.

Preferably, the process controller further in ciudes an Address Display permitting the user to obtain a visual indication of the count of the binary counter and thereby the program step which the process controller has reached.

A programmer unit may be provided, which comprises a Read/Write circuit and N program channels each with a visual display for indicating the binary status ''0''/''1'' of that channel, switching means in each channel for use in program writing operations to set each channel to read the desired binary status ''0''/''1'' according to whether the parameter controlled by the associated memory channel is required to be "ON"/"OFF", and a WRITE switch for inputting the binary status of the program channels to the memory channels after the program channels are set.

The programmer unit may also include a single step advance switch and a fast forward advance switch for advancing the binary counter during writing operations of the programmer.

The memory units may include means for selecting the time interval between program steps by selecting which of a plurality of clock signals, each with different time periods, is employed to enable that memory unit.

In the preferred embodiment, there are 8 memory units M1 to M8 for 8 programs, the number of memory channels N is 32 and the number of steps M in each program is 256 and eight clock signals have periods between 10 seconds and 80 seconds incremented by 10 seconds. These numerical features may be varied according to the user requirements specified for the process controller by making corresponding changes in the controller circuitry as will be apparent to those skilled in the art from the following description of a preferred embodiment.

An embodiment of the invention will now be described, by way of example only, with reference to the accompanying drawings, in which Figure 1 shows diagrammatically a process controller according to one embodiment; Figure 2 is a schematic of the bus bar linking the circuits of Figs. 3 to 7; Figures 3A, 3B and 3C are circuits of the clock circuitry, binary counter and memory unit select of Fig. 1; Figure 4 is a detailed circuit of one of the eight memory units of the memory of Fig. 1; Figures 5A and 5B are circuits of the programmer of Fig. 1 showing the programme channel P, for programming one of the thirty two channels of a program:: Figure 6 is a circuit of an Address Display for giving a visual indication of the count at the binary counter and thus the program step being passed to the inferace buffer unit; Figure 7 is a circuit of the interface buffer unit of Fig. 1, again with the components for one of the thirty-two program channels.

GENERAL DESCRIPTION OF PROGRAMMA BLE PROCESS CONTROLLER A process controller according to one embodiment, is illustrated diayrammatically in Fig. 1. The controller is employed to control 32 process parameters by means of Output signals on each of thrity two interface buffer unit channels 11 to 13 from the Interface Buffer Unit, the circuitry of which is illustrated in Fig. 6. Each signal of Channeis I to I,, is an ON/OFF signal corresponding to the binary status "0"1"1" of a memory unit chan nei. The 32 channels of Interface Buffer unit receive 32 binary signals from one of the memory units M, to M; the circuitry of memory unit My is shown in Fig. 4.

The choice of memory unit from units M- to M is determined by a memory unit select circuit, the circuitry of which is shown in Fig.

3C which includes switch S4 The selected memory unit has a light emitting diode LED (not shown) which illuminates to indicate which memory unit (1) to (8), ancl thus which process control program (1) to (8), is selected.

The memory Li flt it select circuit addresses the memory units M to M in binary coded decimal (BCD).

Each memory unit M to M- includes means of selecting a time Interval (to be described with reference to Fig. 4) in this embodiment from 10 to 80 seconds in 10 second incre marts. for the interval between steps in its 2bb. step program Each step is stored in the memory unit as a binary "0" or "1" and each memory unit has 32 channels. As will be clear to those skilled in the art, the number of channels and number of steps may be increased or decreased by appropriate changes to the circuitry.

In this embodiment, the memory units each comprise 8 four-bit RAMS (random access memories) giving 32 channels which are programmed at will by the programmer. It will be apparent to those skilled in the art that permanent memory units may be employed by replacing the RAMS by ROMS (read only memories) or EPROMS (electrically programmable read only memories). Thus, whilst the supplier of the process controller may be required to employ a programmer as described herein, to customize the process controller, the user may purchase and use the process controller with or without the programmer.

In order to step the memory units through the program steps, a binary counter circuit, the circuitry of which is shown in Fig. 3B, sends binary signals, which are incremented by clock reset signals R/S;on line Lie, to the memory units M, to M8. For a visual indication of these binary signals, these signals are also address to an Address Display Unit, the circuitry of which is shown in Fig. 6.

The clock pulse signals C/K for the memory units M1 to M8 (in this embodiment eight signals with periods of 10 to 80 seconds in 10 second increments) are generated by the clock pulse circuitry of Fig. 3A.

A programmer having 32 program channels P individually related to the 32 memory channeis in each memory unit. is used to WRITE by means of switch S,, the programs in the memory units M, to M8 and has a visual display whereby the binary values of each program channel P, to P32 at each step of the program may be displayed. The programmer circuitry shown in Figs. 5A and 5B has a WRITE/READ circuitry of Fig. 5A including the visual display and a stepping circuitry for "single step" and "fast forward step" advance by means of switches Se, S7 respectively of the binary counter for use in writing or modifying the stored programs. The WRITE/ READ circuitry sends a WRITE/READ signal W/R to the memory units M, to Ms which in the normal mode is a READ only signal.

WRITE signals are transmitted only when the WRITE switch S of Fig. 5A is depressed after the LED(2) light emitting diode of each programmer channel P, to P32 has been manually set by switches SP1 of each channel to indicate the desired binary status "O"/"1" for each of the 32 channels in the addressed memory unit of M, to M8. When switch S5 is depressed, the binary status of the programmer channels P1 to P32 is stored by the 32 associated channels of the addressed memory unit.The programmer advances the active memory unit M, to M to the next programme step by manual depression of switch S6 of Fig. 5B and the status of the programme channels P1 to P32 are reset as required by manipulation of switches Sup1, then the WRITE switch S5 of Fig. 5A is depressed again. This sequence is repeated for the 256 program steps. For editing a step in a memory unit, the binary counter, and thus the Address Display, may be rapidly advanced by means of the "fast forward step" switch S7 of Fig. 5B.

Prior to programming it is necessary that the binary counter, which during normal running of a program in the memory units M, to M5 is controlled by the clock circuitry of Fig.

3A, is first reset and then controlled by the stepping circuitry of Fig. 5B. For resetting of the binary counter, the circuit of Fig. 38 is provided with manually operable reset switch S3.

Likewise, when operating the memory unit select circuitry of Fig. 3C by means of switch S4, it is necessary that the clock circuitry of Fig. 3A is inhibited and the binary counter is reset. Stop switch S of Fig. 3A inhibits the clock circuitry and reset switch S3 of Fig. 3B resets the binary counter. The memory unit select circuitry of Fig. 3C has a NAND-gate (to be further described) which on line L35 receives the clock inhibit signal C/I from the Fig. 3A circuit and receives on line L39 the binary counter reset signal R/S from Fig. 3B circuit. Only when both these signals are present does the NAND-gate allow the switch S4 to step the BCD output signal of the memory select unit through the sequence of BCD addresses for the memory units.

During process control use of the process controller. START switch S1 of the clock circuitry initiates the clock signals and thereby the program of that memory unit selected for operation by the memory unit select. In the aforegoing generalised description no reference has been made to the bus lines A, to A33 and B, to B32 which will be described with reference to Fig. 2 and which are included in Fig. 1 in order that the reader may relate the description of Fig. 2 to the generalised description of Fig. 1. The operation of switches S1 to S3 and SP, will be further described below.

THE BUS The process controller comprises units to be described with reference to Figs. 3 to 7. For communication between these units a bus is provided which is illustrated schematically in Fig. 2.

Lines A1 to A33 are allocated to the circuits as follows Lines A1 and A33 are the positive voltage and ground lines respectively which carry the regulated 5 volt supply to each circuit.

Lines A2 to A" enable binary signals from the binary counter of Fig. 38 to be passed to the memory units of Fig. 4 and the Address Display of Fig. 6: only lines A3 to A9 are required in the embodiments of Figs. 4 and 6 described which operate with 256 program steps (0 to 255), but lines A,,. A.1 allow the process controller to be expanded for use with memory units capable of storing up to 1024 steps.

Line A,2 is allocated for READ/WRITE purposes and carries the WRITE signal from the READ/WRITE circuit of Fig. 5A to the memory units of Fig. 4.

Lines A,3 to A,5 carry the binary coded decimal (BCD) address signals from the memory unit select circuit of Fig. 3C to the memory units of Figs. 4.

Line A,6 is the strobe line which carries a disenable signal from the programmer stepping circuit of Fig. 5B to the memory unit of Fig. 4 during stepping operations.

Lines A,7 to A33 are not allocated.

Line A33 is the line carrying the clock reset signal R/S from the memory units of Figs. 4 back to the clock circuitry of Fig. 3A.

Lines A34 to A31 carry the clock signals C/K from the clock circuitry of Fig. 3A to the memory units of Fig. 4.

Lines B1 to B32 carry the output signals from the enabled memory unit (Fig. 4) to the Interface Buffer Unit of Fig. 7, and the programmer of Figs. 5A and 5B.

CLOCK PULSE CIRCUITRY In Fig. 3A there is shown the clock pulse circuitry for the programmable process controller of Fig. 1. At the right of Fig. 3A there are manually operable start and stop switches S1, S2, which enable the user to start or stop a process program. Line L1, which is connected to bus line A1, is at 5 volts DC and Line L2, which is connected to bus line A32, is at ground potential. Line L3 includes switch S1 and is connected to input pin P, of NAND gate N, and by means of resistor R, (100 ohms) in line L5 to the line L,.Likewise, line L4 includes switch S2 and is connected to input pin P3 of NAND gate N3 and by means of resistor R3 (100 ohms) to the line L1. A capacitor C, (10eel farad) is connected across switch S3 to ground line L2. The output pins P3 of Nand-gates N, and N3 are connected respectively to the inputs pins P,, P2, of Nandgates N3 and N,. Both Nand-gates N1, N3, are incorporated in a standard integrated circuit component IC 7400. The output pin P3 of Nand-gate N3 on line L3 is employed as a clock inhibit signal C/I for the integrated circuit component IC 401 7 when stop switch S2 is depressed. A clock inhibit signal also appears on line L36 (to Fig. 3C) which is connected to line L7. The clock inhibit signal C/I on line L7 to pin P,2 of the integrated circuit 4017 allows this integrated circuit to be inhibited on each occasion that a clock inhibit signal C/I appears on line L7.Circuit 401 7 which operates as a decade counter, is provided with a reset input pin P,3, connected to line L8. a clock pulse input pin P10 connected to line L9, and timing pulse outputs pins P1 to P8 of which the first is not connected and the remainder will be connected as later described. Further, line L,O connects integrated circuit IC 4017 at pin P" to the positive line L, and pin P9 is connected to ground line L2. The integrated circuit 555 is connected as an astable timer circuit producing 10 second pulses. Thus a pulse appears on an output pin P3 to line L9 every 10 seconds.The time interval between these pulses is determined by timing resistors R3. R4 (one kilo ohm and a variable 100 kilo ohms respectively) and capacitor C3 (100 ii farad).

Thus, a fine adjustment in the time interval is effected by adjusting variable resistor R4.

Lines L11, L,2 connect VCC pins P4. P8 and ground pin P, of IC 555 to positive line L, and ground line L2. Line L13 from control voltage pin P5, includes capacitor C3 (0.1 y farad). Line L14 extends from discharge pin P7 of IC 555 to line L and includes timing resistor R3. Line L115 extends from discharge pin P7 to ground line L2 and includes variable timing resistor R4 and timing capacitor C2, line L.6 extends between trigger pin P3 of IC 555 and line L,5. IC NE 555 is available from National Semiconductors.

With integrated circuit IC 401 7 enabled and clock component IC 555 running, pulses generated along line L3 are counted by the decade counter IC 401 7. At the output pins P, to P6 of couner IC 4017, the first output pin P1 is disenabled, pulses appear on the output pins P3 to P8 at intervals of 10 seconds to 80 seconds (in increments of 10 seconds) respectively. Eight lines T, to T8 carry pulses representative of intervals of 10 seconds, 20 seconds up to 80 seconds respectively to correspondingly allocated lines A24 to A31 on the bus-bar. Line T, is derived directly from line L9 as the response time of IC 401 7 requires its output pin P1 to be disenabled as mentioned above.

In order to describe the reset feature of the integrated circuit 401 7 it is convenient to assume that the first memory unit is enabled and that a stepping time interval of 10 seconds has been selected for this memory unit.

Then, when integrated circuit 401 7 receives a first ten-second pulse on line L9 from clock circuit 555, this pulse travels along line T, to line An.., of the bus bar. This clock signal C/K travels via line A24 of the bus bar to the first memory unit (which is enabled). As will be described with reference to Fig. 4, the first memory unit returns a clock reset signal R/S on the clock reset line A23 of the bus bar to line 15.

This clock reset signal R/S returns from line A of the bus bar along the clock reset line L.. to pin P of integrated circuit IC 74121(1) which is a single shot monostable circuit: suffix (1) being a circuit reference. The other pins of IC 17421(1) are connected as follows: pin P, is connected via line L16 to a binary counter to be further described in relation to Fig. 3C; pin P3 is connected via line L,7 to the clock inhibit line L7; pin P" is connected via line L,8, which includes resistor R14 (47K ohms) to positive line L2; pin P6 is connected to line L5 which, in turn is connected to pin P,3 of integrated circuit IC 401 7 for resetting same; pin P6 is also connected by line L30. which includes resistor R13 (1 K ohm) and the light emitting diode LED1, to ground line L2; pins P9 and P6 are inter-connected by line L2r which includes capacitor C4 (10 jt farad); pins P3, P7 are connected to lines L1, L3 resp. LED1 indicates the generation of a step, ping pulse on line L16 on each occasion that a clock reset signal R/S appears at pin P, of IC 74121(1).

When the clock reset signal R/S appears as a pulse at pin 1 of integrated circuit IC 74121(1), this circuit generates a positive going pulse at its pin P6 which is applied via line L5 to pin P,3 of the integrated circuit 401 7 and resets that circuit. Simultaneously, integrated circuit IC 74121(1) generates a negative going stepping pulse at its pin P, which is applied via line L,6 to the pin P, of the binary counter to advance that counter.

This advance of the binary counter causes the program to advance a step as will be further described.

The timing counter of integrated circuit IC 4017(1) is reset to zero by means of a pulse at its pin P,3 generated by the IC 74121(1) at its pin P6 in response to the clock reset signal R/S on bus line A33 appearing via line L15 at pin P3 of IC 74121(1), after the interval selected for operation of the active memory unit. Stepping thus, if the memory unit has an operating interval of 80 seconds, the integrated circuit IC 401 7 outputs pulses every 80 seconds on its pin P8 under the control of the clock reset signal R/S via the monostable IC 74121(1). Capacitor C1 across Switch S2 ensures that at the initial power on situation the stop condition is held until start switch S, is actuated.

BINARY COUNTER CIRCUITRY This circuitry is shown in Fig. 3B. As above mentioned the integrated circuit IC 74121(1) receives a clock reset signal C/S at its pin P3 and generates a positive going pulse at its pin P, which is applied via line L.6 to the binary counter. The binary counter generates binary signals designating the steps in the process program i.e. from 0 to 255; step 256 corresponding to 000 and being the reset signal to the addressed memory unit at the end of a process program. The binary counter comprises four integrated circuits IC 7493 arranged in cascade and labelled by the suffixes (1) to (4).Each integrated circuit IC 7493 is a binary counter and each has output pins P2, P3, P4, an input pin P1 and a reset pins P5 and P. Each of the reset pins P6 are connected to common reset line L72 which includes manually operable reset switch S3 and is connected to the positive line L1. Actuation of switch S3 enables the user to reset the binary counter.

Each of reset pins P6 are connected to line L39 which carries reset signals to the memory unit select circuitry of Fig. 3C described below, to indicate that the binary counter is reset before selecting a memory unit.

Looking first at the integrated circuit IC 7493(1) its output pins P3 to P4 are connected to output lines L23, L24, L26, respectively. Line L25 is connected by line L36 to input pin P1 of integrated circuit IC 7493(2).

Each of the succeeding integrated circuits IC 7493(2) and IC 7493(3) have similar output ines L27-L29, and L3,-L33, respectively and lines L30 and L34 are similar in function to line L26 The final integrated circuit IC 7493(4) in the cascade is only employed for the output on its output pin P7 to line L35. The output lines L23-L25, L27-L29, L31-L32 are similar and enable binary in 8-bit form to be transmitted along lines A3 to A9 of the bus bar for initiating in sequence the steps 0 to 255 of a process program in an addressed memory unit.Each of these output lines from the least significant digit (LSD) line L33 to the most significant digit (MSD) line L35 is similar and a description of line L23 will suffice for all. Line L33 from output pin P3 to line A3 of the bus bar, includes an integrated circuit component IC 7404 which is an inverter, resistor R7 (4K7) and transistor BC107 which is arranged as a common emitter buffer. The common emitters of the ten transistors BC107 (one in each line) are connected to ground line L3 by line L36. The collectors of each of these transistors BC107 are each connected by a respective resistor R6 (1 K ohm) to line L37 and thereby to positive line L1.The output on lines L33 from transistor BC107 matches the polarity of the output pin P3 of the integrated circuit IC 7493(1) due to the double inversion, firstly at inverter IC 7404 and then on the buffer transistor BC107. The eight-bit binary is addressed to the memory units via the corresponding highway "Binary Address OUT PUTS" of lines A3 to A9 on the bus bar.

MEMORY UNIT SELECT The choice of memory unit, thereby program, is effected by means of a memory unit select circuit (Fig. 3C). This circuit produces a three-bit binary coded decimal address signal which is employed to address the memory units as an enable signal along the lines A13-A,5 of the bus bar addressed by lines L40 1 Program select switch S4 is manually operable and successive actuations thereof enable the user to select the desired memory unit. Line L3 is the ground line connected to bus line A37 (previously mentioned).Integrated circuit 74121(2) is a single shot monostable (suffix (2) is a circuit reference) and its pins are connected as follows: pin P1 via line L43 to ground line L2; pin P3 via line L44 to switch S4; contact bounce elimination components R9 (1 K ohm) and capacitor C5 (10 y farad) are arranged in respective lines L45, L46 between lines L44 and L2; switch S4 is further connected to positive line L, by line L47 which includes resistor R" (1 K ohm); pin P3 IS CONNECTED VIA LINE L46 to positive line L,; pin P4 is connected via line L49, which includes capacitor C6 (0.1 p. farad), to pin P5; pin P6 is connected via line L60 which includes resistor R10 (33K ohms), to positive line L1; and pin P7, which is the output pin, is connected via line L51 and IC 7400 to pin P7 of integrated circuit IC 7493(5) which is a binary counter with a three-bit binary coded decimal output on its pins PA, PB, PC to lines L40-L42 and thereby to bus lines A,3 to A16. Binary counter of integrated circuit IC 7493(5) (the suffix (5) being merely for identification in the drawing) has further pins P1 and P3 connected by lines L53 and L53 to positive line L1 and ground line L2 respectively.Each actuation of switch S4 causes single shot monostable IC 74121(2) to output a pulse on its pin P7 which, in turn, appears as an input pulse on pin P3 of binary counter IC 7493(5). Binary counter IC 7493(5) transmits a memory unit enable signal, which is a three-bit binary coded decimal signal, on its output pins PA, PB, PC. This signal passes along bus lines A13 to A16 to address in binary coded decimal, the memory units (labelled 1 to 8) and enables one of these with the corresponding address, according to the contemporary count of the binary counter IC 7493(5).Each memory unit has a light emitting diode (to be described) only one of which will be illuminated when its memory unit is enabled, whereby the user continues to actuate the switch S4 incrementing the binary counter IC 7493(5) until the desired memory unit is enabled. As it is necessary to disenable the clock circuitry of Fig. 3A and reset the binary counter of Fig.

3B, before effecting a reselection of one of the memory units, the output from pin P7 of IC 74121(2) is directed to the input of integrated circuit 7400 which is a Nand-gate.

This IC 7400 ensures that the pulses, appearing at pin P7 of IC 74121(2) in response to actuation of program selector switch S4, cannot step the counter 7493(5) until both the clock circuitry of Fig. 3A is inhibited and the binary counter of Fig. 3B is reset. This ensures that a new program selected by the switch 54 commences at the first step of the program sequence and not the last read step of the preceding program, which is important in the event that the previous program is terminated prior to its last, 255th step. The clock inhibit signal C/I and the reset signal R/S appear on lines 38, 39 respectively.

THE MEMORY UNITS One of eight similar memory units will now be described with reference to Fig. 4. In Fig.

4 the memory unit comprises eight integrated circuits 211 2A marketed by Intel as a 256 word four-bit static random access memory (RAM) element. The suffixes (1) to (8) are merely circuit references.

Each of the IC's 211 2A receives the binary address inputs from bus lines A3 to Ag, from the binary counter of Fig. 3C, and each generates a binary coded decimal output on respective ones of bus lines B, to Bg2. The choice of eight IC's 2112A(1) to (8) enables 32 output parameters to be controlled over 256 steps.

The binary address inputs on bus lines A3 to A9 are derived from the binary counter of Fig.

3B as described above. The binary count of the binary counter determining the step in the series of 256 for which the IC's 211 2A are to generate outputs on lines B, to B32, when enabled.

For each memory unit the interval between steps in the 256 step programme may be selected by means of a manually-actuable selector MS1 having eight inputs connected to bus lines A24 to A31 and eight outputs connected to a common output line C/K. The manually actuable selector MS1 has a slider which is displaceable to selectively connect one of the inputs to its corresponding output.

Clock timing signals on bus lines A24 to A31 represent clock intervals of 10 seconds up to 80 seconds in increments of 10 seconds.

Thus for the memory unit of Fig. 4 the manually-actuable selector MS1 has been positioned to connect the bus line A34 with the line 1, thus determining a timing interval of 10 seconds for the steps outputted on lines B to B32 of this memory unit. Each of the eight memory units has a given binary address and each receives binary coded decimal (BCD) address signals on bus lines A13/A15. In order to enable the memory unit of Fig. 4, which here is designated memory unit number 1, the bus lines Al 3-A15 are connected to integrated circuit 7442. This IC7442, which is available from Motorola, is a BCD to decimal decoder with mutually exclusive outputs.

A BCD input signal read at its inputs A to C is converted to decimal and appears as an enable signal C/E on a respective one of its outputs numbered 1 to 8, which are connected to common output line C/E. These eight outputs of this IC 7442 are connected to individually associated inputs of an eight line manually-actuable selector MS2, which, like the selector MSl, has a slider displaceable to selectively connect one of its inputs to one of its outputs. In Fig. 4, the memory unit is designated memory unit 1 by the position of the slider of selector MS2. Only when the binary address on the bus lines A13 to Al 5 presents the address signal of memory unit 1 does an enable signal C/E appear on the enable line.

Both the selected clock signal C/K and the enable signal C/E are presented to an integrated circuit 74 1 25 which is a tri-state buffer. The enable signal C/E, when present, to the memory elements 21 12A (1) to (8) at the intervals determined by the clock signal C/K selected by selector MS1. Thus, when the enable signal C/E is present (i.e. when the binary address signals on bus lines A13 to A15 address memory unit 1), then-the memory elements 2112A(1) to (8) are enabled and outputs from these elements appear on the bus lines B1 to B32. Each pulse of the clock signal C/K appearing at the IC74125 causes the IC 74125 to generate a clock reset pulse R/S on bus line A23, whereby, as described - with reference to Fig. 3B, the binary counter is stepped.

Each of the memory elements 211 2A is also connected for Write/Read signals to bus line Awl 2, which will be further described.

Integrated circuit 7442 has an input D connected to bus line A16. Bus line A16 carries a strobe signal generated at the programmer (to be described with reference to Fig. 5B). The presence of a strobe signal on the line Al 6 which is input to IC 7442 at input D ensures that no enable signal appears on line C/E. This strobe signal disenables the memory elements 211 2A and is employed, as will be further described with reference to the programmer of Fig. 5, during stepping operations of the programmer. It will be appreciated by those skilled in the art that a binary signal of 'one' at input D of IC7442 causes the decimal output of this IC to read above the value 8 such that whatever the binary coded decimal signal on lines Al 3 to Al 5 the line C/E (to IC 74126) carries a disenable signal.

As shown, power connections are made via resistors R35, R36 to the bus lines Al and A32 respectively.

As will be apparent from the above description, in this embodiment there are eight memory units and the manually-actuable selector MS2 of each is set for a discrete value corresponding to the address of that memory unit. It is at the users discretion to select for each memory unit one of the time intervals available from the bus lines A,3 to A74 carrying the clock pulses, in this embodiment 10 seconds to 80 seconds for the interval between steps of the program.

It will be readily appreciated by those skilled in the art that the number of memory units may be readily increased or reduced.

The IC 7442 has been described with reference to addressing eight memory units, suitable modifications may readily be accom polished if more memory units are to be em ployed. Similarly, in each memory unit of this embodiment, there are eight memory elements 2112A providing the memory unit with 32 outputs. For controlling more than 32 parameters the number of memory elements 2112A may be increased.

THE PROGRAMMER In Fig. 5A there is shown the READ/WRITE section of the programmer circuitry which functions to Read and Write binary from and into the memory units of Fig. 4. In this embodiment of the process controller, each memory unit stores 256 words or steps in binary in its eight 4-bit memory elements 211 2A giving 32 bits per step of the program whereby binary stored in the memory unit can be employed at each step to control the state ON/OFF of thirty two process operations.

For the purposes of this description each output of a memory unit will be regarded as a channel to the bus lines B1 to B32. In Fig.

5A there is a programmer channel assigned to each of the thirty-two channels of the memory units. As the programmer has the same circuitry for each of its programmer channels, only one programmer channel P1 is shown within the broken line box of Fig. 5A, the remainder of the circuitry is common to all channels.

Channel P1 is assigned to the memory unit channel which addresses bus line 81.

Within the channel P, the line L60 receives the output signal of the corresponding memory channel (of whichever memory unit 1 to 8 is enabled) from bus line B,. This output signal, which is in binary. is buffered by IC 7417 and directed to light emitting diode LED(2). LED(2) is arranged in line L6, between positive line L, and ground line L2 (which are connected to bus lines A,, A37). Line L61 includes resistor R30 (1 K ohm). The conditions of LED2 monitors the status of the signal on the bus line B1-whether it is binary "one" or ''Zero'' and is illuminated for binary '1'''.

The Write circuitry (to the right of Fig. 5A and to be further described) which is common to all 32 programmer channels, enables the programmer swith SP, of each programmer channel P1 to P33 to change the status of its memory channel if desired. If LED(2) indicates that the memory channel associated with bus line B, is at the "one" binary state, i.e.

LED(2) is illuminated, then, when the WRITE signal is present on line L62, this status may be maintained by keeping the programme switch SP, open. With switch SP, open. the integrated circuit 74125 (which is a tri-state buffer) receives a binary "one" signal from line L63 which it passes to line L60 via line L64 The status of line L64 remains unchanged.

Alternatively, with switch SP1 closed, a binary ''zero'' signal appears on line L63 and is passed via IC 74125 to line L64 and changes the binary status of line L60 to binary "zero',, thereby causing LED(2) to extinguishing indicating a binary ''zero'' status of the memory channel associated with bus line B,. It will be noted that switch SP1 is located in line L65 between lines L1 and L2 and that line L66 includes resistor R2, (1 K ohm).

The status of the tri-state buffers IC 74125 of all programmer channels P1 to Pr, associated with bus lines B, to B7 is determined by the READ/WRITE circuitry of Fig. 5A. WRITE/ READ switch S6 is arranged in line L67 which is between lines L1, L3 and includes resistor R23 (1 K ohm). Line 67 is connected by line 68 to input pin P6 of another integrated circuit 74121 (which is a one-shot monostable). Between line L66 and line L2, line L69 includes capacitor C7 which eliminates contact bounce effects from the switch S5.

The remaining pins of the IC 74121(3) are connected as follows: pin 2 is connected to line L70 which carries the READ/WRITE signal to the memory units on line A,2 of the bus bar; pins P7 and P7 are connected to by lines L7" L73 ground line L2; pins P14, P11 are connected by lines L73, L74 to line L, with Resistor R37 (10K ohms) in line L74; pins P9, P,O, are joined by line L75 which includes timing capacitor C8 (0.1 y farad).In addition, line L67 from pin P1 includes a buffer 7417 to ensure that the write signals on line 62 enable the tri-state buffer of IC 74125: buffer 7417 is an integrated circuit with an open collector output connected by line L1,6 including resistor R77 (1 K ohm) to line L,.

During normal working the LED(2) of each programme channel P, to P32 will indicate the state of its respect memory channel. Each individual LED(2) is illuminated for binary "one" and extinguished for binary "zero".

Each programme switch SP, is ''opened'' to write binary "one" and closed to write binary "zero". The settings of the switches SP, for all 32 programmer channels are written into the memory unit by pressing WRITE switch S5. Thus far described, the circuitry of Fig. 5A permits the first program step to be written into the memory unit.

In Fig. 5B there is shown the stepping circuitry of the programmer, which incorporates means for advancing the memory unit through the steps in a program, independently of the clock circuitry of Fig. 3A, in one of two modes, namely, "single step" manually controlled by switch S6 and "fast forward step" controlled by switch S7. In addition, this circuitry generates the strobe signal passed on bus line A16 and employed to disenable the clock pulses from Fig. 3A during stepping as mentioned above with reference to the description of the memory unit of Fig. 4.

The stepping pulses pass to the bus line A23via line L76 Switch S,. when closed, causes a single stepping pulse to be generated by the single shot monostable of integrated circuit 74121(4). Single stepping is used during the initial programming of a memory unit and when reprogramming individual steps to correct faults to locate the step to be corrected (probabiy after stepping by the "fast forward step switch S7).

The IC 74121(4) has pin P6 connected by line L77 to line L7g. Line L76 includes switch S6 and resistor R34 (1 K ohm) and is arranged between lines L1, L2; capacitor C9 (10 farad) is arranged in line L79 to eliminate contact bounce effects at switch S5. Pins P3 and P7 are connected by lines L89, L8, to line L2. Pin P6 is connected to line L76 by line L which includes resistor R25 (100 ohms). Pins P9 and P10 are connected by line L83 which includes timing capacitor C,O (1 p farad).Pin P1 is connected by line L54 which includes resistor R36 (10 K ohms) to line L,. Pin P14 is connected by line L85 to line L, Switch S7, when closed, causes integrated circuit 555(2), which is a timer circuit, to generate a clock signal continuously on line L76 to thereby rapidly step the memory unit forward e.g. at a rate of 10 steps per second.

Pin P3 is connected by line Li, which includes switch S7 to line L,5. Pins P1, P5 are connected to line L, by lines L87, L88; line L88 includes capacitor C., (0.1 p farad). Pin P is connected by line L89 to line Lg, and to pin P6.

Line L90 includes resistors R37, R28 (both 1 0K ohms) capacitor C12 (5 ,Lt farad) and extends between lines L1, L2 Pin P7 is connected by line Lg, to line L90 between resistors R27, R28.

Pins P4 and P5 are connected by line L92 to line L.

The strobe signal, for disenabling the memory outputs during stepping, is obtained by arranging both of switches S5, S7 as double switches. Thus switch S7 is connected by line L92 to line L1 and to line L94 from which Line L95 takes the strobe signal. Likewise switch S6 is connected by line L95 to line L and to line L94. Line L94 is connected to line L3 by line L97 which includes resistor R29 (1 K ohm). Each time, either switch S6 or switch S7 is depressed to step the memory unit, the strobe line L95 receives a pulse or a train of pulses of polarity for disenabling the memory unit during the stepping.

When Writing operations are performed, the strobe signal on line 76 travels via bus line A23 and via line 15 (of Fig. 3A) to pin P2 of IC 74121(1) (of Fig. 3A). This causes the binary counter of Fig. 3B to be stepped by the strobe pulses on line 76. Likewise, the Read/Write signal on line Las are transmitted along bus line A16 to the Write/Read line in the memory unit of Fig. 4. Binary signals of vlaue ''zero'' on line L2 cause the memory elements 21 12A (Fig. 4) to be placed in the WRITE only condition and binary signals of value "one" on line L95 cause the memory elements 2112A to be placed in the READ only condition.

THE ADDRESS DISPLAY As described above in relation to Fig. 4 the memory units are addressed in binary with signals from lines A3 to A9 of the bus bar: these signals are generated by the binary counter of Fig. 3B. These signals designate the step of the program which the memory unit is to output to bus lines B1 to B32.

In order that a visual indication is available of the number of the program step which is being outputted on lines B1 to B32, an Address Display is provided, the circuitry for which is shown in Fig. 6. Firstly, the binary signals from the bus lines A3 to A9 are received by the Address Display on lines L,02 to L109. Lines L,0s to L,O9 are directly coupled to pins P,, to P,4 of an integrated circuit 74185(1) which is a binary to binary coded decimal decoder.Likewise lines L103, L104 are directly connected to lines pins P,O, P" of a similar IC74185(2) which also receives at its pins P,2 to P14 the output of pins P, to P3 of the first IC 74185(1). Similarly, a third IC 74185(3) receives the output of pin P6 of IC 74185(2) at its pin P,0 and outputs from pins P4 to P6 of IC 74185(1) at its pins P" to P13.

By this arrangement Lines L102 to L1" which are connected respectively to pins P1 to P4 of IC 7447(1), pins P1 to P4 of IC 7447(2) and pins P, and P3 of IC7447(3) designate the BCD signals from the least significant digit (LSD) to the most significant digit (MSD).

Each IC 7447 is a BCD (binary coded decimal) to 7 segment decoder driver. Each IC 7447 (1) to (3) has seven output pins which are connected respectively by suitable resistive elements of components DIL/K (1) to (3) and from there to individually associated 7 segment light emitting diode (LED) display elements SLED (1) to (3) which give the visual indication of the binary count at the binary counter of Fig. 3B. Each of SLED (1) to (3) is connected in common mode by line L113 to positive line L1 (leading to bus line A1). Resistors R30, R31 (1 K ohm) by means of lines L113, L1,4 are connected from IC 7447 (3) to ground Line L3 (leading to bus line A37).

THE INTERFACE BUFFER UNIT In order to employ the binary signals outputted onto bus lines B, to B32 from the enabled memory unit, it is necessary to provide an Inerface Buffer unit, the circuitry for which is illustrated in Fig. 7. An interface buffer unit channel I1 is illustrated and the remaining interface buffer unit channels 12 to 133 are similar. Seven interface buffer unit channels I are contained in an integrated circuit which is commercially available. Input line L130 communicates with bus line B1. The binary signal on bus line Bi, which has the binary value "0" or "1", travels along line L120 via resistor R33 (2.5K ohnis). The circuitry also comprising transistors T1, T2, diodes D,, D2, D3 and resistors R33 (7K ohms) (R34 (3K ohms) buffers and inverts the signal on bus line B2. Output lines Lq2" L,22 are connected to line L,23 which includes the users load, for example a solenoid connected to an unregu lated 1 2 volt supply line L134. The user employs the outputs on lines L,2,, L,22 to control the load ON/OFF according to the binary status "1"/"0" line B,. The load may be any suitable device such as a solenoid which, in turn, will control an operating parameter.The diodes D, to D3 protect the circuitry against an inductive load and protect the signal on bus line B2. The transistors T1, T3 are arranged as a Darlington pair.

The interface buffer unit may be provided with an on/off switch in order that this unit does not respond to signals on bus lines B, to B32 during programming operations of the programmer of Figs. 5A and 5B: this ensures that the LOADS of Fig. 7 do not respond to the stepping of the programmer during programming operations which must result in undesired rapid control sequences being communicated to the equipment controlled through the LOADS.

Modifications to increase the number of memory units (and thereby the number of available programs) and/or the number of program steps will, as previously suggested, be readily apparent to those skilled in the art.

The integrated circuit components mentioned herein are all well known in the art.

National Semiconductor supply the 555 timers. INTEL supply the 211 2A memory elements. RCA supply the 401 7 counter. The Darlington drivers of the interface buffer units are available from RS Components. For the various other integrated circuits referred to under numbers 7400, 7404, 7417, 7442, 7447, 7493, 74121, 74125 and 74185, reference may be made to the product literature of Motorola Semiconductor Products Inc.

Claims (7)

1. A process controller for controlling a series of time related parameters comprising a plurality of memory units each with N memory channels and each channel storing M steps, a memory unit select circuit operable to select one of said memory units and thereby the program stored therein, a clock pulse circuit generating at least one clock pulse signal, whereby the time interval between steps of the memory unit is controlled, a binary counter stepped by the clock pulse circuit and generating a binary count for advancing the memory units through the program steps, and, an interface buffer unit having N channels operable to receive binary output signals from individually associated ones of the N memory channels and produce operation signals for controlling the ON/OFF condition of a process parameter.

2. A process controller as claimed in Claim 1 further comprising an Address Display permitting the user to obtain a visual indication of the count of the binary counter and thereby the program step which the process controller has reached.

3. A process controller as claimed in either Claim 1 or Claim 2, including a programmer unit which comprises a Read/Write circuit and N program channels each with a visual display for indicating the binary status "0"/"1" of that channel, switching means in each channel for use in program writing operations to set each channel to read the desired binary status "0"/"1" according to whether the parameter controlled by the associated memory channel is required to be "ON" /"OFF", and a WRITE switch for inputting the binary status of the program channels to the memory channels after the program channels are set.

4. A process controller as claimed in Claim 3, wherein the programmer unit includes a single step advance switch and a fast forward advance switch for advancing the binary counter during writing operations of the programmer.

5. A process controller as claimed in any one of Claims 1 to 4, wherein the memory units include means for selecting the time interval between program steps by selecting which of a plurality of clock signals, each with different time periods, is employed to enable that memory unit.

6. A process controller as claimed in any one of Claims 1 to 5, wherein there are 8 memory units M, to M5 for 8 programs, the number of memory channels N is 32 and the number of steps M in each program is 256 and eight clock signals have periods between 10 seconds and 80 seconds incremented by 10 seconds.

7. A process controller for controlling a series of time related parameters, arranged, constructed and adapted to operate substantially as herein described with reference to the accompanying drawings.