GB2070898A - PCM detector - Google Patents

Abstract

In a pulse code modulation (PCM) detector, an integrator integrates the central portion of each signaling interval of a PCM input signal for a time less than the reciprocal of the PCM baud rate. Means responsive to the integrated signal or a manifestation thereof performs a comparison operation at the end of the integration period and stores the result until the end of the next following period. The integrator is reset between integration periods when transitions of the signal are likely to occur, whereby immunity to PCM signal amplitude variations and transition edge distortion is enhanced and the probability that the integration will be monotonic is enhanced, thereby reducing the detector error rate. Preferably a change source provides a predetermined quantity of charge continuously or in discrete amounts to the integrator during the central portion of each PCM signaling interval.

Description

SPECIFICATION PCM detector This invention relates to detectors and particularly to synchronous pulse code modulation (PCM) detectors suitable for recovering digital data from a multilevel input signal. The invention is especially useful in video reproducer apparatus where time base errors may result in variation ofthe signal baud rate and where noise may also accompany the signal.

In Application No. 8032856 entitled "IMPROVED DIGITAL ON VIDEO RECORDING AND PLAYBACK SYSTEM" filed October 1980, it is proposed that digital data be recorded on a video disc during selected lines of the vertical blanking interval and that the data be recovered on playbackofthe disc for controlling various player functions such as program and playing time identification, locked groove identification and escape, record scanning, etc. PCM is a preferred means of encoding the digital data because (unlike Pulse Amplitude Modulation and Pulse Width Modulation) it is essentially a digital technique which facilitates error checking and correction ofthe recovered data.Non-return-to-zero PCM encoding, as well as synchronous transmission is preferred in order to maximize the data transmission rate within the relatively limited bandwidth available on the video disc.

In that Application, it is proposed that the PCM data be represented by the video signal level (e.g., luminance) and be sampled (detected) using the color subcarrier as a source of clock signals. By this means timebase errors which may be present in the luminance signal are also present in the clock signal (derived from chroma burst) and tend to offset each other. To illustrate the principle, if the baud rate of the data tended to vary (due, for example, to warpage or eccentricity of the record) the color burst frequency will vary in the same sense to that, in principle at least, the clock signal will always have a known time relationship with the data signal.This relationship holds true for players designed for variable speed turntables (the constant linear velocity type) and also for players designed for fixed turntable speeds (the constant angular velocity type).

In addition to providing a solution to the clock data synchronization problem mentioned above, Application No. 8032856 also shows a solution for minimizing a source of data errors caused by shifts in the d.c.

level of the video signal. The player shown utilizes buried subcarrier encoding of the chrominance signal, that is, the chrominance signal recorded on the disc is located or "buried" within the luminance band as taught by Pritchard in U.S. Patent 3,872,498 and is recovered upon playback by means of comb filtering as described in U.S. Patent 3,996,606 (also Pritchard). Also, in that application, it is shown that the horizontal line adjacent to the line containing data be of constant luminance level. Such an arrangement permits the use of a signal already available in the player, namely the chrominance related output of the comb filter, as the data signal.

Since the comb filter subtracts one line from an adjacent line the output is self referenced thereby substantially minimizing the probability of data errors caused by changes in the d.c. level of the video signal.

Detection of PCM data interleaved with analog data is a relatively difficult undertaking in cases where the transmission channel may be subject to noise, gain variations, d.c. level shifts, or other undesired signal pertubations. The PCM detector described herein is relatively immune to such problems and well suited for recovering data of the standard proposed in Application No. 8032856.

The present invention is directed to providing further advances in PCM video processing over those mentioned above. The invention resides in part in recognition that the transmission channels through which the data and the synchronizing signals pass may have different bandwidths, delays, etc., so that noise present in one channel may be of a different character than that present in another, that is, the cross correlation function between the data channel noise and the clock or synchronizing channel noise may be less than unity.

A second aspect of the invention resides in recognition of the disadvantages of conventional predetection and post detection integration type noise reduction techniques as applied to PCM data in which substantial leading and trailing edge distortion may occur owing, for example, to differences in signal channel and timing channel transmission characteristics.

Athird aspect of the invention resides in recognition that, in a video disc player of the type in which serial non-return-zero (NRZ) PCM data represented by amplitude levels of the video signal is synchronously detected by means of a clock signal derived from the color burst component of the video signal, the clock signal should not be phased so as to cause sampling of the anticipated center of the data signaling interval.

In accordance with the invention, a synchronous detector for recovering digital data from a PCM input signal comprises means for periodically integrating the input signal, the integration period taking place at a time other than one at which a transition of said PCM input signal is likely to occur and lasting for a period less than one signaling interval of the PCM input signal and means responsive to the integrated signal or a manifestation thereof for performing at least one comparison operation at the end of the integration period and storing the result until the end of the next following period.

More particularly, a current source produces an output current proportional to the difference between the instantaneous and average values of a composite signal which includes a serial PCM component interleaved (time division multiplexed) with an analog component. The current is integrated during a central portion of each signaling interval of the PCM component and the integrator is reset to a reference voltage level during initial and terminal portions of the signaling intervals.The process of integrating the signal advantageously enhances the immunity of the detector to PCM signal amplitude variations and resetting the integrator between integration periods where transitions of the signal are likely to occur rninim zes the edge., of transition edge distortion and incrn: < ~ babiiitythatsl;e integration will be mc .ot . .ic which which minimizes the deta-;-o: ror ra.-.a. . cutput data signal is then re @@@@ from the integrated signal by means of a threshold d spice having a threshold voltage level substantially equal to the reference voltage level to which the integrator is reset.This means of deriving an output signal from the integrator has an advantage in that it is readily adaptable for automatically cancelling the effect of drift or manufacturing tolerance variations.

As will be discussed in detail, subsequently, a PCM detector utilizing the principles of the invention offers substantially improved noise performance because data is integrated during periods between anticipated transitions where the effective signal to noise ratio is substantially peaked.

Of particular benefit is the increased probability that what is integrated will result in a monotonic change in the integrator output thereby greatly reducing detection uncertainty. Also, as will be explained, the invention may be applied to multilevel PCM transmission systems in which the bit rate is greater than the baud rate.

Under certain conditions, the detector may tend to exhibit a higher sensitivity for PCM data of a first signal level and a lower sensitivity for PCM data of a second signal level. This difference in sensitivities, when the signal is accompanied by noise or other pertubations, may result in an occasional failure to detect data present at the second level. This imbalance in detection sensitivity tends to occur in transmission systems where the average value of the composite signal is different from the average peakto-peak value of the PCM component signal. Illustratively, this condition may be encountered in video disc players where the data is encoded in a video signal in accordance with the standard proposed in Application No. 8032856, and the video signal is derived from the subtractive output of a comb filter prior to detection of the PCM component.In accordance with a feature of the invention, a compensator circuit is provided which supplies a charge to the integrator to compensate the imbalance in detection sensitivity.

In accordance with a further feature of the invention (particularly desirable in video disc players of the type shown in Application No. 8032856), further improvement in terms of bit error rate reduction may be facilitated by selective removal of the direct current component of the PCM signal. This provides the benefit of minimizing very low frequency perturbations not counteracted by the technique of transmitting a line of constant luminance level adjacent to the line containing data.

In accordance with yet another aspect of the invention, means are provided for resetting the integrator to a predetermined reference level between integration periods, said predetermined reference level being selected to be substantially equal to a decision threshold level associated with the comparison operation performing means which desirably includes means for storing the result of the comparison operation for a predetermined period of time.

Preferably, the predetermined period of time equals - ' - period ~ + - independent of the ratio bet- tre ine PCM signaling baud rate and the data bit rate. In the drawings: The invention is illustrated in the accompanying drawings wherein like reference numbers designate like elements and in which: FIGURE lisa block diagram, partially in schematic form, of a PCM detector embodying the invention interfaced with a video disc player for recovering digital data from a video signal component produced bythe player; FIGURE 2 is a diasi-am illustrating signal waveforms and timing relationships of the PCM detector of FIGURE 1, FIGURE 3 is a block diagram illustrating certain modifications of the detector of FIGURE 1.

FIGURE 4 is a block diagram, partially in schematic form, of a modified embodiment of a PCM detector interfaced with a video disc player for recovering digital data from a video signal component produced by the player; FIGURE 5 is a diagram illustrating signal waveforms; and timing relationships of the PCM detector of FIGURE 4; FIGURE 6 is a schematic diagram, partially in block form, of a portion of the detector of FIGURE 4 illustrating a preferred form of continuous charge compensation; and FIGURE 7 is a schematic diagram, partially in block form, of a portion of the detector of FIGURE 4 illustrating a form of discrete charge compensation.

The video disc player in FIGURE 1 comprises a turntable 10 for rotating video disc 12 and a pickup transducer 14 for recovering information signals from the disc. Illustratively, it will be assumed that the player is intended for use with records in which information is stored in the form of topological variations and recovered by sensing capacitance variations between pickup transducer 14 and the record 12. The output of transducer 14 is coupled to the input of a pickup converter circuit 16 which comprises a capacitance-to-voltage converter responsive to capacitance variations between a stylus in transducer 14 and the record being played for producing an FM output signal voltage representative of the record information. Such records and suitable circuits for implementing the capacitance-to-voltage conversion function of pickup circuit 16 are well known. See, for example, U.S. Patent 3,783,196 enti tled "HIGH-DENSITY CAPACITIVE INFORMATION RECORDS AND PLAYBACK APPARATUS THERE FOR" which issued to T. O. Stanley, January 1,1974; U.S. Patent 3,972,064 entitled "APPARATUS AND METHODS FOR PLAYBACK OR COLOR PIC TURESISOUND RECORDS" which issued to E. O.

Kiezer, July 1976, and U.S. Patent 3,711,641 entitled "VELOCITY ADJUSTING SYSTEM" which issued to R. C. Palmer, January 16, 1973.

Video FM demodulator circuit 18 converts the FM signal produced by pickup circuit 16 to a video output signal. For purposes of illustrating certain features of the invention, it will be assumed that the video signals recorded on the disc are in the previously mentioned "buried subcarrier" (BSC) format rather than the conventional NTSC format. An illustrative subcarrier frequency choice is in the vicinity of 1.53MHz, with the color subcarrier side bands extending t 500KHz thereabout and, with the luminance signal band extending well above the highest color subcarrier frequency (to 3MHz), for example). It will also be assumed that digital data is encoded in the video signal as proposed in the aforementioned Application No. 8032856.

FM demodulator 18 illustratively may be of the pulse counting type or of the phase-lock-loop (PLL) type. A suitable pulse counting type FM demodulator is disclosed in U.S. Patent 4,038,686 entitled "DEFECT DETECTION I AND COMPENSATION" which issued to A. L. Baker, July 26, 1977. An FM demodulator of the phase-lock-loop type is described in U.S. Patent 4,203,134, which issued May 13, 1980 to T. J. Christopher, et al. entitled "FM SIGNAL DEMODULATOR WITH DEFECT DETEC TION".

The composite video signal produced by FM demodulator 18 is converted from the BSC format to an NTSC format by video converter 20 (outlined in phantom). The BSC video signal is supplied to the input of delay line 22 and is summed with the output of delay line 22 by means of summation circuit 24 to thereby form a comb filter which separates the luminance component from the composite color video signal. The delay of delay line 22 is selected such that the luminance comb filter has frequency response characterized by multiple response peaks falling at even integral multiples at half the nominal horizontal line frequency and multiple rejection notches falling at odd integral multiples of half the nominal line frequency. Illustratively, a suitable delay would be equivalentto one horizontal scan interval.

The output of delay line 22 is subtracted from the BSC video signal by subtraction circuit 26 to thereby form another comb filter which passes the chrominance component of the composite video signal.

This chrominance comb filter has a frequency response characteristic having multiple peaks falling at odd integral multiples of half the nominal horizontal line frequency and multiple rejection notches falling at even integral multiples of half the normal line frequency.

Delay line 22 may be a conventional LC delay line, an acoustic delay line or preferably may be of a charge couple device (CCD) type. (See for example, the article byJ. Matob, entitled "CHARGE COUPLE DEVICE" which appeared in the January, 1975 issue of Wireless World). Further advantages and examples of comb filtering and video format conversion may be found in: U.S. Patent 3,872,498 entitled "COLOR INFORMATION TRANSLATING SYSTEM" which issued to D. H. Pritchard, March 18, 1975; U.S.

Patent 3,996,610 entitled "COMB FILTER APPARATUS FOR VIDEO PLAYBACK SYSTEMS" which issued to H. Kawamoto, December 7, 1976 and the U.S. Patent 4,195,309 to T. J. Christopher and L.

L. Trotter entitled "VIDEO PROCESSING SYSTEM INCLUDING COMB FILTERS" issued on March 25, 1980.

Since the frequency range of the luminance signal component in the BSC format is substantially the same as in the NTSC format, all that remains to provide a proper NTSC luminance output signal is to compensate for preemphasis which was performed in the recording process and to supplement the signal with information relating to vertical detail.

Supplementation is provided by coupling the output of summation circuit 24 to one input of a further summation circuit 28 via a cascade connection of delay element 30 and a low pass filter 32 and coupling the output of subtraction circuit 26 to the other input of summation circuit 28 via a low pass filter 34.

Suitable design parameters for the coupling elements would be: a delay of about 500n5ec. for delay element 30 (this compensates forthe delaythrough low pass filter 34); a passband of O-SMHz for low pass filter 32; and a passband of 0-500KHz for low pass filter 34. Compensation of preemphasis is provided by coupling the output of summation circuit 28 to the input of deemphasis circuit 36 which preferably has a transfer characteristic complementary to that of the preemphasis circuit used in the recording process.

The output of subtraction circuit 26 contains both low frequency luminance information (which is passed by low pass filter 34 for supplementing vertical detail of the luminance signal as previously mentioned) and the chrominance signal in BSC format.

The low frequency information is rejected by connecting the output of subtraction circuit 26 to the input of bandpass filter 38 which preferably has a passband of about 1MHz centered at the BSC frequency of nominally 1.53MHz.

Since the frequency range of the chrominance signal in the BSC format (nominally 1.53MHz) is lower than its range in the NTSC format (nominally 3.58MHz), up-conversion of the output signal of bandpass filter 38 is necessary before the chrominance and luminance signals may be added (in summation circuit 40) to produce an NTSC composite video signal. This frequency translation is provided by voltage controlled oscillator (VCO) 42, mul tipl ier 44 and bandpass filter 46. The output frequency of VCO 42 (when at the center of its control range) is nominally 5.11MHz. Accordingly, multiplier 44, which mixes or multiplies the BSC chrominance signal produced at the output of bandpass filter 38 with the output of VCO 42, produces output signals of nominally 3.58 and 6.64MHz.Bandpass filter 46 passes the lower frequency signal (which corresponds to the NTSC chrominance signal standard) to summation circuit 40 where it is summed with the NTSC luminance signal produced at the output of deemphasis circuit 36 to thereby provide a composite video output signal in the NTSC format from the video disc player.

Multiplier 44 and band pass filter 46 may be of conventional design. It is desirable, however, that VCO 42 feature high stability and be capable of wide frequency deviation. A preferred voltage controlled oscillator having a wide deviation range, is disclosed in Application No.8019873 filed 18th June 1cm80 and entitled "VARIABLE FREQUENCY OSCILLATOR".

VCO 42, in addition to providing a source of signal for up-conversion of the chrominance signal to NTSC standard, also provides timebase error correction of the converted signal. TErn- base errors are detected by means of phase detector 50 which com pares thg frequency .. rd phase of the color burst com; - nt of the chrominance signal produced at the outpu of bandpass filter 46 with the standard NTSC reference frequency (3.579545MHz) produced by a reference oscillator 52 and supplies an error voltage to VCO 42 via a filter 56 thereby completing a phase-lock-loop which varies the frequency of VCO 42 in a sense to minimize errors in the up-converted NTSC chrominance signal.Phase detector 50 is keyed during the color burst interval by means of a burst key generator 58 which is triggered by means of a sync detector 59 which detects horizontal synchronizing pulses present in the luminance signal at the output of deomphasis circuit 36.

PCM detector 60 comprises a multiplier 62 which is interfaced with video converter 20 by coupling one input of the multiplier to the output of VCO 42 and the other multiplier input to the output of reference oscillator 52. By this means the same phase-lockloop which provides timebase correction in video converter 2Q serves a dual function as a source of continuous clock signals at the buried subcarrier frequency (1.53MHz) and these clock signals exhibit timebase errors in proportion to the timebase errors present in the pulse code modulated signal at the output of subtraction circuit 26.

The output signal of multiplier 62 includes sum and difference frequencies of 1.53MHz and 6.64MHz.

The lower frequency signal is coupled to a clock output terminal 64 by means of a cascade connection of a bandpass filter 66 and a phase adjusting circuit 68.

The purpose of circuit 68 is to set the phase of the output clock signal in quadrature with the phase of the buried subcarrier chrominance signal reproduced from the disc. Illustratively, circuit 68 may be an all pass network. Alternatively, the phase shift may be provided by a suitable lead or lag network in combination with a limiter or by means of a suitable delay line.

The signal produced at the output of subtraction circuit 26 is applied to the input of an inverting amplifier 70 in PCM detector 60 by means of series connection of a d.c. blocking capacitor 72 and a current limiting resistor 74. A feedback circuit comprising a parallel connection of an integrating capacitor 76 and an integrator reset switch 78 is coupled between the input and output terminals of amplifier 70.

Switch 78 may be conventional bipolar or field effect transistor transmission gate. The output of amplifier 70 is applied to the data input (D) of a D-type flip-flop 80 which has a true output terminal (Q) connected to data output terminal 82. The output signal from phase adjuster 68 is coupled to a control input terminal of switch 78 and to a clock input terminal (CL) of flip-flop 80 for supplying a quadrature phase clock signal thereto. For purpose of discussion, it will be assumed that flip-flop 80 is of the positive edge triggered type and that switch 78 is of a type which closes in responsive to positive (high) control signal levels.

Flip-flop 80 performs dual functions of comparing the output of the integrator formed by amplifier 70 and capacitor 76 w'th a threshold voltage and stor ing the result of ti - comparison operation. To facili- faae tis it is preferably that amplifier 70 be of a type which exhibits a quiescent d.c. output voltage when switch 78 is closed which is substantially equal to the logic decision threshold level at the data input of flip-flop 80. Amplifier70 and flip-flop 80 may be, for example, complementary metal oxide semiconductor (C-MOS) integrated circuits. The threshold voltage of C-MOS circuits is nominally equal to about halfthe supply voltage but has been found to be subject to some variance from chip to chip.The effect of this variation for devices integrated on a common substrate has been found to be minimal insofar as operation of the present invention is concerned and so it is preferable that amplifier 70 and flip-flop 80 be integrated on the same substrate. The threshold turn-on voltage of swich 80 (e.g., a C-MOS transmission gate) is not critical insofar as detection of the integrator output is concerned and so switch 78 may be on the same integrated circuit as amplifier 70 and flip-flop 80 or externally connected to it.

In operation, switch 78 is closed in response to the quadrature clock signal during the initial and terminal portions of each PCM signaling interval and opened during the central portions of each signaling interval. Upon each closure of switch 78 flip-flop 80 is clocked whereby the output of the data integrator (70, 76) is compared with the threshold voltage of flip-flop 80 and the result stored.

FIGURE 2 illustrates operation of the detector during four consecutive signaling intervals (waveform A, intervals 1,2,3 and 4) for an assumed data message 1-0-0-1 (waveform B). Illustratively the message is represented by luminance level variations of nominally 100 IRE units (waveform E) and it is assumed that the luminance signal exhibits edge distortion during transition intervals. The uncertainty as to the luminance transitions is indicated by dashed lines in waveform E. Waveform C represents the output of band pass filter 66 which is a signal in phase with the data signaling intervals. Waveform D is the output of phase adjuster 68 which is in phase quadrature with waveform C.

During the initial portion (ta-tr ) and the terminal portion (t3-t4) of the first signaling interval, waveform D is high whereby switch 78 is closed. This causes amplifier 70 to be self biased at the data threshold level of flip-flop 80 and maintains capacitor 76 in a discharged condition. During the central portion (t,-t3) of the first signaling interval waveform D is low whereby switch 78 is opened and capacitor 76 is charged in a positive sense (waveform F). When waveform D makes a positive transistion (t) switch 78 closes thereby resetting the integrator (discharging capacitor76) and vimultaneously clocking flipflop 80. Since the integrator output (F) was positive relative to the threshold of flip-flop 80 at the time the waveform D positive transition took place a logic 1 will be latched in flip-flop 80. Since flip-flop 80 is only responsive to positive clock transitions (as assumed) the stored data will remain at the flip-flop output for a time equal to one signaling interval in length and will be delayed by a time equal to three quarters of a signaling interval (waveform G).

As illustrated in waveform F, integration of the luminance signal takes place only during the central portion of each signaling interval. This is where transitions of the signal are least likely to occur and where the signal to noise ratio is maximal. The integrator is effectively disabled during the initial and terminal portions of each of the signaling intervals where transitions are most likely to occur and so distortion of the signal during those times is effectively rejected.

FIGURE 3 illustrates a modification of the invention for providing integration by means of an updown counter 89. The counter is supplied with a high frequency clock signal by means of an oscillator 92 and the direction of count (up or down) is controlled by applying the PCM input signal to its UP/DOWN control input (U/D). Preferably the up/down logic threshold of counter 89 equals one half of the peakto-peak luminance signal swing for digital data.

Alternatively the luminance signal may be detected by means of a comparator biased at the equivalent of 50 IRE units (for data recorded as 0-100 IRE units) and the detector output used to control the direction of count The most significant bit of the counter is applied to the data input of flip-flop 80 which is clocked by the quadrature clock signal as in FIGURE 1. In order to insure that the data input to flip-flop 80 does not change at the time the quadrature clock positive transition occurs the clock signal is coupled to the counter reset terminal (R) input via a delay element 94.

Operation of the example of FIGURE 3 is similar two that of FIGURE 1. An exception is that "integration" of the PCM signal is performed by the counter rather than by a capacitor. The counter is reset to zero each time waveform D is high and counts up or down depending on the level of the PCM (luminance) signal when waveform D is low. If the total count is positive at the end of an "integration" period the most significant bit (MSB) will be logic zero and the flip-flop will reset by the positive transition of the quadrature clock signal. Thisassumesthatthe number of counter stages and the frequency of oscillator 92 are selected such that the counter capacity is not exceeded (i.e., there is no carry to or borrow from the MSB stage) during the time the counter is enabled.For a negative total count the MSB will be a logic "1" at the end of an integration or counting period so that flip-flop 80 will be reset. To recover non-inverted output data the counter output (MSB) may be inverted prior to application to flip-flop 80 or the complemented (Q) output of the flip-flop may be used rather than its true (Q) output.

In Figure 4, wherein like numbered elements are as shown and described in Figure 1, the signal produced atthe output of subtraction circuit 26 is coupled to the input 71 of an inverting amplifier 73 which has an output coupled via a d.c. blocking capacitor 77 to the summing node 75 of a resettable integrator. Capacitor 77, in addition to providing d.c.

blocking (which minimizes effects of drift and low frequency noise components) serve a dual purpose in combination with amplifier 73 of acting as a current source for supplying current to node 75 proportional to a difference between the instantaneous and average values of the signal produced at the output of subtraction circuit 26. Preferably, the time constant (i.e., R-C product) formed by the amplifier output impedance and the value of capacitor 77 is very much longer than several PCM data signaling intervals so that the average voltage across capacitor 77 is relatively constant and reflective of the average "vertical detail" signal level. A suitable time constant would be about one millisecond for a PCM signaling rate of about 1.53 Megabaud.

The resettable integrator comprises an integrating capacitor79 coupled between summing node 75 and a point of reference potential (ground), an inverting amplifier 70 having an input coupled to node 75 and a reset switch 78 connected between the amplifier input and output terminals and controlled by the quadrature clock signal produced at the output of phase adjusting circuit 68. The grounded plate of capacitor 79 may, alternatively, be coupled to the output of amplifier 70 to enhance integration linearity if desired. It is advantageous to connect the capacitor 79 as shown, however, in cases where the output of amplifier 70 is an internal node in an integrated circuit.This avoids the need for accessing the internal node and, therefore, may be used to advantage for either reducing the integrated circuit package pin count or for making an extra pin available in a package with a given pin count. Switch 78 may be a conventional bipolar or field effect transistor transmission gate.

The integration time constant of the rosettablo integrator should be selected to be not less than one half of one signaling interval of the PCM signal to avoid saturation and should be substantially less than the previously mentioned time constant of the differential current source (73,77). A suitable value (again considering a 1.53 megabaud data rate) would be on the order to one microsecond which is greater than one but less than two signaling intervals in length. The integration time constant where one plate of capacitor 79 is grounded as shown may be approximated by the product of the output impe- dance of amplifier 73 and the value of capacitor 79.

The output signal of amplifier 70 is applied to the data input terminal (D) of a D-type flip-flop 80 which has a true output terminal (Q) connected to data output terminal 82. The output signal from phase adjuster 68 is coupled to a clock input terminal (CL) of flip-flop 80 for supplying the quadrature phase clock signal thereto. For purposes of discussion, it will be assumed that flip-flop 80 is of the positive edge triggered type and that switch 78 is of a type which closes in response to positive (high) control signal levels.

Flip-flop 80 performs dual functions of comparing the output of the integrator formed by amplifier 70 capacitor 79 and switch 78 with a threshold voltage and storing the result of the comparison operation.

As previously described, to facilitate this it is preferably that amplifier 70 be of a type which exhibits a quiescent d.c. output voltage when switch 78 is closed which is substantially equal to the logic deci sionthreshold level atthe data input of flip-flop 80.

Therefore again, amplifier 70 and flip-flop 80 may be, for example, complementarSJ metal oxide semicon ductor (C-MOS) integrated circuits.

As shown in Figure 4, ds :ec; Ir ~., includes a compensator circuit 9û avr nc 3 l output line connected te node 75 of the in > ~- . ator for equalizing integrator outp . c tage excursions relative to the detection threshold revel at the data input of flip-flop 80 in cases where the PCM data is encoded in accordance with the standard shown in Application No. 8032856.

Compensator 90 comprises a charge source mains for supplying a predetermined quantity of charge to node 75 of the integrator (79,70,78) each time switch 78 is open. The charge is supplied in a sense to augment the current supplied to node 75 via the current source (amplifier 73 and capacitor 77) when the PCM component of the signal produced at the output of subtraction circuit 26 is at a level closer to an average value of the circuit 26 output signal and to oppose the output current of circuit 26 when the PCM signal level is farther from said average value.

Suitable circuits for implementing this function are given in FIGURES 6 and 7 and discussed subsequently.

The waveforms of FIGURE 5 provide further illustration of the operation of the embodiment of the invention of Figure 4. It will be assumed in the following discussion that disc 12 is encoded with PCM data in accordance with the previously mentioned standard proposed in Application No.8032856.

Three parameters of the standard important to an understanding of operation of the specific example of FIGURE 4 are: (1) the PCM data is represented by luminance variations between two levels; (2) each line of data is recorded adjacent to a line of constant luminance; and (3) the line of constant luminance is of a level closer to one of the PCM levels than the other and differs from an average of the luminance signal taken over a number of successive lines.To simplify the discussion it will be assumed that a PCM logic "1" corresponds to a luminance level of 100 IRE units, that a PCM logic "0" corresponds to a luminance level of0 IRE units, that the line of constant luminance corresponds to a level ofO IRE units and that the average luminance level taken over a number of successive lines is about 50 IRE units.

This average, of course, depends upon picture constant and this will vary, but, an assumed value of 50 units is not unrealistic and serves to illustrate the principles involved.

Upon playback of disc 12, the player pickup transducer 14, pickup circuits 16, FM demodulator 18 and video converter 20 function as previously described for producing an NTSC standard signal at the output of summation circuit 40 as previously described. The digital control signal code occurs during a selected line of the vertical blanking interval and will be assumed to follow the line of constant (blanking level) luminance. The comb filter formed by delay line 22 and subtraction circuit 26 will supply a signal to amplifier 73 whose average level (average taken over a 1 millisecond period) is substantially constant despite any variation in the (1 msec.) average amp litude of the buried subcarriervideo signal (which can vary between 0 and 100 IRE units).This results because circuit 26 subtracts each horizontal line from the previous line causing each line's luminance values to be both added and subtracted in the avr .:.r.g process. - :Jsing any variations to cancel.

'Sji-:cs input of ampiifier 73 has a substantially constant value (zero IRE units), capacitor 77 will be charged to a voltage love equal to the difference between the average output voltage of amplifier 73 and the average voltage at integration node 75. This latter voltage will have an average (over 1 msec.) value equal to the threshold voltage of amplifier 70 (a CMOS inverter) due to a periodic closure of switch 78 which self biases amplifier 70 to its logic threshold voltage once each half period of the quadrature clock signal and thereby sets the integration node 75 to said logic threshold voltage.

Because the average output voltage of amplifier 73 is constant and the average voltage at integration node 75 is also constant, the charge accumulated on capacitor 77 may be considered to be of constant value so that any instantaneous value of luminance level different from the assumed average will cause amplifier 73 to supply current to or withdraw current from integration node 75 via d.c. blocking capacitor 77. The voltage on capacitor 77, in other words, cannot change instantaneously and therefore, luminance related current which changes at a rate faster than the previously mentioned capacitor 77 amplifier 73 time constant (one millisecond) is coupled to the integration node.Stated another way, capacitor 77 functions in one sense as an integrator for accumulating a charge proportional to the average luminance level (zero IRE units) and in another sense (in combination with amplifier73) as a differentiator for supplying current to (or withdrawing current from) node 75 depending on whether the instantaneous value of the luminance signal is above or belowthe average value. The significance of the charging of capacitor 77 to a voltage level representative of an average luminance level of zero IRE units is, as will now be explained in detail, that the variations of the PCM modulated luminance signal are not symmetrical with respect to zero IRE units and this asymmetry causes amplifier 73 to supply a greater magnitude of current to the integrator for one data logic level than the other.This in turn can cause the integrator output voltage (inverted) atthe output of amplifier 70 to be asymmetrical with respect to the logic decision threshold level at the data input terminal of flip-flop 80. Asymmetry at the point when coupled with noise or other signal perturbations, can result in occasional failure of detector 60 to detect one or more code bits. To avoid this, compensator circuit 90 supplies a symmetry correcting charge to integration node 75 when switch 78 is opened during the central portion of each data signaling interval.

FIGURE 5 illustrates two modes of operation of detector 60, one in which compensator 90 supplies a continuous symmetry correction charge to node 75, the other in which the charge is supplied intermittently. Waveform A signifies three consecutive signaling intervals (1,2 and 3) of one line of the PCM code for an assumed data message of 1-0-0 (waveform B). Waveform C illustrates the luminance level variation at the output of subtraction circuit 26.

Note that since the line containing the message is preceded by a line of blanking level luminance (0 IRE units) the output of subtraction circuit 26 is exactly equal to its input and varies between 100 IRE units for a data logic "1" (signaling interval 1 ) and 0 IRE units for a data logic "0" signaling intervals 2 and 3).

Note also that the average value of luminance taken over the previous several lines is at or close toO IRE units as previously explained. As a result of this difference between instantaneous and average values of luminance at the subtractive output of the comb filter (22, 26), a greater current is withdrawn from integrator node 75 from a PCM logic "1" state than is supplied to node 75 for a logic "0" state (ignoring, for the moment, compensator90).

Waveform D illustrates the quadrature clock signal produced at the output of phase adjuster 68 which is 90 degrees out of phase with the PCM signaling intervals (waveform A). During the initial portion (to,) and the terminal portion (t3-t4) of the first signaling interval, waveform D is high whereby switch 78 is closed. This completes a negative feedback path around amplifier 70 which self biases the amplifier (C-MOS as assumed) at a level or nominally half its supply voltage and resets the integrator. During the central portion (t,-t3) of the first signaling interval, when the clock signal is low, switch 78 is opened so that the integrator is enabled and capacitor 79 is charged in a negative sense by current supplied to node 75 from amplifier 73.

Waveform E illustrates a component of the node 75 voltage due solely to the luminance related current As shown, the negative peak value of this voltage during the first signaling interval for a logic "1" data state is substantially greater than the positive peak values occurring during signaling intervals 2 and 3 when the PCM data is at logic "0". This results because during the first signaling interval the instantaneous value of the luminance signal is nearly 100 IRE units above the average value whereas during intervals 2 and 3 it is nearly equal to the average value. For purposes of discussion, positive peaks are illustrated as being slightly greater than the average value; if they equaled the average value the integral would be zero and the data would not be detected.

As a practical matter, of course, some data would always be detected due to shifts in the average luminance level which depends upon picture content.

Waveforms F and G illustrate the node 75 voltage for two modes of operation of symmetry compensator 90. In waveform F compensator 90 continu- ously supplies charge to node 75 in a sense to oppose the current produced by amplifier 73 when the PCM data is at logic "1" and to aid the current produced by amplifier 73 when the PCM data is at logic "0". Waveform G is similar to F except that rather than the charge being continuously supplied (e.g., via a constant current source) it is supplied intermittently in discrete amounts (e.g., via a charge pump) at the beginning of each integration period. It could, alternatively be supplied at any time within the integration period priorto a positive transition of waveform D where the integrator output is sampled and stored by means of flip-flop 80.

Waveform H illustrates the detector output signal atterminal 82. Each time waveform D makes a positive transition (t3, t11) switch 78 closes thereby resetting the integrator and simultaneously clocking flip-fiop 80. Since the integrator node 75 is negative at time t3 the amplifier 70 output will be high relative to the threshold of flip-flop 80 so the flip-flop will be set and produce a logic "1" at its true output (Q) which corresponds to the value of the data during signaling interval 1.Operation is similar during intervals 2 and 3 except that the PCM data is at logic zero and the flip-flop is reset and produces a logic zero at its output Since the flip-flop is only responsive to positive clock transitions (assumed), the stored data will remain at the flip-flop output for a time equal to one signaling interval in length and will be delayed by a time equal to three quarters of a signaling interval (waveform H).

As illustrated in waveforms F and G, integration of the luminance signal takes place only during the central portion of each signaling interval. This is where transitions of the signal are least likely to occur (indicated by dashed lines in waveform C) and where the signal to noise ratio is maximal. The integrator is effectively disabled during the initial and terminal portions of each of the signaling intervals where transitions are most likely to occur and so distortion of the signal during those times is effectively rejected.

In FIGURE 6, amplifier 73 is implemented by means of an NPN transitor Q1 operated in common emitter configuration. The ratio of the collector load resistor R2 and the emitter degeneration resistor R1 determines the amplifier gain. The collector load resistor also determines the amplifier output impedance which should be selected with regard to the values of d.c. blocking capacitor 77 and integration capacitor 79 to provide the aforementioned two widely spaced time constants. Amplifier 70 comprises N channel (02) and P channel (Q3) field effect transitors arranged as a CMOS inverter. Switch 78 is a CMOS transmission gate connected between the gate and drain electrodes of transistors Q2 and Q3.

Compensator 90 comprises a resistor R3 which in this case is connected between a supply voltage source +V1 which is more positive than one half of the supply voltage +V2 of the CMOS converter, so as to continuously supply current to node 75. In operation, a PCM logic "1" level causes the collector voltage of Q1 to decrease substantially whereas a logic "0" causes little change. The charge added to capacitor 79 via resistor R3 when gate 78 is open equalizes the node 75 voltage changes for the different logic states as shown in waveform F of FIGURE 5.

The value of R3 should be chosen such that a voltage differential of +V1 minus the logic threshold voltage of inverter 70 will produce a current flow through R3 substantially equal to half the current flow through capacitor 77 when an input signal equal to 100 IRE units greater than average is present at the input of amplifier 73.

FIGURE 7 is similar to FIGURE 6 except that compensator 90 is implemented by means of a discrete charge source (pump) rather than a continuous current source. The charge pump comprises an converter 91 responsive to the quadrature clock signal for causing capacitor 95 to accumulate charge via diode 93 from supply V3 during the initial or terminal por tionsofeach signaling interval. Inverter 91 then causes capacitor 95 to discharge into capacitor 79 via diode 97 during the central portion of each signaling interval {waveform; ; time t, tS, tgj. The quantity and sense '- r the charge transfer should be selected as previously explained to equalize the peak-to-peak values of the integral of the PCM signal relative to the threshold of flip-flop 80.

Claims (8)

1. A PCM detector for use in video reproducer apparatus of the type in which digital data is represented by serial synchronous pulse code modulation of a video signal produced by said apparatus and synchronously detected by means of a color burst component of said video signal, said video signal tending to exhibit leading and trailing edge distortion, said detector comprising: oscillator means responsive to said color burst component of said video signal for producing a reference signal of predetermined phase relative to signaling intervals of said pulse code modulated video signal; phase shifting means responsive to said reference signal for producing a clock signal in phase quadrature with said signaling intervals of said pulse code modulated video signal; integrator means having an input terminal for receiving said pulse code modulated video signal and an output terminal for providing an integrated output signal; control means responsive to said clock signal and coupled to said integrator means for enabling said integrator means when said clock signal is of a first value during the central portion of each signaling interval and for resetting said integrator means when said clock signal is of a second value during initial and terminal portions of each signaling interval; and output means responsive to transitions of said clock signal and to said integrated output signal for detecting said digital data corresponding to said pulse code modulated video signal at the end of each integration period and for storing said digital data until the end of the next integration period to produce a pulse code modulated digital data output signal having reduced leading and trailing edge distortion.

2. A PCM detector as recited in Claim 1 wherein said color burst component of said video signal is subject to timebase errors and wherein said oscillator means includes means for varying said reference signal in accordance with said timebase errors.

3. A PCM detector as recited in Claim 1 wherein said color burst component of said video signal is of a frequency different from that of said reference signal and is subject to timebase errors and wherein said oscillator means includes means for translating the frequency of said color burst component to that of said reference signal and for imparting timebase errors to said reference signal in accordance with the timebase errors of said color burst component.

4. A PCM detector as recited in Claim 1,2 or 3, wherein said output means comprises bistable means having a data input terminal coupled to an output terminal of said integrator means, a clock terminal coupled to receive said clock signal and an output terminal for providing said digital data output signal.

5. A PCM detector as recited in Claim 4 wherein said bistable means is of a type having a threshold YOELa9 a at said da: :r put terminal lying within a preuetermined range of values, and wherein said integrator means includes an amplifier of a type having a quiescent output voltage when biased by negative feedback which lies within said predetermined range of values.

6. A PCM detector as recited in any preceding Claim wherein said integrator means includes a charge source having resistive means connected between a point of fixed reference voltage and a summing node in said integrator means to which said PCM video signal is coupled, said resistive means continuously supplying current to said node.

7. A PCM detector as recited in any preceding Claim wherein said integrator means includes a charge source comprising charge pump means for accumulating a predetermined charge when said integrator means is in said reset mode and for supplying the accumulated predetermined charge to a summing node in said integrator means to which said PCM video signal is connected when said integrator means is in said enabled mode.

8. A PCM detector substantially as hereinbefore described with reference to any of the embodiments illustrated in the accompanying drawings.