GB2069785B - Ratioless logic circuit - Google Patents

Ratioless logic circuit

Info

Publication number
GB2069785B
GB2069785B GB8004687A GB8004687A GB2069785B GB 2069785 B GB2069785 B GB 2069785B GB 8004687 A GB8004687 A GB 8004687A GB 8004687 A GB8004687 A GB 8004687A GB 2069785 B GB2069785 B GB 2069785B
Authority
GB
United Kingdom
Prior art keywords
logic circuit
ratioless
ratioless logic
circuit
logic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB8004687A
Other versions
GB2069785A (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Philips Electronics UK Ltd
Original Assignee
Philips Electronic and Associated Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Electronic and Associated Industries Ltd filed Critical Philips Electronic and Associated Industries Ltd
Priority to GB8004687A priority Critical patent/GB2069785B/en
Publication of GB2069785A publication Critical patent/GB2069785A/en
Application granted granted Critical
Publication of GB2069785B publication Critical patent/GB2069785B/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/501—Half or full adders, i.e. basic adder cells for one denomination
    • G06F7/503—Half or full adders, i.e. basic adder cells for one denomination using carry switching, i.e. the incoming carry being connected directly, or only via an inverter, to the carry output under control of a carry propagate signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/096—Synchronous circuits, i.e. using clock signals
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/386—Special constructional features
    • G06F2207/3872—Precharge of output to prevent leakage

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Computational Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Optimization (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
GB8004687A 1980-02-12 1980-02-12 Ratioless logic circuit Expired GB2069785B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB8004687A GB2069785B (en) 1980-02-12 1980-02-12 Ratioless logic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB8004687A GB2069785B (en) 1980-02-12 1980-02-12 Ratioless logic circuit

Publications (2)

Publication Number Publication Date
GB2069785A GB2069785A (en) 1981-08-26
GB2069785B true GB2069785B (en) 1983-09-01

Family

ID=10511296

Family Applications (1)

Application Number Title Priority Date Filing Date
GB8004687A Expired GB2069785B (en) 1980-02-12 1980-02-12 Ratioless logic circuit

Country Status (1)

Country Link
GB (1) GB2069785B (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07104774B2 (en) * 1985-11-26 1995-11-13 株式会社東芝 Synchronous arithmetic circuit
JP3110221B2 (en) * 1993-10-04 2000-11-20 株式会社東芝 Full adder circuit

Also Published As

Publication number Publication date
GB2069785A (en) 1981-08-26

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Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee