GB2069785A - Ratioless logic circuit - Google Patents

Abstract

A multiphase phase ratioless logic circuit which can be fabricated from a family of three basic types of circuit elements, or sticks, with an optional fourth type producing a complementary output of the third type. D type flip-flops and binary adders may be fabricated. In a D-type flip-flop (Figure 3), one of each type of sticks is used, comprising a logic array (10, 18, 20 and 22), a precharging MOS transistor (T1, T3, T5, T7) connected to a VDD rail (14) and a sampling MOS transistor (T2, T4, T6 and T8). Each logic array may be different, and perform some more complex function. Each stick output is derived from the source of its respective precharging transistor (T1, T3, T5, T7). An output node (12) of a first type of stick is connected to the logic array (18) of the second type of stick via a transfer and store (TAS) gate (T16) and the output (24) of the second type of stick is connected to the logic array (20) of the third type of stick by way of another TAS gate (T18). A sequence of four non-coincident clock signals K1, K2, K3 and K4 is supplied to the sampling transistors (T2, T4, T6 and T8) of the first, second, third and fourth types of sticks, respectively to read out the outputs of their logic arrays. Precharging transistors (T1, T3, T5 and T7) are also clocked prior to their associated sampling transistors (T2, T4, T6 and T8) to precharge the output nodes (12, 24, 26 and 28). When the sampling transistors (T6, T8) of the third and fourth types of stick, are conductive and one or other logic array output (26 or 28) is "low", then that output is clamped at the VSS rail (16) voltage to provide a reliable "low". (Figures 3 and 4). <IMAGE>

Description

SPECIFICATION Ratioless logic circuit The present invention relates to a family of 4 phase metal oxide semiconductor (MOS) ratioless logic circuits which can be constructed from a number of standard modules otherwise known as sticks. Such logic circuits include a Dtypeflip-flop and an adder, both of which may be used in arithmetic or logic circuits, for example telephone exchange CODECS where low power consumption is important.

According to the present invention there is provided a ratioless logic circuit comprising first, second and third types of stick, each stick including a precharging MOS transistor, a sampling MOS transistor and a logic array coupled between voltage supply rails, an input coupled to the logic array and an output derived from the source of the precharging transistor, the precharging and sampling transistors of each stick, in use, being clocked so that only one or other transistor is conductive at any one time, and a transfer and store (TAS) gate coupled to the output of each stick of the first and second type.

The present invention also provides a ratioless logic circuit comprising one or more sticks of a first and second type and a stick of a third type, each type of stick comprising a precharging MOS transistor, a sampling MOS transistor and a logic array, an input to the logic array and an output derived from the source of the precharging transistor, transfer and store (TAS) gates for coupling respectively the output of each stick of the first and second types to the input of an associated stick of the second and third types, the TAS gate being clocked in synchronism with the sampling transistor of the stick to whose output it is connected, and means for providing first, second and third clock pulses of which the first clock pulses are supplied to the samping transistor of the or each first type of stick, the second clock pulses, which do not overlap the first clock pulses, are supplied to the sampling transistor of the or each second type of stick and the third clock pulses, which do not overlap the second clock pulses and rise before and overlap the first clock pulses, are supplied to the sam ping transistor of the third type of stick.

In a simple embodiment of the invention the logic array of a stick may be an inverter. In other embodiments the logic array may comprise a NAND, NOR, AND, OR or an EXCLUSIVE OR, a NOR gate or some more complex function.

If it is desired to invert the output from the third type of stick, a fourth inverting type of stick may be used, its input being connected directly to the output of the third type of stick. The fourth type of stick comprises a precharging MOS transistor and a sampling MOS transistor which are so clocked that they are not conductive atthe same time.

A logic circuit is disclosed in British Patent Specification No. 1,434,771 (corresponding to United States Patent Specification 3,917,958), this circuit which uses metal insulated gate field effect transistors (Misfets) comprises a number of sticks each having a depletion transistor connected as a load, a logic block and an enhancement transistor which is connected to a clock pulse source and serves as a current limiting transistor. In certain embodiments, for example Figure 3, the sticks are arranged alternately so that the output of one stick is connected to an input of the next stick by an enhancement Misfet operating as a transfer gate and also instead of each stick having a separate current limiting enhancement transistor, all the odd numbered sticks have a common enhancement transistor as does the even numbered sticks.In operation the odd numbered sticks and the transfer gates connected to their outputs are closed together so that the logic state of the odd number sticks is transferred by charge sharing to the inputs of the respective even numbered sticks, the current limiting transistor of which in a following period, is clocked simultaneously with the transfer gates connected to the outputs of the even numbered sticks to shift their logic condition to the inputs of the respective odd numbered sticks. It is stated in this prior art specification that it is difficult to adopt a clock drive system for use with depletion transistors and hence the depletion transistors are connected as loads.A disadvantage of this is that when the enhancement transistor of the or each stick is clocked then there is a direct current path through the logic block from one supply rail to the other and consequently the current drain is higher than in the logic circuit of the present invention which does have a clock drive system for the precharging transistor in each stick. Further in the circuit in accordance with the present invention, the phases of the clock pulses for the precharging and sampling transistors of each stick are such that both are not conductive at the same time and thereby there is no direct current path through the or each stick. Hence the current consumption is less than in the prior art current.

In the circuit in accordance with the present invention each transfer and storage gate may have a kick-up capacitance which enables the logical levels of the signal being transferred to remain clearly defined and generally unaffected by noise.

The sampling transistor in the sticks of the third and fourth types may be connected to a voltage supply rail, for example the VSS rail. Accordingly when there is a "low" output from the logic array, it is clamped to the supply rail voltage while it is being read by the following circuits to provide a reliable "low" which has been difficult to obtain in some known circuits.

The present invention also provides a ratioless clocked logic unit comprising n ratioless logic circuits in accordance with the present invention, where n is an integer, wherein the outputs of the first to (n-1 )th logic circuits are respectively connected directly to the inputs of the second to nth logic circuits.

Embodiments of the present invention will now be The drawing(s) originally filed was/were informal and the print here reproduced is taken from a later filed formal copy.

described, by way of example, with reference to the accompanying drawings, wherein: Figures 1 and 2 show diagrammatically two alter native arrangements of a stick, Figure 3 is a schematic circuit diagram of a D-type flip-flop, Figure 4 is a diagram of the clock waveforms for use with the circuit of Figure 3, Figure 5 is a circuit diagram of the input stage of an adder circuit having a ripple through carry, Figure 6 is a schematic circuit diagram of the carry logic of the adder circuit, Figure 7 is a schematic circuit diagram of an output stage of the adder circuit, and Figure 8 is a truth table illustrating the overall operation of a complete adder bit stage, that is input, carry logic and output of the adder circuit.

Before proceeding with the description of specific circuits which illustrate embodiments of the invention, reference is made to Figures 1 and 2 which show alternative general arrangements of a stick which may be defined as a series conducting path between a VDD supply rail 14 and a VSS supply rail 16, which path comprises two field effect transistors (FETs) 8, 9 of the same conductivity type and a logic array 10. The gates of the transistors 8, 9 are connected to different, non-overlapping clock phases ~A and ~B SO that both transistors are not conductive at the same time.The drain of the FET 8 is connected to the VDD rail 14 and is termed the precharging FET and the other FETwhich may be connected between the logic array 10 and the VSS rail 16 (Figure 1) or between the FET 8 and the logic array 10 which is connected to the VSS rail 16 (Figure 2) is called the sampling FET. The precharging FET8 may comprise a depletion MOS transistor in which case ~A and ~B will vary between t5 volts for VDD = 5 volts or an enhancement MOS transistor in which ~A and ~B will vary between 0 and +9 volts.

In the illustrated embodiments to be described, the sticks are arranged in the manner shown in Figure 1 and the precharging transistors are depletion transistors however it is to be understood that the sticks may be arranged as shown in Figure 2 and in either arrangement the precharging transistors may be enhancement rather than depletion transistors.

Referring to Figure 3, the illustrated circuit comprises a D-type flip-flop having one stick of each of four different types. In all the described embodiments all the transistors are of the same conductivity type and in the case of the circuits illustrated they are of n-type. Further it should be understood that the reference to MOS transistors is intended to be interpreted in such a broad sense asto include devices where the gate electrode is of a material otherthan a metal, for example poly-crystalline silicon, and where the gate insulating layer is of a composition other than wholly of silicon oxide.

In Figure 3 each type of stick comprises a precharging, depletion transistor T1, T3, T5 and T7 having one end of its source-drain path connected to a VDD supply rail 14 at +5 Volts, a sampling enhancement transistor T2, T4, T6 and T8 having one end of its source-drain path connected to a VSS supply rail 16 at 0 Volts and a logic array 10, 18, 20 and 22 connected between the source-drain paths of the associated depletion and enhancementtransistors. The logic array 10 may be a single FET, in which case the flip-flop performs a delay function, or may be any series/parallel network of FETs to perform any required combinatorial logic.The type of each stick is identified by the clock signal K1, K2, K3 and K4 (Figure 4) applied to the gate of the enhancement transistor atthe bottom of each stick. The depletion transistors T1 to T7 have the clock signals K1 and K2 applied to their gates, it being arranged that the enhancement and depletion transistors of each stick are not conductive at the same time although they may be simultaneously non-conductive. As there are no d.c. current paths the circuit is 100% dynamic.

Coupling between the sticks of the first and second types and between those of the second and third types is by transfer and store gates (TAS gates) comprising respectively an enhancement transistor T16 whose source-drain path is connected between a junction 12 in the first stick and the gate of the transistor T10, and a depletion transistor T18 whose source-drain path is connected between a junction 24 and the gate of the transistor T12. A kick-up capacitor 23 is connected between the junction 24 and the gate of the transistor T1 8. The output QB of the third type of stick is connected to the junction 26 which is also connected to the gate of the transistor T14 of the fourth type of stick. The output Q of the fourth type of stick is derived from a junction 28.In certain applications it is not desired to provide simul- taneously complementary outputs QB and Q in which case the fourth type of stick is optional and may be omitted.

Clock signal K1 is connected to the gates of the transistors T2, T16, T3, the signal K2 is connected to the gates of the transistors T1, T4, T18, T5 and T7, the signal K3 is connected to the gate of T6 and the signal K4 is connected to the gate of T8. Referring to Figure 4 which shows one cycle of the clock signals K1 to K4. In the illustrated circuits the pulse repetition frequency is 512 KHz. Clock signals K1 and K2, which swing between -5V and +5V when going from low to high are non-coincident in time but K2 immediately follows K1. Clock signals K3 and K4 are normally high at +5V but go low to 0V at substantiallythe same time atK1 goes low. K3 goes high again following K2 going low and after a time period corresponding to twice the time period that K3 is low, K4 goes high. It is necessarythatthe low level of K1 and K2 is SV in orderto cut-off the depletion transistors.

In operation when K2 goes high the junction 12 is precharged to substantially the full VDD rail voltage; When K1 subsequently goes high, transistors T2, T16, and T3 are clocked. If the logic array 10 is conductive when the transistors T2 is conductive, the potential atthe junction 12 goes towards that of the VSS rail 16. Since the transistor T1 6 is also conductive the gate of the transisto r T10 goes low.

Alternatively if the logic array 10 is nonconductive, then the transistor T2 is non conductive so that the junction 12 remains high and the charge thereat is shared with the gate of the transistor T10.

Because the transistor T3 has been rendered con ductive the junction 18 has been precharged to the VDD rail 14 voltage.

Accordingly the condition of the circuit at the termination of K1 is that there is a true logic level on the gate of the transistor T10 and the junction 18 has been precharged.

When K2 goes high (and K3 and K4 go low) the junctions 12, 26 and 28 are precharged to the VDD rail 14 voltage via the transistors T1, T5 and T7 respectively, the transistors T4 and T18 are conductive so that the inverted form of the true logic level on the gate of the transistor T10 is now stored on the gate of the transistor T12. The provision of the kickup capacitor 23 ensures that in the case of a logic "high" value being stored on the gate of the transistor T1 2, there is sufficient charge available to lift the "high" value so that it is clear of any noise present in the circuit.

At the termination of K2, K3 goes high and the inverted form of the logic level stored on the gate of the transistor T1 2 appears at the output terminal QB.

It should be noted that in the case of the output on the terminal QB being a low, it is held at the VSS rail 16 voltage until K2 next goes high, consequently a reliable "low" value is maintained throughout the next time K1 is high.

An inverted form of the output on the terminal QB is obtained on the output terminal Q by the K4 going high. The delay between K3 and K4 going high is to enable the third type of stick to become stable before clocking the fourth type of stick. Because K4 remains high until K2 next goes high, a "low" at the terminal Q is made reliable by clamping the junction 28 to the VSS rail 16 voltage throughout the next time K1 is high.

The illustrated circuit behaves as a D-type flip-flop because it is able to transfer the output of the logic array to the output terminal Q with one clock period delay, the output being true while K1 is high.

This family of circuits is effectively ratioless in that all transistors have a width to length (W/L) ratio of 4/4.

In the case of fabricating the circuit as an integrated circuit, the kick-up capacitor 23 may comprise a capacitor formed by a double level metallisation process or a depletion transistorT20 shown in broken lines. The area of the transistor T20 is determined by how much charge is required to be stored for sharing between the junction 24 and the gate of the transistor T1 2, and may be 7 x 7 #m2. In the illustrated circuit the gate of the transistor T20 is connected to the junction 24 and its source and drain are connected to the gate of the transistor T1 8.

Alternatively the transistor T20 may be arranged so that its gate electrode is connected to the gate of the transistorT18 and its source and drain electrodes are connected either both to the coupling between the transistors T3 and T10 orto form the coupling between the transistors T3 and T10, because it avoids having to go out of diffusion into polysilicon twice.

The kick-up capacitor may also comprise an enhancement transistor.

Turning now to Figures 5, 6 and 7 which illustrate parts of a binary adder circuit which utilises different numbers of the first, second, third and fourth types of sticks, it is assumed that the two numbers to be added are multi-bit, and illustrated is one full adder bit which adds two bits other than the least significant bits. All the bits in the two numbers are added in parallel in one clock cycle.

Figure 5 comprises an input stage in which three different combinational functions of the two input bits are obtained. These are then used in a ripplethrough carry logic circuit shown in Figure 6. The sum output signal is derived from the carry logic circuit using an output stage shown in Figure 7.

Referring to Figure 5, the input stage effectively comprises three sticks of the first type in which instead of having an enhancement transistor at the bottom of each stick, a common enhancement trans istorT30 of W/L ratio 8/4 is provided. As indicated the transistor T30 is clocked by clock signal K1 (Fig urge4).

The first stick 25 comprises a logic array in the form of an EXCLUSIVE OR gate connected between the source-drain path of the transistor T30 and that of a depletion transistorT32 which is also connected to the VDD rail at +5V. The EXCLUSIVE OR gate comprises two parallel arranged paths, one of which comprises enhancement transistors T33, T34 connected in series to whose gates data signals D1 and D2 are applied, respectively, and the other of which comprises enhancement transistors T35 and T36 connected in series to whose gate the inverted data signals D1 and D2 are applied, respectively.An output terminal W3 is connected to a junction 30 to which one side of a kick-up capacitor 31 is connected, the other side of the capacitor 31 being connected to the gate electrode of the transistor T30.

In operation the junction 30 is precharged to the VDD rail 14 voltage by K2 going high and gating the transistor T32 on. Thus when K1 goes high to gateon the transistor T30, the output at the terminal W3 will adopt the logic level of the logic array which in the present case will be "high" if only D1 or D2 is high and "low" if both D1 and D2 are high or low.

The kick-up capacitor 31 provides additional charge to be shared in the carry logic circuit.

The logic array in the second stick 27 comprises a NOR gate connected between the source-drain paths of a depletion transistor T38, whose gate is clocked by clock signals K2, and the enhancement transistor T30. The NOR gate comprises enhancementtransistors T39 and T40 whose source-drain paths are connected in parallel and whose gates receive the data inputs D1 and D2 respectively. An output terminal W2 is connected to a junction 32 of the NOR gate and the source-drain path of the transistor T38. A kick-up capacitor 33 is connected between the junction 32 and the gate of the transistor T30. The condition of the logic array will only be high when inputs D1 and D2 are low. The operation of the stick 27 in response to the clock signals K1 and K2 will be apparent from the previous description of the stick 25 and will not be repeated again.

The logic array of the third stick 29 comprises an AND gate formed by enhancement transistors T43 and T44 whose source-drain paths are connected in parallel between the source-drain path of a depletion transistor T42 and that of the transistor T30. The transistorT42 which is also connected to the VDD rail 14, has its gate connected to receive the K2 clock signals. Inverted data inputs D1# and D2 are applied to the gates of the transistors T43 and T44, respec tively. An output terminal W1 is connected to a junc tion 34 of the logic array and the source-drain path of the transistor T42, the junction 34 being high when both inputs D1 and D2 are high (that isD1 and D2 are low). A kick-up capacitor 35 is connected between the junction 34 and the gate of the transistor T30.

The carry logic of Figure 6 effectively comprises two sticks 36,38 of the second type having respec tive depletion mode MOS transistors T45, T46 con nected between the VDD rail 14 and the junctions 40, 42 which are connected to a common logioarrny 44 which in turn is connected to one end of the source- drain path of a common sampling enhancement transistor T47, the other end of which path is con nected to the VSS rail 16. The precharging transis tors T45 and T46 are clocked by K1 whilst the transis torT47 is clocked by K2. An output X1 is derived from the junction 40 and an output X2 from the junc tion 42.

The logic array 44 includes a carry-in (Cl) line 46 from a carry logic stage (not shown) of less signifi cance and a carry-out (CO) line 48 which is con nected to carry logic stage (not shown) of greater significance. The lines 46 and 48 are connected to the source and drain electrodes of an enhancement transistor T48. Lines 50 and 52 provide the comple ment (CIB and COB, respectively) of the carry-in and carry-out signals, these lines 50 and 52 are con nected to the source and drain electrodes of an enhancement transistor T49.The CO line 48 and COB line 52 are connected by way of the source-drain paths of respective enhancement transistors T50 and 51 to the one end of the source-drain path of the transistor T47. The junction 40 is connected to the CIB line 50 by way of the source-drain path of an enhancement transistor T52. The junction 42 is con nected to the Cl line 46 by way of the parallel arranged source-drain paths of enhancement trans istors T53 and T54 which in one mode of operation act as a NOR gate.

Input terminals W1, W2 and W3 are coupled to the respective outputs W1, W2 and W3 of the input stage shown in Figure 5. The input terminal W1 is con nected by a TAS gate, enhancement transistor T55, to the gate electrodes of the transistors T51 and T54.

The input terminal W2 is connected by a TAS gate, enhancement transistor T56, to the gate electrodes of the transistors T50 and T56. Finally the input ter minal W3 is connected by a firstTAS gate, enhancement transistor T57, to the gate electrode of the transistor T52 and by a second TAS gate, deple tion transistor T58, to the gate electrodes of the transistors T48 and T49. All the TAS gate transistors are clocked by K1. The W/L ratios of the transistors T47 to T51 are each 20/4 lim and those of the other transistors T45, T46 and T52 to T58 are each 4/4,am.

The operation of the overall adder bit stage is shown in the truth table of Figure 8 and the opera tion of the ripple through carry logic will be explained by reference to the columns Cl, W3, W2, Wl, Xl, X2 and CO. It will be realised from the preceding description of Figure 3 that at the occurrence of clock signal K1,thejunctions40 and 42 of the carry logic are precharged to VDD and the logic level on the input terminals Wl, W2 and W3 will be adopted by the gate electrodes of the transistors to which the TAS gate transistors a re connected. At the occurrence of clock input K2, the outputs X1 and X2 adoptthe logic levels of the respective parts of the logic array 44 which simultaneously passes any carry signal from one stage to the next.In the case of CEbeing low, the line 46 being connected to VSS by a less significant bit, and CIB being high then output X1 is unconditionally high and the outpelt X2 adopts the NOR function of inputs W1 and W2, CD being high cmlywhen W1 is high and W2 is low,Con- versely when Cl is high and CIB is low, the line 50 being connected to VSS by a less significant bit, then output X1 adopts a logic level which is the complement of the logic::Fevel on the input3, and the out putX2 is unconditionally high, CO being high in the cases where W1 and W2 are both low and where W1 is high and W2 is-low.

Figure 7 illustrates an embodiment of an output stage which comprises one stick 54 of the third type and one stick 56 of the fourth type.

The third type of stick 54 comprises a NAND logic array connected in series with the source-drain paths of a precharging, depletion transistor T60, connected also to the VDD rail 14, and a sampling, enhancement transistor T61, connected also to the VSS rail 16. The NAND logic array comprises enhancement transistors T62 and T63 whose source-drain paths are connected in series. The outputs X1 and X2 of the carry logic (Figure 6) are connected respectively to the gates of the transistors T62, T63 via respective TAS gates in the form of depletion transistors T64, T65. The gates of the transistors T60, T64 and T65 are clocked by clock signals K2 whereas the gate of the transistor T61 is clocked by clock signals K3.

Kick-up capacitors 60,62 are connected respectively between X1 and X2 and the gates of the transistors T64 and T65. An output QB of the stick is derived from a junction 58 of the source-drain path of the depletion transisto r T60 and the NAND logic array In the operation of this stick, the junction 48 is precharged during the period that K2 is high and when K3 goes high the logical output of the logic array appears or: the output QB. This is shown inthe truth table of Figure 8 and requires no further explanation.

The fourth stick 56 provides an output Q the inverted form of the output QB. Since the construe tion and operation of this stick is self evident from the description of the corresponding stick in Figure ly it will not be repeated again.

In so far as the fabrication of the adder of Figures 5,6 and 7 as an integrated circuit is concerned, apart from the transistors identified below the W/L ratios of the other transistors is 4/4. In Figure 5 the W/L ratios of the transistor T30 is 8/4. In Figure 6 the W/L ratios of the transistors T47, T49, T52, T26 and T56 are all 20/4. The kick-up capacitor 31 in Figure 5 may have an area of 15 x 15 Sam2 whilst that of the capacitors 33 and 35 may be 10 x 10,am2, and the kick-up capacitors 60, 62 in Figure 7 may have areas of 7 x 7,am2 each. These kick-up capacitors may be fabricated in one of the several different ways stated earlier for the capacitor 23.

In certain implementations of the logic circuit in accordance with the present invention, there may be a plurality of sticks of the third type, the outputs of which are connected to a fourth type of stick. The logic will only produce a Q output, the QB output having been sacrificed.

A Aplurality of the described logic circuits may be connected together to form a ratioless clocked logic unit. In connecting the logic circuits together the output(s) of one circuit is (are) connected to the input(s) of the next following circuit without an intervening TAS gate.

Claims (12)

1. A ratioless logic circuit comprising first, second and third types of stick, each stick including a precharging MOS transistor, a sampling MOS transistor and a logic array coupled between voltage supply rails, an input coupled to the logic array and an output derived from the source of the precharging transistor, the precharging and sampling transistors of each stick, in use, being clocked so that only one or other transistor is conductive at any one time, and a transfer and store (TAS) gate coupled to the output of each stick of the first and second type.

2. A circuit as claimed in Claim 1,furthercom- prising a fourth type of stick including a precharging MOS transistor, a sampling transistor and an inverting logic array, an input coupled to the logic array, which input is connected to the output of a stick of the third type, and an output derived from the source of the precharging transistor; the precharging and sampling transistors, in use, being clocked so that only one or other transistor is conductive at any one time and the sampling transistor of the fourth type of stick, in use, being clocked-on after the sampling transistor of the third type of stick.

3. A ratioless logic circuit comprising one or more sticks of a first and second type and a stick of a third type, each type of stick comprising a precharging MOStransistor, a sampling MOS transistor and a logic array, an input to the logic array and an output derived from the source of the precharging transistor, transfer and store (TAS) gates for coupling respectively the output of each stick of the first and second types to the input of an associated stick of the second and third types, the TAS gate being clocked in synchronism with the sampling transistor of the stick to whose output it is connected, and means for providing first, second and third clock pulses of which the first clock pulses are supplied to the sampling transistor of the or each first type of stick, the second clock pulses, which do not overlap the first clock pulses, are supplied to the sampling transistor of the of each second type of stick and the third clock pulses, which do not overlap the second clock pulses and rise before and overlap the first clock pulses, are supplied to the sampling transistor of the third type of stick.

4. A circuit as claimed in Claim 3, further comprising a fourth type of stick comprising a precharging MOS transistor, a sampling MOS transistor and a logic array comprising a single MOS transistor whose gate is connected directly to the output of the stick of the third type, and means providing fourth clock pulses to the sampling transistor, which fourth clock pulses rise after the third clock pulses but before the first clock pulses and overlap the first clock pulses, the output of the fourth type of stick being derived from the source of the precharging transistor, which output is the complement of that of the third type of stick to which it is connected.

5. A circuit as claimed in Claim 2 or 4, wherein the source-drain path of the sampling transistor the fourth type of stick is connected to a supply voltage rail whereby a "low" output of the logic array of that stick is clamped to the supply rail voltage when the output is read.

6. A circuit as claimed in any one of Claims 1 to 5, wherein the source-drain path of the sampling transistor of the third type of stick is connected to a supply voltage rail, whereby a "low" output of the logic array of that stick is clamped to the supply rail voltage when the output is read.

7. A circuit as claimed in any one of Claims 1 to 4, wherein each TAS gate comprises an MOS transistor whose source-drain path is connected between the output of a stick of one type and the input of a stick of another type, the gate of the MOS transistor being clocked simultaneously with the gate of the sampling transistor of the stick to whose output the MOS transistor is connected, and wherein a kick-up capacitor is connected between the gate of the MOS transistor and the side of the source-drain path the MOS transistor coupled to the output of a stick.

8. A circuit as claimed in any one of Claims 1 to 7, wherein when two or more sticks of the same type are used, the logic arrays of each stick are connected in series with the source-drain path of a sampling transistor which is common to said sticks.

9. A ratioless logic circuit substantially as hereinbefore described with reference to the accompanying drawings.

10. A ratioless clocked logic unit comprising n ratioless logic circuits as claimed in any one of Claims 1 to 9, where n is an integer wherein the outputs of the first to (n-l )th logic circuits are respectively connected directly to the inputs of the second to nth logic circuits.

11. AD-type flip-flop constructed and arranged to operate substantially as hereinbefore described with reference to Figures 3 and 4 of the accompanying drawings.

12. A binary adder constructed and arranged to operate substantially as hereinbefore described with reference to Figures 5 to 8 of the accompanying drawings.