GB2064860A - Method for metallizing a semiconductor element - Google Patents

Method for metallizing a semiconductor element Download PDF

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Publication number
GB2064860A
GB2064860A GB8031411A GB8031411A GB2064860A GB 2064860 A GB2064860 A GB 2064860A GB 8031411 A GB8031411 A GB 8031411A GB 8031411 A GB8031411 A GB 8031411A GB 2064860 A GB2064860 A GB 2064860A
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United Kingdom
Prior art keywords
regions
semiconductor device
plasma etching
plasma
metal
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Granted
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GB8031411A
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GB2064860B (en
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General Electric Co
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General Electric Co
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Filing date
Publication date
Priority claimed from JP13352579A external-priority patent/JPS5659434A/en
Priority claimed from US06/098,907 external-priority patent/US4247579A/en
Application filed by General Electric Co filed Critical General Electric Co
Publication of GB2064860A publication Critical patent/GB2064860A/en
Application granted granted Critical
Publication of GB2064860B publication Critical patent/GB2064860B/en
Expired legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H01L21/3046—Mechanical treatment, e.g. grinding, polishing, cutting using blasting, e.g. sand-blasting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J29/00—Details of cathode-ray tubes or of electron-beam tubes of the types covered by group H01J31/00
    • H01J29/02—Electrodes; Screens; Mounting, supporting, spacing or insulating thereof
    • H01J29/10—Screens on or from which an image or pattern is formed, picked up, converted or stored
    • H01J29/36—Photoelectric screens; Charge-storage screens
    • H01J29/39—Charge-storage screens
    • H01J29/44—Charge-storage screens exhibiting internal electric effects caused by particle radiation, e.g. bombardment-induced conductivity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

A method of forming a metal electrode on a semiconductor device includes the steps of mechanically abrading the surface of the device as by grit dusting, plasma etching the surface and applying the metal electrode. Where surface adjacent regions of differing dislocation densities are present, the mechanical abrading followed by plasma etching produces a surface to which a metal layer may be applied with relatively uniform adherence characteristics.

Description

SPECIFICATION Method for metallizing a semiconductor element This invention relates in general to the formation of electrodes on the surfaces of bodies of semiconductor material and more particularly to the preparation of such surfaces for the application of such electrodes thereto.
In orderto enable the performance of a useful function, electrical connection must be made to a semi-conductor device. One method for making such an electrical connection is to provide specific metal layer or layers on portions of the semiconductor body to which electrical connection are required.
A low resistance electrical connection may be made thereto by soldering, high pressure dry interface methods, or the like.
In order to ensure that consistently good quality electrodes are formed on semiconductor surfaces, attention must be directed to the preparation of such surfaces prior to the deposition of a metal layer thereon. Heretofore, various methods of surface preparation have been employed which have commonly included surface cleaning in a concentrated acid or the like to remove impurities and to provide a surface favorable for metallization. Such wet chemical surface preparation techniques are expensive and cumbersome often requiring repeated immersions of the semiconductor device into various caustic and/or acidic solutions and also requiring multiple steps to ensure the complete removal of such solutions by, for example, quenching and rinsing.
Some of the disadvantages of wet chemical processing may be eliminated through the appropriate application of plasma processing to the wafer. The attractiveness of plasma processing in the manufacture of semiconductor devices is due to several considerations including cost savings and higher yields, as well as environmental factors. Additionally, processing advantages such as the capability for sequential multi-step processes without the necessity for handling the wafers merely through the manipulations of the plasma conditions makes automatic semiconductor device processing possible. In accordance with such processing, the semiconductor devices would remain within the plasma reactor and the sequential processes would be accomplished by changing the nature of the plasma in the reactor.
One area of semiconductor device processing in which plasma techniques appear not to have thus far been employed is in the preparation of semiconductor surfaces for the application of electrodes thereto.
In order to achieve a high quality ohmic contact to a diffused silicon surface, which contact is easily manufactured and meets the required device specifications such as low resistance contact to the wafer and strong mechanical adherence thereto, and has good reliability, the following conditions interalla are required. The depletion region at the silicon surface prior to contact application must be removed. A roughened silicon surface such as that provided by mechanically abrading the surface preparation must be provided in order to insure good mechanical adherence between the contact material and the silicon surface. The silicon surface must be free of organic and inorganic impurities as well as oxides and moisture.
While plasma etching alone is capable of providing a semiconductor surface for metallization which exhibits the above-identified preferred characteristics, it has been observed that the surface conditions of the semiconductor device depend not only upon the time and conditions of the plasma etching step, but also upon the nature of the semiconductor region, the surface of which is subjected to the plasma process. Some surfaces, therefore, may require different conditions of plasma etching than others in order to achieve the same ultimate surface conditions for bonding.While it is relatively easy to adjust the plasma conditions to provide the desired semiconductor surface conditions where a single type of semiconductor region with regard to conductivitytype concentration, and the like, is being prepared, in some instances more than one such region is preferably simultaneously prepared in a single plasma step. For example, certain bilateral triode thyristors such as triacs include a single electrode which bridges two surface adjacent semiconductor regions of different conductivity types and surface concentrations. The plasma etching of the surface including these distinct regions result in a degree of nonuniformity which adversely affects electrode application thereto.
The present invention broadly provides a method of making a semiconductor device having a metal electrode thereon, including the steps of: mechanically abrading the surface of the semiconductor device; plasma etching said surface; and applying said metal electrode.
As applied to preparing a semiconductor surface including first and second surface adjacent regions at different surface impurity concentrations, the method may include the steps of grit dusting the surface, then simultaneously etching the entire surface in a plasma followed by depositing a metal layer on the etched surface.
Normally, where p-type and n-type regions of high surface concentration are employed, the n-type region has a slightly higher surface concentration than the p-type region and, therefore, the number of dislocations introduced into the silicon lattice by diffusion is generally greater than the number introduced by the p-type dopant. It has been discovered that when two such regions are simultaneous- ly exposed to a gaseous plasma for surface preparation that independent of the plasma condition including the time of plasma etching, the pconductivity type region exhibits an ultimate surface roughness which is less than the ultimate surface roughness of the n-conductivity type region.When a metal layer is thereafter applied to the plasma etched surface, the degree of adhesion to the p-type surface region is less than that to the n-type surface region and failure of the device through separation of the metal layer therefrom is possible. It might be expected that by some sort of pre-etching treatment of the p-conductivity type region, a more uniform surface could be produced. Such a pre-etching step would require masking of the n-conductivity type region and selective exposure of the adjacent pconductivity type region to a pre-etch treatment.
This procedure leads to the increased possibility of processing misalignment and the like and, consequently, is not to be preferred. It has been discovered, quite unexpectedly, that by lightly abrading the entire surface to which a contact is desired to be applied, that is to say, both the p and the nconductivity type regions, followed by plasma etching of the entire surface, that a uniform surface roughness is provided. Upon the subsequent application of a metal layer to the plasma etched surface, a uniform degree of adherence is obtained. In accordance with a presently preferred embodiment of this invention, the surface to which contact is desired to be made is abraded by a lightly grit dusting with fine optical powder as will be more thoroughly described hereinbelow.The effect of grit dusting prior to plasma etching is somewhat unexpected inasmuch as grit dusting does not appear to affect the p and the n-conductivity type regions equally which would result in maintaining the difference in surface roughness after the plasma etch step, but rather results in elimination in difference of roughness heretofore experienced by plasma etching alone.
An embodiment of the invention as applied to a silicon type semiconductor device will now be described by way of example.
The silicon device is prepared up to the point where metal electrodes are applied according to techniques well known to those skilled in the art such as mask diffusion, groove etching for passivation, glass deposition, and the like. Those areas to which a metal contact is to be applied are defined by a mask which is preferably a photo-lithographic mask as is quite commonly employed for masked diffusion. Those areas where metal contacts are desired are open, and those other areas including glass grooves and the like are masked by the photoresist. Such techniques are well known and no deviation from techniques known by those skilled in the art is required for practicing this invention.
Preferably, the photoresist has a thickness of about 60 - 80 KA and may be made of any material which is not unduly affected by grit dusting or by plasma etching.
Where contacts are decided to be applied to both sides of a semiconductor wafer, such as a diode, transistor, thyristor, or bidirectional triode thyristor, all the following steps may be simultaneously performed on both sides of the wafer. Grit dusting is accomplished by directing a stream of particles at the surface of the semiconductor device. While grit dusting itself is a well known technique and may be employed in accordance with this invention without special modification, it is preferred to employ a grit dust prepared as follows: sieve a quantity of No. 250 Optical Powder through a 74-micron screen, place the sieved powder in an oven at about 1600C for a period of at least one and one-half hours, store the grit in closed containers until ready for use. The grit dust thus prepared is directed in a stream against the surface of the semiconductor wafer.After grit dusting, the surface should have a dull grey appearance rather than the shiny metallic appearance prior to grit dusting. Only a light grit dusting is required by this invention, a few seconds per side being adequate. A convenient method for determining the amount of grit dusting required is to weigh the wafers prior to and subsequent to the grit dust step.
It is preferred that about .03 - .07 mils of silicon be removed, the weight being a function of the diameter of the wafer, the calculation of which is well within the cognizance of one skilled in the art. After grit dusting, the wafers are cleaned, for example, by rinsing in deionized water and then baked in nitrogen at about 1400Cfor about10minutes. The wafers are now ready for plasma etching. While any plasma which will etch the grit dusted silicon surface while not attacking the masked silicon surface may be employed, it has been found that carbon tetrafluoride, CF4, which may be purchased under the trade name Freon-14, which is available from Dupont Corporation, is advantageously employed.
Preferably, the plasma also contains a small amount of oxygen. A preferred gas is described in U.S.
Patent No. 3,795,557. Increasing the oxygen content of the plasma increases the degree of reaction with the photoresist masking material, but, at the same time, slows the etch rate of silicon and increases the degree of control thereof. An oxygen content of about four per cent is preferred.
In the alternative, other plasma may be employed such as SIF4 also including about four per cent of oxygen.
The plasma conditions and the time of etching may be varied to increase the rate of etch while decreasing the time therefor, or vice versa, according to principles well known to those skilled in the art. It has been found, however, that an etch having a duration of about five minutes at a temperature of about 750C is preferred in accordance with this invention. The plasma conditions are to some extent dependent on the number of wafers being etched as is well known to those skilled in the art. The conditions hereinabove described are appropriate for about 50 wafers in a 10-inch diameter, 18-inch long chamber.The plasma conditions should be adjusted so that the depletion region at the silicon surface is removed prior to contact application, the surface has a degree of roughness which provides, for the particular metallization employed, suitable roughness to insure good mechanical adherence to the surface, and finally that the surface is free of organic and inorganic materials, oxides, and moisture. As heretofore mentioned, between .03 and .07 mils were removed during the grit dust operation and the plasma etch conditions should be established to remove between about .04 and .07 mils. It is preferred that the total amount of material removed by the mechanical abrading and plasma etching steps be sufficient to remove any depleted surface layer but not so much as to significantly reduce the surface impurity concentration of the device.
The devices are ready for the application of metallic contacts thereto immediately after removal from the plasma reactor. Where it is necessary to store the wafers after plasma etching, it is preferred that the same be stored in an inert atmosphere such as dry nitrogen until ready for plating. It is further preferred that no more than about two hours be allowed to elapse between the plasma etching and the plating.
Vapor plating provides a preferred method for the application of metal electrodes to semiconductor devices processed in accordance with this invention.
While the surface preparation technique hereinabove provides a surface which is suitable for the application for a variety of metallizations thereto, it has been found that chrome-nickel-silver electrodes are advantageously employed.
The method of the invention may thus be used for forming an electrical contact on the surface of a semiconductor body having more than one surface adjacent a semiconductor region of different impurity concentration and/or different impurity type. For example, a method has been described for simultaneously forming an electrode on the surface adjacent p and n-type regions such as are found in a bi-directional triode thyristor (triac). Other examples of semiconductor devices where opposite conductivity type regions are divided to be provided with metal electrodes simultaneously, include the cathodes and gates of SCR's, the emitter regions of any thyristor wherein emitter shorts are provided which rely upon the termination at the surface of the device of regions of opposite conductivity type.

Claims (11)

1. A method of making a semiconductor device having a metal electrode thereon, including the steps of: mechanically abrading the surface of the semiconductor device; plasma etching said surface; and applying said metal electrode.
2. A method according to claim 1 of making a semiconductor device having first and second regions therein of different impurity concentrations, including the steps of: simultaneously mechanically abrading the surfaces of said first and second regions; simultaneously plasma etching said surfaces; and applying a metal layer to said surfaces.
3. A method according to claim 1, comprising the steps of: forming a semiconductor body having first and second regions therein of different impurity concentration, said regions each including a surface portion; mechanically abrading the surface portions of each region; simultaneously plasma etching said surface portions; applying a metal layer to said surface portions.
4. A method according to claim 2 or claim 3, wherein said step of mechanically abrading comprises grit dusting said surfaces or surface portions.
5. A method according to any one of claims 2 to 4, wherein the first and second regions comprise regions of opposite conductivity type.
6. A method according to claim 1 of forming a semiconductor device having first and second coplanar regions of different dislocation density, including the steps of: mechanically abrading said regions to equalize the dislocation densities therein; simultaneously plasma etching said regions; and applying a layer of metal to each of said regions whereby the adherence of the metal layer is essentially uniform as to the first and second regions.
7. A method according to claim 1 of forming a semiconductor device having first and second surface adjacent regions of different conductivity determining impurity type, including the steps of: simultaneously abrading the surfaces of the first and second regions; simultaneously plasma etching said surfaces; simultaneously applying a layer of metal to said surfaces, said layer of metal adhering equally to said first and second regions.
8. A method according to any one of the preceding claims, wherein said step of plasma etching comprises etching in a fluorine plasma.
9. A method according to claim 8, wherein the fluorine plasma includes a few percent of oxygen.
10. A method according to claim 1 of making a semiconductor device having a metal electrode thereon, substantially as hereinbefore described.
11. A semiconductor device having a metal electrode thereon, made by the method according to any one of the preceding claims.
GB8031411A 1979-10-18 1980-09-29 Method for metallizing a semiconductor element Expired GB2064860B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP13352579A JPS5659434A (en) 1979-10-18 1979-10-18 Secondary electron multiplying target
US06/098,907 US4247579A (en) 1979-11-30 1979-11-30 Method for metallizing a semiconductor element

Publications (2)

Publication Number Publication Date
GB2064860A true GB2064860A (en) 1981-06-17
GB2064860B GB2064860B (en) 1984-01-25

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2132412A (en) * 1982-12-08 1984-07-04 Int Rectifier Corp Improvements in or relating to methods of manufacture of semiconductor devices

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2132412A (en) * 1982-12-08 1984-07-04 Int Rectifier Corp Improvements in or relating to methods of manufacture of semiconductor devices

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Publication number Publication date
GB2064860B (en) 1984-01-25

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