GB2064247A

GB2064247A - Pulse Generating Circuit

Info

Publication number: GB2064247A
Application number: GB7928653A
Authority: GB
Original assignee: Clarion Co Ltd
Current assignee: Faurecia Clarion Electronics Co Ltd
Priority date: 1979-08-16
Filing date: 1979-08-16
Publication date: 1981-06-10
Also published as: GB2064247B

Abstract

A pulse generating circuit for producing a pulsive output in response to an input signal. In the circuit, a circuit C2 charges rapidly by the input signal and discharges at a predetermined time constant upon disappearance of the input signal. An output voltage of the circuit C2 elongates a pulse width of the pulsive output to a width of the input signal pulse plus a predetermined width. <IMAGE>

Description

SPECIFICATION Pulse Generating Circuit This invention relates to a pulse generating circuit suitable for semiconductor integrated circuit formation, which is capable of producing an output pulse having a pulse duration as long as a pulse duration of an input pulse plus a predetermined duration and having a rapid rising characteristic.

As illustrated in Figure 1 (A) and (eel), known monostable multivibrator circuits can only produce a pulse having a definite duration To from a leading edge of an input trigger pulse T, or T2 (Figure 1 (A)) or from a tail edge thereof (Figure 1 (B)).

It is therefore an object of the present invention to provide a pulse generating circuit which is capable of producing a pulse having a pulse width corresponding to combination of a pulse width T' or T'2 of an input pulse (trigger pulse) and a predetermined width T'o, i.e., a pulse width of T'1+T'0orT'2+T'0 as illustrated in Figure 1 (C).

Another object of the invention is to provide a pulse generating circuit which is capable of producing a pulse having a rapid rising characteristic enabled especially by constant current and constant voltage drive of the circuit.

Such a pulse generating circuit as can generate, in response to an input trigger pulse, an output pulse having a duration corresponding to the combination of the duration of the input trigger pulse and a predetermined duration is effectively employed especially in a noise eliminating circuit for eliminating a noise interfering with an FM signal or an AM signal.

Figure 2 shows a block diagram of an FM noise eliminating circuit. When an input signal containing a noise is applied to an input terminal 1, the input signal is supplied to a gate circuit 3 through a low pass filter 2. On the other hand, the noise is detected by a high pass filter 4 to trigger a pulse generating circuit 6. The output pulse from the circuit 6 is then applied to the gate circuit 3 to open the same during the occurrence of the noise preventing the input signal from appearing at an output terminal 7.

The trigger pulse responsive to the noise passed through the high pass filter 4 has a duration shorter than the actual duration of the noise. On the other hand, the noise component applied to the gate circuit 3 has a duration increased than the actual duration of the noise since it is treated by the low pass filter 2.

Therefore, in order to open the gate circuit 3 throughout the occurrence of the noise, the output pulse of the pulse generating circuit 6 should have a duration as long as the duration of the trigger pulse plus a duration necessary for compensating for the reduction in duration due to the treatment by the high pass filter 4 and a duration for covering the increase in duration due to the treatment by the low pass filter 2. Such a pulse is provided in the form as illustrated in Figure 1 (C).

The invention will be better understood from the ensuing description given in connection with the accompanying drawings in which: Figure 1 is a diagram showing relations between input pulses and output pulses: (A) and (B) show the relations between input pulses and output pulses of known monostable multivibrators; (C) shows the relation between an input pulse and an output pulse of a pulse generating circuit in accorance with the invention; Figure 2 is a block diagram of an FM noise eliminating circuit; Figure 3 is a circuit diagram of one form of the pulse generating circuit in accordance with the invention; Figure 4 is a diagram showing potentials at various portions in the circuit of Figure 3; Figure 5 is a circuit diagram of another form of the circuit in accordance with the invention; and Figure 6 is a diagram showing potential waveforms at various portions in the circuit of Figure 5.

The invention will now be described in detail referring to Figures 3 to 6. Figure 3 illustrates one form of a pulse generating circuit in accordance with the invention. Figure 4 shows potentials at various portions in the circuit illustrated in Figure 3. In the circuit of Figure 3, when an input signal is applied to an input terminal 8, the signal is amplified by transistors Q1 and Q3 and a pulse output appears at an output terminal 9. The input signal applied to the input terminal 8 is further applied to transistors Q2,Q4 and Q5 for amplification and charges capacitor C1. When the input signal is removed, the capacitor C, discharges through a resistor R9 at a predetermined time constant and the potential of the capacitor C1 is applied to the base of the transistor Q3 through a resistor R2.Therefore, the transistor Q3 remains conducting even after removal of the input signal so long as the capacitor C1 discharges and an output as illustrated in Figure 1 (C) appears at the output terminal 9.

The circuit will be explained more specifically referring to Figures 3 and 4. While the transistors Q1 to Q5 are normally in their OFF state, the transistors Q1 and Q2 conduct simultaneously when a trigger pulse produced due to a noise and having a pulse width T1 is applied to the input terminal 8 as illustrated in Figure 4 (8). When the transistor Q2 conducts, the transistor Q4 and Q5 conduct in turn. Upon conducting of the transistor Q5, the capacitor C1 charges since the capacitor C, is connected to the junction 12 of resistors R8 and R9.Therefore, even when the input pulse disappears, the potential at the junction 12 is not immediately lowered to zero but lowered according to a time constant determined by the resistors R9 and R2 and the capacitor C,.

Consequently, though the collector potential of the transistor Q3 rises immediately, as illustrated in Figure 4 (9), upon application of the input pulse, via the transistor Q1 and the transistor 03, the transistor Q3 is held conductive after the input pulse disappears, until the potential at the junction 12 is lowered to below a threshold voltage VIE of the transistor Q3.

Thus, a pulse having a width of T2+To is obtained at the output terminal 9. The pulse width To is determined by the resistors R, and R2 and the capacitor C1. The resistor R8 is inserted so as to prevent a rush current caused upon conducting of the transistor Q5.

Figure 5 illustrates another embodiment of the invention. Transistors Q1 to Q5 are arranged identically to those in the circuit of Figure 3. An input signal is applied to the circuit through a differential amplifier formed of transistors Qs and Q7. A power supply potential is regulated by a resistor R11, a diode D2 and a zener diode D3. In this circuit, a pulse having a more accurate pulse width can be obtained rapidly by constant current and constant voltage drive of the circuit. Figure 6 illustrates potential waveforms at portions 13, 14 and 15 of the circuit illustrated in Figure 5.

As mentioned above, the pulse generating circuit of the invention enables generation of a pulse having a width corresponding to a duration of an input pulse and a predetermined time length, and can be advantageously employed in a noise eliminating circuit for eliminating a noise interfering with an FM or AM signal.

Claims

1. A pulse generating circuit which comprises: a first circuit for amplifying an input pulse signal; a second circuit adapted to charge by the pulse signal amplified by said first circuit and to discharge at a predetermined time constant upon disappearance of said signal; and a third circuit for generating a pulsive output in response to the input pulse signal which pulsive output has a pulse duration increased by a predetermined length over the pulse duration of the input pulse signal by the output of said second circuit.

2. A pulse generating circuit of claim 1 which further comprises a differential amplifier circuit and a constant voltage circuit and wherein said input pulse is applied to said first and third circuits through said differential amplifier circuit and a power supply voltage is applied to said first to third circuits and said differential amplifier circuit through said constant voltage circuit.

3. A pulse generating circuit substantially as hereinbefore described with reference to and as illustrated in the accompanying drawings.