GB2059704A - Improvements in and relating to digital inverters employing field effect transistors - Google Patents

Abstract

A method of coupling adjacent stages of a digital logic circuit in which a stage includes an active load device connected in the drain circuit of a depletion mode field effect transistor (FET), by means of a capacitive element located between the stages of the circuit which produces the voltage necessary to turn the depletion mode FET off by bootstrapping. A logic circuit including an inverter consisting of a depletion mode field effect transistor having an active drain load, has a capacitive element connected to the gate circuit of the transistor. The capacitive element provides an input port to the logic circuit and permits cascading of the digital logic circuits without the need for special level-shifting circuits previously needed with depletion mode devices. The digital logic circuit is preferably constructed as a monolithic integrated circuit using gallium arsenide as the semiconductor material and with metal-semiconductor field effect transistors (MESFETS) in order to employ the advantages of MESFETS in digital communications systems. <IMAGE>

Description

SPECIFICATION Improvements in and relating to digital inverters employing field effect transistors The present invention relates to digital circuits which employ depletion mode field effect transistors.

A depletion mode field effect transistor is a three-terminal device in which the resistance between two of the terminals is low when no bias potential is applied at the third terminal, and in which the resistance between the two said terminals can be increased by providing at the third terminal a bias potential which lies below that of both of the other terminals. The terminals of a field effect transistor are identified as the source, drain, and gate terminals, respectively, the controlling terminal being the gate terminal.

Some classes of depletion mode field effect transistors known at present have cut-off frequencies in the gigahertz range. Their high cut-off frequency makes them suitable for use in digital communications systems, but circuits employing them suffer from the disadvantage that special provision must be made if more than one stage is required, since the input and output voltage swings of any stage differ, which means that cascading is not straight forward. At present, cascading is effected by the use of voltage level shifting circuits which increase power dissipation and signal delay, and reduce yields of intergrated circuits because they increase the complexity of the integrated circuits.

The depletion mode field effect devices referred to above are metal-semiconductor field effect transistors (MESFETS) which employ a Schottky-barrier diode as the field depletion diode, and junction FETS, which are known and are at present being applied in integrated circuit form. In the applications referred to above, there exists a need for FET circuits which are suitable for connection in cascade.

It is an object of the present invention to provide means for achieving cascade coupling between stages using depletion mode FETS.

According to the invention, cascade coupling is achieved between adjacent stages of a circuit in which a stage includes a depletion mode field effect driver transistor having drain, source, and gate electrodes, and with an active load device connected in the drain circuit of the driver transistor, by means of a capacitive element connected between an output port of one stage and an input port of the adjacent stage.

In an embodiment of the invention there is provided a digital logic circuit suitable for cascade connection, the digital logic circuit including a depletion mode field effect driver transistor having drain, source, and gate electrodes, an active load device connected in the drain circuit of the driver transistor, and a capacitive element coupled to the gate circuit providing an input port of the digital logic circuit.

A cascade of two digital inverters may be provided, each inverter consisting of a deple tion mode field effect driver transistor having an active load device connected in its drain circuit, wherein the cascade includes a capaci tive element coupling the drain circuit of one inverter to the gate circuit of the other inver ter.

The capacitive element may be a capacitor, or it may be a semiconductor diode arranged as a blocking diode. Alternatively, the capaci tive element may be a coupling N-channel depletion mode FET arranged as a blocking diode. There may be a plurality of semicon ductor diodes or coupling FETS connected as the capacitive element.

The active load device connected in the drain circuit of the driver field effect transistor may also be a field effect transistor which may have its gate and source electrodes connected together.

Combinations of driver transistors may be used to give combinatorial logic functions to any inverter.

For steady state operation, an intermediate transistor is introduced into the drain circuit of the or each driver transistor, and, in opera tion, clocked at a rate dependent on the discharge rate of the capacitive element. The circuit will still function with an a.c. input signal when an intermediate transistor is pre sent. A cascade of two digital inverters having intermediate transistors clocked synchro nously, and with a capacitive coupling ele ment, may be provided.

In one embodiment of the invention, dy namic data storage is achieved by providing an intermediate transistor located between the driver transistor and an active load transistor, and clocking the intermediate and load trans istor by means of non-overlapping clock pulses. A dynamic shift register stage is pro vided by means of two dynamic data stores having respective load and intermediate field effect transistors clocked by means of four non-overlapping clock pulses, and having a capacitive element coupling the drain circuit of the first store to the gate circuit of the second store. A bistable flip-flop is obtained when the drain circuit of the second store is in addition capacitively coupled to the gate cir cuit of the first store.

A logic circuit according to the invention and various development thereof will now be described by way of example only and with reference to the accompanying drawings, in which: Figure 1 represents a logic circuit suitable for cascade connection and employing deple tion mode field effect transistors in an inverter with a capacitor at the input port, Figure 2 represents an alternative form of the cascadable logic circuit having a blocking diode as a capacitive element, Figure 3 represents another form of cascadable logic circuit having a depletion mode field effect transistor arranged as a capacitive element, Figure 4 represents a cascade of two inverters employing capacitor coupling, Figure 5 illustrates, as the lower trace, the waveform obtainable at the gate node of the right inverter when the upper trace waveform is applied at the gate node of the left inverter, for Fig. 4, Figure 6 represents a cascade of two inverters having synchronously clocked intermediate transistors in the drain circuits and with an interstage coupling capacitor, Figure 7 illustrates, respectively, a waveform applied at the gate node of the driver transistor of the left inverter, the clock pulses applied to the intermediate transistors, a waveform obtainable at the drain node of the left inverter, and a waveform obtainable at the gate node of the right inverter, for Fig. 6, Figure 8 represents a cascade of two inverters having active load and intermediate transistors clocked by means of non-overlapping four-phase clock pulses and providing a shift register, and Figure 9 represents signals at various points in the cascade of inverters of Fig. 8.

Referring now to Fig. 1, a depletion mode FET logic circuit is shown, the logic circuit consisting of an N-channel field effect driver transistor 1 having a current limiter load 2 connected in its drain circuit and a capacitor 3 connected to its gate circuit and providing an input port to the logic circuit. The current limiter load 2 is provided by a second Nchannel field effect transistor having its gate electrode connected to its source electrode and which therefore operates with zero gate bias in known manner. The logic circuit shown in Fig. 1 may be implemented in monolithic form by forming the driver transistor and the active load using convenional techniques for fabricating integrated circuits and providing either a metal insulator semiconductor capacitor or a metal insulator metal capacitor as the capacitive element.The semiconductor material may be silicon, indium phosphide, or gallium arsenide, and the transistors may employ either a p-n junction gate or a Schottky-barrier gate. Advantageously, in a a monolithic integrated circuit form of the logic circuit, the capacitance of semiconductor diodes may be used as the capacitive element, either as illustrated in Fig. 2 where a blocking diode 4 is shown with its anode electrode connected to the gate circuit of the driver transistor and its cathode electrode providing the input port of the logic circuit or as is shown in Fig. 3 where an N-channel field effect coupling transistor is shown with its drain and source electrodes connected together as the input port and its gate electrode connected to the gate circuit of the driver transistor 1.

Reference may be made to Figs. 4 and 5 in order to understand the characteristics of the logic circuit of the invention, where Fig. 4 shows a cascade of two inverters employing capacitor coupling and in which the capacitor and the right inverter are recognisable as the.

logic circuit of the invention. Fig. 4 when constructed with discrete components may employ type BSV80 transistors for the transistor drivers 1 and 11, type 2N4302 transistors for the active loads 2 and 21, and a 1 00pF capacitor or two type BSV80 transistors for the capacitive element 3. The input signal to the inverter cascade is applied to the gate electrode of the driver transistor 11, the input signal being typically a square wave voltage having upper and lower limits of OV and - 4V respectively, as represented by the upper trace of Fig. 5.When the input voltage changes from OV to - 4V, the node 7 formed by the drain electrode of the driver transistor 11, the active load 2, and the capacitor 3 changes from about to 0/5V driving the node 17 formed by the capacitor 3 and the gate electrode of the driver transistor 1 upwards to about .5V where the gate-source diode of the transistor 1 clamps it by conducting and from which it will drift slowly downward while the driver transistor 1 1 remains switched off.

When the input voltage swings from - 4V to OV, the drain electrode of the driver transistor 11 swings from 5V to about OV, and the gate electrode voltage of the transistor 1 is caused to swing downward to - 2.5V because of the capacitor 3, and will tend to rise very slowly towards zero because of the reverse leakage current of the transistor 1. The leakage current is very small and the transistor 1 will not conduct again before the input signal changes when such a circuit is present in, say a digital communications system, provided the capacitor discharge time constant is much greater than the signal period.

Fig. 6 illustrates a cascade of two clocked inverters with capacitive coupling, the clocking being effected by introducing an intermediate field effect transistor into the drain circuit of each driver transistor and energising the intermediate transistor by means of a clock pulse. Operation of the cascade of clocked inverters with capacitive coupling may be understood by referring to Fig. 7 which shows in sequence from top to bottom, an input square waveform with about a 1:1 mark:space ratio, a clock pulse waveform of frequency roughly twice that of the input ' waveform but having a much shorter pulse length, a waveform obtainable at the drain node of the intermediate transistor of the left inverter, and a waveform obtainable at the gate node of the driver transistor of the right inverter when the circuit is energised by a 5V supply.The intermediate transistors are switched by the same clock pulse. In Fig. 7, the line DD represents a time when the gate electrode of the driver transistor 11 is held at oV, but there is no clock pulse and the gate electrode of the intermediate transistor 81 is held at - 5V, holding-off the intermediate transistor 81 and causing its drain potential to be held at + 5V. The gate electrode 17 of the right driver transistor 1 then remains at about oV. At the time EE a clock pulse is applied to the gate electrode of the intermediate transistor 81, turning it on, and causing its drain potential to drop to about oV. This change is transmitted to the gate electrode 17 of the driver transistor 1 by the capacitor 3, and the potential of the gate electrode 17 falls, turning off the transistor 1.The capacitor 3 discharges slightly during the presence of a clock pulse, and on the termination of the clock pulse, the gate electrode 17 is driven to about oV again, remaining there during the time FF in Fig. 7. During the period DD to FF, the drain electrode of the right intermediate transistor 8 will have remained at + 5V. At the time GG, when the intermediate transistor 8 is switched on, the driver transistor 1 is also switched on, and the drain electrode of the intermediate transistor 8 falls to about oV for the duration of the clock pulse. Therefore the drain potential of the intermediate transistor 8 is valid during each clock pulse, and follows the input potential applied at the gate electrode of the transistor 11, even when the input potential is a d.c. waveform. The circuit will tolerate appreciable leakage of charge from the capacitor 3.The circuit of Fig. 6 may be regarded as a pseudo-static transmission gate which propagates the input signal to its output, provided that the output signal is required only during a clock pulse. The output levels of the circuit shown in Fig. 6 are + 5V and oV, but these may be shifted to oV and - 3V by adding a capacitor and a positive clamp diode to the output circuit. The clamp diode may be the gate-source diode of a depletion mode field effect transistor.

In Fig. 8, a shift register is shown, the shift register being obtained by providing clocked active load devices in the arrangement of Fig.

6, and clocking with no overlap. The operation of the shift register of Fig. 8 may be understood by referring to Fig. 9, in which the vertical lines HH to SS represent the same times at the nodes named to the left of the waveforms.

Referring to Figs. 8 and 9, at a time HH, the input voltage level to the gate electrode of the drive transistor 11 is at oV, the gate electrode of the driver transistor 1 is at about oV, and the output port of the right inverter is at - 3V. The output port of the right inverter is the right plate of the capacitor 13 to which a further gate-source junction would be attached. At a later time JJ, a clock pulse 41 is applied to the gate electrode of the load transistor 121, turning it on and raising the potential level at the left plate of the capacitor 3 to about 5V. The rise in the potential at the left plate of the capacitor 3 is propagated to the gate electrode of the driver transistor 1, but the clamping effect of the gate-source junction holds the potential of the gate electrode of the driver transistor 1 at about oV.

The left plate of the capacitor 3 is therefore charged to + 5V a#nd the right plate is held at about oV. At the time KK, the clock pulse #1 is removed turning off the load transistor 121.

At time LL a clock pulse #2 is provided, turning on the intermediate transistor 81. The left plate of the capacitor 3 is pulled down to about oV, since the driver transistor 11 and the intermediate transistor 81 are both switched on, and the right plate of the capacitor 3 goes down to about - 3V, turning off the driver transistor 1. This change in the state of the driver transistor 1 has no effect at the output port of the right inverter since the intermediate transistor 8 is held switched off, and the situation remains unchanged because all charge remains trapped on the stray and coupling capacitances in the circuit.At the time MM a clock pulse < 1)3 switches on the load transistor 12, thereby pulling the left plate of the capacitor 13 up to about + 5V, and causing the right plate of the capacitor 13 to rise to about oV where it is clamped by the gate-source junction of the next transistor in the cascade. The condition of the circuit remains substantially unchanged for the duration of the clock pulse #3. During the time NN the clock pulse #4 switches on the intermediate transistor 8. Because the driver transistor 1 is already switched off, the left plate of capacitor 13 remains at about 5V and the gate of the right transistor remains at about oV. The original level at the input has now been transferred to the right transistor gate during one complete clock cycle.During a time PP there are no clock pulses present and the circuit does not change its state because all charge remains trapped on the respective stray and coupling capacitors of the circuit. At a time QQ, the input signal to the gate electrode of the drive transistor 11 falls to - 5V, but the change has no effect on the circuit. At some later time RR, another clock pulse 4)1 is introduced at the gate electrode of the load transistor 121, and this causes the left plate of the capacitor 3 to rise to + 5V, and the right plate of the said capacitor to rise to about oV where it is clamped by the gatesource junction of the driver transistor 1. No further change takes place during the arrival and presence of another clock pulse #2 and another clock pulse 4 > 3 because the driver transistor 11 is held switched off, but when another clock pulse #4 arrives at the gate electrode of the intermediate transistor 8, the left plate of the capacitor 13 is pulled down to about oV, and the right plate of the said capacitor falls to about - 3V, and completes a second clock cycle of circuit operation.

The shift register properties of Fig. 8 are illustrated in Fig. 9 by the waveforms identified as the input signal to the gate of the left driver transistor, and the output signal from the output port of the right inverter, from which it can be seen that the said output signal corresponds to the said input signal, displaced by one clock period. The shifting is to be regarded as pseudo-static, since data is stored by being trapped on the effective drain node capacitances of the intermediate transistors of the circuit, and is trasferred between the input and output nodes by the clocking of the driver and the load transistors via the coupling capacitors.

The circuit of Fig. 8 functions as a bistable flip-flop by the connection of its input port to its output port. The condition of bistable operation is present because the input signal appears at the output port with some delay, and the signal is stored when the loop is closed.

In Fig. 9, the time scale is such that a clock period corresponds to about 1.5 microseconds.

A novel family of digital circuits, including a cascade of digital inverters has been described with reference to discrete components as a means of specifying approximate circuit parameters, but the advantages of the circuits are best realised when they are constructed as integrated circuits, particularly as MESFET or d J FET circuits employing galluim arsenide, induim phosphide, or silicon as a semiconductor material.

The advantages include: (i) reduced sensitivity to process parameter variations in respect of all the circuits, (ii) reduced power dissipation because of the use of passive rather than active coupling elements, in respect of all the circuits, (iii) further reduced power dissipation because of the use of clocking, in respect of the circuits of Figs. 6 and 8, and (iv) all transistors may be identical and have dimensions corresponding to the smallest transistors used in prior art circuits, permitting higher packing density, and consequently the choice of higher operating speed or further reduced power dissipation, in respect of the circuit of Fig. 8.

Claims (8)

1. A method of coupling adjacent stages of a digital logic circuit in which a stage includes a depletion mode field effect driver transistor having drain, source, and gate electrodes and with an active load device connected in the drain circuit of the driver transistor, by means of a capacitive element connected between an output port of one stage and an input port of the adjacent stage of the digital logic circuit.

2. A digital logic circuit including a depletion mode field effect driver transistor having drain, source, and gate electrodes, an active load device connected in the drain circuit of the driver transistor, and a capacitive element coupled to the gate circuit providing an input port to the digial logic circuit.

3. A digital logic circuit including cascade of two digital inverters, each digital inverter including a depletion mode field effect driver transistor having an active load device connected in its drain circuit, and a capacitive coupling element coupling the drain circuit of one inverter to the gate circuit of the other inverter.

4. A digital logic circuit as claimed in claim 3, and including, in each digital inverter, an intermediate depletion mode field effect transistor connected in series with the active load device in the drain circuit of the driver transistor, the gate electrode of each intermediate transistor being arranged to provide a control input port.

5. A shift register, comprising a cascade of inverters as claimed in claim 4, wherein the gate electrodes of the active load devices are arranged to provide further control input ports.

6. A digital logic circuit as claimed in any one of claims 2 to 4, wherein the capactive element is a capacitor having a semiconductor oxide or nitride as dielectric material.

7. A digital logic circuit as claimed in any one of claims 2 to 4, wherein the capacitive element is a semiconductor diode arranged as a blocking diode.

8. A digital logic circuit as claimed in any one of claims 2 to 4, wherein the capacitive element is a field effect transistor.