GB2053566A - Integrated circuit package - Google Patents

Integrated circuit package Download PDF

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Publication number
GB2053566A
GB2053566A GB8021575A GB8021575A GB2053566A GB 2053566 A GB2053566 A GB 2053566A GB 8021575 A GB8021575 A GB 8021575A GB 8021575 A GB8021575 A GB 8021575A GB 2053566 A GB2053566 A GB 2053566A
Authority
GB
United Kingdom
Prior art keywords
integrated circuit
circuit package
package
socket
die
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB8021575A
Other versions
GB2053566B (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CTU of Delaware Inc
Original Assignee
Mostek Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mostek Corp filed Critical Mostek Corp
Publication of GB2053566A publication Critical patent/GB2053566A/en
Application granted granted Critical
Publication of GB2053566B publication Critical patent/GB2053566B/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K7/00—Constructional details common to different types of electric apparatus
    • H05K7/02—Arrangements of circuit components or wiring on supporting structure
    • H05K7/10—Plug-in assemblages of components, e.g. IC sockets
    • H05K7/1053—Plug-in assemblages of components, e.g. IC sockets having interior leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/107—Indirect electrical connections, e.g. via an interposer, a flexible substrate, using TAB
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An integrated circuit package is provided with a socket arrangement into which a second integrated circuit package may be plugged. In a first embodiment metallization patterns 22 are used to electrically interconnect the first integrated circuit package 10 to a conventional printed wiring board or ceramic wiring board 26 containing socket contacts 28 to receive lead pins from another integrated circuit package. A second embodiment is a unitized package containing integral socket contacts within the unitized integrated package to receive lead pins from another integrated circuit package. <IMAGE>

Description

SPECIFICATION Integrated circuit package This invention relates to integrated circuit packages and more particularly, but not by way of limitation, to integrated circuit packages which may support more than one integrated circuit.
Certain electronic applications or methods require functional electronic coperation between two or more integrated circuits. For example, functional electronic cooperation is often required between an integrated circuit microprocessor die and an integrated circuit electrically programmable/ultraviolet erasable read only memory (EPROM) die. With certain electronic applications, a critical design objective is reducing the amount of area space required to conduct certain electronic functions.
One method used by the prior art to reduce the amount of required area space has been to incorporate the cooperative electronic functions of a microprocessor and an EPROM on a monolithic integrated circuit that is placed into an integrated circuit package. Using this method, the EPROM may be erased using ultraviolet light transmitted through a window in the lid of the integrated circuit package. This method has proven to be very expensive due to the low die per wafer yield resulting from manufacturing two electronic circuit functions on the same, large monolithic integrated circuit die and also because of the large, special window lid required.
One other prior art method is the simple stacking of integrated circuit packages. This method does not provide interconnects in a single package.
Advantages of the present invention include the use of two die rather than one which provides better reliability and yield. Further, more than one type of EPROM may be used with the same microprocessor. Also, one socket set and interconnections are eliminated thereby decreasing board area and costs. Finally, the overall field retrofit/repair capability is increased.
The present invention allows the use of separate die while still achieving the same goal of reducing space requirements. By way of example, the present invention allows for the use of separate EPROM and microprocessor die while achieving the requirement of reducing area space.
With the present invention, the use of two die rather than one provides for increased die per wafer yields and improved electronic application flexibility by allowing more than one type of EPROM to be used with the same microprocessor die. The first embodiment is a two-piece integrated circuit package. The first piece contains a region in which a microprocessor die may be placed and interconnected to a metallization pattern. The second piece is comprised of a nonconductive material, such as ceramic or PC board material, having socket contacts, connected with metallization patterns which will accept the pins of a separate integrated circuit package.
A microprocessor die may be mounted in a ceramic integrated circuit package provided with means to electrically receive a second integrated circuit package. A second separate integrated circuit package containing an EPROM die assembled using techniques and skills recognized in the art can then be inserted into the socket contacts of the microprocessor package to produce electrical interconnection between the integrated circuits.
A second embodiment is a unitized integrated circuit package containing integral interconnection conductors and socket contacts. These components are dielectrically separated within the integrated package. In this embodiment a microprocessor die may be assembled and hermetically sealed into a ceramic integrated circuit package using techniques and skills recognized in the art. A separate integrated circuit package assembly containing an EPROM die may then be inserted into the integral socket contacts to produce electrical interconnection between the integrated circuits.
Preferred embodiments of the invention will now be described with reference to the accompanying drawings, in which:~ FIGURE 1 shows a perspective exploded view of a two-piece integrated socket package embodying the present invention; and FIGURE 2 is a perspective exploded view of a one-piece integrated socket package embodying the present invention.
With reference to FIGURE 1, a preferred embodiment of the invention includes an integrated circuit package 10 with a die-cavity 12.
The integrated circuit package body may be ceramic or other material that is not conductive.
Typically a microprocessor unit or other integrated circuit on a die 13 is placed in the die-cavity 12.
Bonding finger pads 14 are shown to connect the die 13 by the interconnecting conductors 15. The bonding finger pads 14 are also interconnected with the external lead pins 16. A lid 18 is also shown ready to be attached to the package by lid seal metallization 20.
The integrated circuit package 10 is provided with a first metallization pattern 22 on its top surface. This metallization pattern may typically be composed of conductors and solder pads. A second metallization pattern 24 is provided on the bottom surface of the socket board 26 to match the first metallization pattern 22, thereby capable of interconnecting the integrated circuit package 10 and the socket board 26. The electrical interconnection between the ceramic integrated circuit package and conventional printed wiring or ceramic wiring board may be accomplished using such recognized techniques as alloy or elemental fusion reflow, conductive elastomeric or conductive particles combined with adhesive bonding substances. The body of socket board 26 is preferably nonconductive multilayered.
As shown, there are metalized interconnects 27 from the second metallization pattern 24 to the socket contacts 28. A separate integrated circuit package, not shown, such as an EPROM on its own die, may then be plugged into these receptacles, providing a single space integrated circuit package comprised or a microprocessor and an EPROM which is interchangeable or may be removed multiple times for programming.
Note that the socket board 26 shown has a notch 30 to fit over the lid 1 8. The same effect can be similarly achieved by raising the first metallization pattern 22 slightly to meet the second metallization pattern 24. In this manner the socket board 26 can be a uniform board and no notch is required.
Referring now to FIGURE 2, the second embodiment of the invention is shown. A single integrated circuit package 32 is used to provide a unitized socket and integrated circuit package. A die-cavity 12 with interconnections or bonding wires 15 is shown connecting the die 13 to the bonding pads 14. The bonding pads 14 lead to external lead pins 16. The lid 18 covers the circuit package cavity. Socket contacts 28 are further spaced on the package 32 to receive a separate integrated circuit package. The socket pin contacts 28 are interconnected to the bonding pads 14.
Typically the socket contacts 28 will be spaced between the leads 16. The leads 16 may be side mounted as the FIGURE 1 or may be bottom or top mounted as shown in FIGURE 2. Further, when bottom mounted, leads 16 may be formed with an angular portion between the vertical contact portion and the horizontal portion attached to the package. This provides further room and spacing for the socket contacts 28.
While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended

Claims (14)

claims. CLAIMS
1. An integrated circuit package comprising: (a) a first integrated circuit package having an integrated circuit die mounting means and external lead pins, (b) a first metallization pattern on the top surface of the first integrated circuit package, interconnected to the die mounting means, (c) a socket board having socket contacts to receive a second integrated circuit package, and (d) a second metallization pattern on the bottom surface of the socket board to match the first metallization pattern and interconnect the first integrated circuit package and socket board.
2. The integrated circuit package of Claim 1 wherein the first metallization pattern is raised.
3. The socket board of Claim 1 wherein the second metallization pattern is raised.
4. An integrated circuit package comprising: (a) a first multilayer integrated circuit package having a die cavity, bonding finger pads, a die cavity lid, and external lead pins, (b) a first metallization pattern on the top surface of the first integrated circuit package, (c) a socket board having socket contacts to receive a second integrated circuit package, and (d) a second metallization pattern on the bottom surface of the socket board to match the first metallization pattern and interconnect the second integrated circuit package and socket board.
5. An integrated circuit package comprising: (a) a first integrated circuit package having a die mounting means and external lead pins, (b) a socket board having socket contacts to receive a second integrated circuit package, and (c) means for interconnecting the second integrated circuit package and socket board.
6. The integrated circuit package of Claim 5 wherein the body of the socket board is nonconductive multilayered.
7. The integrated circuit package of Claim 5 wherein the socket board is recessed on its bottom surface to provide a notched area about the lid area on the top surface of the first integrated circuit package.
8. A unitized integrated circuit package comprising: (a) a package having a die mounting means and external lead pins, and (b) a plurality of integral socket contacts for receiving an integrated circuit package.
9. The unitized integrated circuit package of Claim 8 wherein the leads are bottom mounted.
10. The unitized circuit package of Claim 9 wherein the plurality of socket pins are spaced between the leads.
11. The unitized integrated circuit package of Claim 10 wherein the leads are formed into a vertical contact portion, a bottom mounted horizontal portion, and a bent portion between the vertical contact portion and the horizontal portion whereby increased spacing is provided between the socket contacts and leads.
12. A unitized integrated circuit package comprising: (a) a supporting package, (b) a die cavity in the package, (c) bonding finger pads for connecting an integrated circuit die, (d) a die cavity lid for sealing the integrated circuit die, (e) external lead pins interconnected with the bonding finger pads, and (f) socket contacts spaced in the supporting package and interconnected with the bonding finger pads to receive an integrated circuit package.
13. An integrated circuit package substantially as herein described with reference to Fig. 1 of the accompanying drawings.
14. An integrated circuit package substantially as herein described with reference to Fig. 2 of the accompanying drawings.
GB8021575A 1979-07-02 1980-07-01 Integrated circuit package Expired GB2053566B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US5387979A 1979-07-02 1979-07-02

Publications (2)

Publication Number Publication Date
GB2053566A true GB2053566A (en) 1981-02-04
GB2053566B GB2053566B (en) 1984-05-02

Family

ID=21987178

Family Applications (1)

Application Number Title Priority Date Filing Date
GB8021575A Expired GB2053566B (en) 1979-07-02 1980-07-01 Integrated circuit package

Country Status (2)

Country Link
JP (1) JPS5649551A (en)
GB (1) GB2053566B (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1984002613A1 (en) * 1982-12-20 1984-07-05 Motorola Inc Integrated circuit carrier and assembly
US4617216A (en) * 1980-08-07 1986-10-14 Gao Gesellschaft Fur Automation Und Organisation Mbh Multi-layer identification card
EP0298219A2 (en) * 1987-06-08 1989-01-11 Tektronix Inc. Method and apparatus for testing unpackaged integrated circuits in a hybrid circuit environment
EP0486829A2 (en) * 1990-10-22 1992-05-27 Seiko Epson Corporation Semiconductor device and semiconductor device packaging system
EP0605982A2 (en) * 1992-12-28 1994-07-13 AT&amp;T GLOBAL INFORMATION SOLUTIONS INTERNATIONAL INC. Multi-chip module board
US5376825A (en) * 1990-10-22 1994-12-27 Seiko Epson Corporation Integrated circuit package for flexible computer system alternative architectures

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60259935A (en) * 1984-06-07 1985-12-23 Komatsugawa Kakoki Kk Turbidity meter

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4617216A (en) * 1980-08-07 1986-10-14 Gao Gesellschaft Fur Automation Und Organisation Mbh Multi-layer identification card
WO1984002613A1 (en) * 1982-12-20 1984-07-05 Motorola Inc Integrated circuit carrier and assembly
EP0298219A2 (en) * 1987-06-08 1989-01-11 Tektronix Inc. Method and apparatus for testing unpackaged integrated circuits in a hybrid circuit environment
EP0298219A3 (en) * 1987-06-08 1990-08-01 Tektronix Inc. Method and apparatus for testing unpackaged integrated circuits in a hybrid circuit environment
EP0486829A2 (en) * 1990-10-22 1992-05-27 Seiko Epson Corporation Semiconductor device and semiconductor device packaging system
EP0486829A3 (en) * 1990-10-22 1993-10-27 Seiko Epson Corp Semiconductor device and semiconductor device packaging system
US5376825A (en) * 1990-10-22 1994-12-27 Seiko Epson Corporation Integrated circuit package for flexible computer system alternative architectures
EP0605982A2 (en) * 1992-12-28 1994-07-13 AT&amp;T GLOBAL INFORMATION SOLUTIONS INTERNATIONAL INC. Multi-chip module board
EP0605982A3 (en) * 1992-12-28 1994-07-27 Ncr Int Inc Multi-chip module board.

Also Published As

Publication number Publication date
JPS5649551A (en) 1981-05-06
GB2053566B (en) 1984-05-02

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