GB2053537A

GB2053537A - Digital Computing Apparatus

Info

Publication number: GB2053537A
Application number: GB8021148A
Authority: GB
Original assignee: Lucas Industries Ltd
Current assignee: ZF International UK Ltd
Priority date: 1979-07-10
Filing date: 1980-06-27
Publication date: 1981-02-04
Also published as: GB2053537B

Abstract

A digital computing apparatus has two digital computing devices and a digital memory, interconnected by a data bus. Each computing device includes a controlling clock and these clocks may have different operating frequencies. A synchronising interface unit allows one of the computing devices to obtain access to the memory only during predetermined cyclic states of the clock of the other device.

Description

SPECIFICATION Digital Computing Apparatus This invention relates to digital computing apparatus. It may be required to provide a computing apparatus in which separate digital computer devices which are controlled by their own respective clocks are required to co-operate in a manner which requires the transfer of data between the devices and in which both devices have access to data stored in a single memory. If the clocks of the respective devices have different frequencies, difficulties arise in ensuring that only one of the computer devices can obtain access to the memory at any one time.

It is an object of the present invention to provide an apparatus by means of which two digital computing devices may, without mutual interference, have access to one memory, even when these devices include respective controlling clocks which have different frequencies.

It is a further object of the invention to provide an apparatus in which access to the memory by one of said computing devices is controlled by the clock of said one device, access to the memory by the other device being constrained to occur at times when data is not being transferred between said one device and the memory.

In an apparatus of the present invention these results are obtained by providing that the first of the computing devices obtains access to the memory during one half cycle only of its clock pulses, and arranging that the second computing device obtains access to the memory during the other half cycle of a clock pulse from the first device. For this purpose a modified clock signal derived from the clock pulses of the second device is provided in response to a requirement by the second device to obtain access to the memory. The second device obtains the aforesaid access in response to a control signal which is responsive to coincidence between the modified clock signal and the aforesaid other half cycle of a clock pulse from the first computing device.

According to the invention a digital computing apparatus comprises a first digital computing device including a controlling clock for generating pulses of a first frequency, a second digital computing device including a controlling clock for generating pulses of a second frequency, a memory, a data bus interconnecting said devices and said memory, synchronising means responsive to a signal indicative of a requirement by said second device to obtain access to said memory and also responsive to a predetermined cyclic state of the clock pulses from said first device, for generating a control signal of a duration which lies within the period of one of said predetermined cyclic states, and selector means responsive to said control signal for allowing access to said memory by said second device for the duration of said control signal, and for allowing access to said memory by said first device at all other times.

In a preferred embodiment said selector means comprises a multiplexing circuit for address and data signals from said first and said second computer devices.

In a further preferred embodiment said synchronising means includes means for delaying the start of said control signal for a predetermined period after the beginning of one of said predetermined cyclic states.

An embodiment of the invention will now be described by way of example only and with reference to the accompanying drawings in which:~ Figure 1 is a block diagram of a fuel flow control system for an engine, Figure 2 is a block diagram of a calibration apparatus for parts of the system of Figure 1, Figure 3 is a block diagram of a fuel flow test rig forming part of the apparatus of Figure 2, Figure 4 is a block diagram of a digital computer forming part of the apparatus of Figure 2, Figure 5 is a diagram of an interface unit forming part of the computer of Figure 4, Figure 6 shows a synchronising circuit forming part of the interface unit of Figure 5, Figure 7 shows delay circuit forming part of the test rig of Figure 3, Figure 8 shows the signal pulses present at several locations of the circuits shown in Figures 5 and 6, Figure 9 shows the time relationship between clock pulses and address and data signals from a conventional digital computing device, and Figure 10 shows how the relationship shown in Figure 9 is modified by the delay circuit of Figure 7.

Figure 1 shows a fuel flow control system for an engine 10, the flow control system corresponding generally to that described in British patent application 41906/78. The system includes a pump 11, a variable metering device 1 2 which is responsive to an engine intake pressure P 1, a servo pressure operated throttle valve 13 in series with the device 12, a servo pressure control 14 which is responsive to a pressure difference across the metering device 12 and to electrical signals from a control circuit 15.

The control circuit 15 is responsive to engine temperature T, intake pressure P1 and a signal 0 which corresponds to an angle of incidence between the fore and aft axis of the engine 10 and its direction of movement through the surrounding atmosphere. The circuit 15 includes a digitial microprocessor unit (mpu) 16 which is controlled by a clock 17 and which has a programmable read-only memory (prom) and which also includes an analog to digital converter for the input signals T, P1, 0 and also a digital to analog converter for providing output signals to the servo pressure control 14.

In the above system the throttle valve 13 assumes full control of fuel flow at predetermined levels of 0 and T, subsequent control being in accordance with 0, T and P1. In order that fuel flow shall, in these conditions, correspond accurately to that required for the sensed input values, in spite of tolerances in the hydromechanical and electromechanical components of the throttle 13 and servo pressure control 14, it is necessary to calibrate the system.

The calibration apparatus shown generally in Figure 2 includes a fuel flow test rig, indicated generally at 20, and described in more detail with reference to Figure 3. The rig 20 includes a metering device 12, throttle valve 13, servo pressure control 14 and circuit 15 from the fuel system to be calibrated. The apparatus of Figure 2 further includes a computer 21, described in more detail with reference to Figures 4, 5 and 6 and having an input/output control panel 22 which may include a printer 19 for providing a record of calibrations supplied from the computer 21.

As shown in Figure 3, and as previously indicated, the test rig 20 includes the circuit 15 and a flow control 25 which includes the devices 12, 13 and 14 previously described. The flow control 25 is supplied with fuel from a tank 26 by a positive displacement pump 27, by way of an accumulator chamber 39 and a fuel pressure regulator 28 which is controlled by an analog electrical signal on line 29 from the computer 21, and which provides a fuel delivery pressure signal PD on a line 30 to the computer 21. Excess fuel is returned to the tank 26 through a non-return valve 40.

The flow control 25 and circuit 15 are responsive to a test air pressure which corresponds to pressure P1 and which is derived from pressure sources 31,32 by a pressure regulator 33 which is responsive to an analog signal on line 34 from the computer 21. A transducer 35 provides a signal Plt on a line 36 indicative of the magnitude of the test air pressure. The computer 21 provides an analog test signal Ot, corresponding to the aforementioned incidence signal 0, on a line 37 to the circuit 15. An air heater 38 provides a temperature signal Tt, corresponding to the aforementioned engine temperature T.

As shown in British Patent 41906/78 the fuel flow control 25 has four outlet passages 41, and in the test rig 20 flow from these passages is combined to pass through a mass flow meter 42 before return to the tank 26. The flow meter 42 provides an analog output signal on a line 43 to the computer 21. A buffer circuit 44 is interposed in an address and data bus 45 and in a plurality of control lines 46 between the control circuit 15 and the computer 21. The buffer circuit 44 includes a delay circuit 47, later to be described with reference to Figure 7.

As shown in Figure 4 the computer 21 includes a microprocessor 50, a random access memory (RAM) 51 and a programmable read-only memory.

(PROM) 52. The signals on lines 29, 34 and 37 are provided from the microprocessor 50 through an analog output circuit 53. The input signals on lines 30, 36 and 43 pass to the microprocessor 50 through an analog input circuit 54.

The RAM 51 is accessible to the microprocessor 16 in the circuit 15. This access is controlled by an interface unit 55, to be described in more detail with reference to Figures 5 and 6.

The interface unit 55 communicates with the microprocessor 1 6 by way of the bus 45 and with the microprocessor 50 by way of a bus 57.

Signals between the control panel 22 and microprocessor 50 pass through an input/output circuit 56 and a programmable read-only memory programmer circuit 58. The microprocessor 50 includes a clock 59.

In the present example the clock 59 has a frequency of 1 MHz and the clock 17 in the fuel system control circuit 15 has a frequency of .9MHz. it is necessary that the RAM 51 is accessible by only one of the microprocessors 1 6 or 50 at any time. It is also required that the output of the circuit 15 shall not be interrupted, whereby access to the RAM 51 by the microprocessor 50 may be permitted only in those intervals in which access by the circuit 1 5 does not occur.

As shown in Figures 5 and 6 the interface unit 55 includes an address and data multiplexer 60, of the type available from Texas Instruments under the designation SN 74LS1 58N, for controlling flow of addresses and data on the buses 45 and 57 to and from the RAM 51 on a bus 61. Since the circuit 15 is required to operate uninterruptedly, it is arranged that normal operation of the multiplexer 60 is such that the microprocessor 16 can obtain access to the RAM 51. The multiplexer 60 is responsive to a signal (L) on a line 62 from a synchronising circuit 63, shown in more detail in Figure 6. The circuit 63 is responsive to a pulse train (A) on a line 64. This pulse train (A) is derived from the pulses (A) of the clock 17 in the circuit 15, in a manner to be described.The circuit 63 is also responsive to signals (C) and (F) on respective lines 66, 65, Signal (C) is provided by an AND gate 67 when signals on lines 68, 69 indicate that the microprocessor 50 requires to address the RAM 51, and that the required address is valid. If necessary a pulse train (B) on a line 70 from the clock 59 of the microprocessor 50 is applied to the clock terminal of a D-type bistable 71 through an inverter 72. The D terminal of the bistable 71 is responsive to a signal (D) on a line 73 from the synchronising circuit 63. The signal at the Q output of the bistable 71 is applied, together with the (B) signal on line 70, to a NAND gate 74, to provide the signal (F) on the line 65. The arrangement of the bistable 71, inverter 72 and gate 74 is such that when the signal (D) on line 73 is high, the signal (F) on line 65 is the inverse of the signal (B) on line 70 from the clock 59 and that when the signal (D) on line 73 is low the signal (F) on line 65 is maintained high, commencing at the next subsequent low level of the signal (B). This relationship of the signals is seen more clearly in Figure 8.

As shown in Figure 6 the synchronising circuit 63 includes 3D-type bistables 80, 81, 82 each of which forms part of a dual unit of type number SN74LS74AN, three monostables 83, 84, 85 each of which forms part of a dual unit of type number SN74LS123N, two AND gates 86, 87, a NAND gate 88 and an inverter 89. The (F) and (C) signals on lines 65, 66 are applied to AND gate 86, whose output is applied to the D input of the bistable 80. The clock input of bistable 80 is supplied with the pulse train (A) on the line 64.

Pulses (H) at the Q output of the bistable 80 are applied to the B input of the monostable 83, to provide, at the Q output of the monostable 83, low-going pulses (J) of a predetermined duration, the pulses (J) being applied to the B input of the monostable 84, to an inverting preset terminal PR of the bistable 81 and to an inverting clear terminal CLR on the bistable 82. The (J) signal at the B input of monostable 84 provides a high pulse (K) of predetermined duration at its Q output, and a low pulse of corresponding duration at the Q output.The pulse (K) is applied on a line 90 to a selector circuit 91 (Figure 5) whose outputs on lines 129 cause the RAM 51 to be placed in a state in which data may be entered or obtained, which effective comprises gates which are selectively responsive to the pulse (K) or a low level timing signal on a line 128, to provide signals on lines 129 which cause the RAM 51 to be placed in a state in which data may be entered or obtained. The signal on line 128 indicates that a valid address in the RAM 51 has been selected by the microprocessor 16, and this timing signal is extended, in a manner to be described, by the delay circuit 47.

A pulse at the Q of the monostable 84 is applied to the clock terminal CK of the bistable 81, whose D terminal is maintained at a low level.

A "reset" pulse can be applied on a line 92 to the clear terminal CLR of the bistable 81, to an inverting preset terminal PR of the bistable 82, and also to one input of the AND gate 87. The output of the AND gate 86 is applied through the inverter 89 to the clock input CK of the bistable 82, whose D input is maintained at a high level. A pulse at the Q output of bistable 82 is applied to the other input of the AND gate 87, whose output is applied to the clear terminal CLR of the bistable 80 and to the CLR terminal of the monostable 85.

The B input of the monostable 85 is responsive to the (C) pulses on the line 66. The NAND gate 88 has as inputs the (C) pulse on line 66 and the pulses at the Q output of the monostable 85. The low level output signals on the line 73 from NAND gate 88 provide the (D) pulses on line 73 to the bistable 71 in Figure 5.

The circuits shown in Figures 5 and 6 provide pulses as shown in Figure 8, which indicates the signal sequence by means which access to the RAM 51 by the microprocessor 50 is initiated during a high-level portion of the pulses (A) and also during a low-level portion of those pulses. It is arranged that the microprocessor 1 6 shall have access to the RAM 51 when the pulses (A) derived from the clock 17 are at a low level. The microprocessor 50 may therefore be permitted to have access to the RAM 51 only when the pulses (A) are at a high level. When the signals on lines 68, 69 indicate that a valid address for the RAM 51 has been selected by the microprocessor 50, the signal (C) on line 66 goes high at a time t1, as shown in Figure 8. The signal (C) generates a high level pulse at the Q output of the monostable 85, causing the signal (D) on line 73 to go low.As previously indicated, the low (D) signal at time t1 at the D input of bistable 71 causes the (F) signal on line 65 to be maintained high, commencing at the next low-going part of the pulses (B). At time t2 the next high going part of pulses (A) on line 64 produces the pulse (H), causing the monostable 83 to provide the low-going pulse (J) at its Q output, the pulse (J) persisting until time t4. The low-going pulse (J) also sets the Q output of the bistable 81 to provide the pulse (L) on line 62 to the multiplexer 60, allowing the address on the bus 57 from the microprocessor 50 to be applied to the RAM 51. The pulse (J) also clears the bistable 82, causing the output signal (N) of AND gate 87 to become low at a time t3 which is slighly later than time t2, as a result of delays imposed by operation of the bistable 82 and the gate 87.The low level signal (N) clears the monostable 85, setting the output (D) of the NAND gate high, also at time t3.

The monostable 85 will also clear at a preset interval (e.g. 4 microseconds) after time t1, so that the signal (D) will become high after this preset interval, even in the absence of pulse (A) on line 64. The signal (N) is also applied to the clear terminal CLR of bistable 80 and terminates the (H) pulse at time t3. For the duration of the low period of signal (N) the combination of a high portion of pulses (A) and the signal (C) will not result in initiation of signals (H), (J), (L) or (K).

When the signal (J) goes high at time t4, the signal (K) on line 90 goes high until time t5, during which period the microprocessor 50 can obtain access to the ram 51. At time t5 the 0 signal from monostable 84 causes the bistable 81 to send the signal (L) low.

The pulse (K) enables access to the ram 51 to be obtained, after the multiplexer 60 has been set by the signal (L) to allow an address and data to be sent to the RAM 51 from the microprocessor 50, and the pulse (K) occurs wholly within a high level of the pulses (A), that is during a time in which access to the RAM 51 by the microprocessor 16 is not required. The arrangement thus provides that when the microprocessor 50 requires access to the RAM 51, this access can be obtained during the next high level of the pulses (A) even though the frequency of the clock 17 is different from that of the clock 59.

It will, however, be apparent that the apparatus would be equally effective if the clocks 1 7, 59 have the same frequencies but are of different phase. The apparatus moreover, may also be used for controlling access to stored information by devices having clock pulses of identical frequency and phase.

Since the test rig 50 of Figure 2 includes the engine fuel control of Figure 1, and the computer 21 is a separate item of equipment, it is convenient that they are interconnected by electrical cables which provide the bus lines 45 and control lines 46. Information passing between the microprocessor 16 and RAM 51 is, as previously indicated, under control of pulses (A) from the clock 17 in the microprocessor 16.

As indicated in Figure 9, address information 100, which is provided by the microprocessor 1 6 at the beginning of a low-going part of the pulse train (A) from the clock 17, does not stabilize for approximately 275 nanoseconds thereafter. Data 101 to be supplied to an indicated address is provided at the beginning of a high going portion of the clock pulse train, but does not stabilize for approximately 225 nanoseconds thereafter. Both the address information 100 and data 101 persist for a period which cannot be assumed to exceed 20 nanoseconds after the beginning of the next low going part of the pulse train (A).

Delays imposed by a cable length of, for example, 6 metres will be at least 20 nanoseconds, and this delay may vary from line to line of the address and data bus 45. Synchronism, at the computer 21, of the information on the bus 45 and the clock pulses on one of the lines 46 cannot therefore be guaranteed, and this information may have become inaccurate before the end of the pulse (L) which controls its access to the RAM 51.

In the present invention any such lack of synchronism is prevented from affecting transfer of information, by retaining this information on the bus 45 for a predetermined period after the end of the high part of the clock signal (A).

As previously described the clock 1 7 has a frequency of .9MHz, whereby each half cycle of the pulse train (A) has a duration of approximately 550 nanoseconds. As shown in Figure 7 the delay circuit 47 includes an inverter 110 responsive to the pulses (A) from the clock 17, these pulses being re-inverted by an inverting buffer 111, and transmitted to the interface unit 55 (Figure 4) on a line 121 which forms one of the lines 46. The output from the inverter 110 is also applied to the preset terminal PR of a D-type bistable 112 whose D terminal is maintained at a low potential and whose Q output is connected to one input of a NAND gate 113. The other input of the NAND gate 11 3 is connected to the output of the inverter 110.The output of the NAND gate 113 is connected to one input of each of two NAND gates 114, 11 5. The other input of the NAND gate 11 5 is provided by the output of an inverter 11 6 whose input is provided by a control signal on a line 117 which indicates that the microprocessor 16 has selected a valid address in the RAM 51. The other input of the NAND gate 114 is provided through an inverter 11 8 which is supplied by the output of the inverter 11 6. A bistable 11 9 has its preset terminal PR and clear terminal CLR supplied with output signals from the NAND gate 115 and NAND gate 114 respectively.An inverting buffer 120 is supplied from the 0 output of the bistable 11 9, and the output terminal of gate 120 communicates with a line 128 which forms one of the lines 46.

The signal on line 121 is applied to an inverting buffer 122 which forms part of the interface unit 55 (Figure 5), the output of buffer 122 providing the (A) signal on the line 64. Also as shown in Figure 5 the (A) signal is further modified by successive inverters 123, 124, 125 to provide a signal (P) which is returned to the delay circuit 47 by a line 126 which forms one of the lines 46. In the circuit 47 the (P) signal is applied, through an inverting buffer 127 to the clock terminal of the bistable 112.

Thus as indicated in Figure 10, a high going part of the pulse train (A) from the clock 17 sets the signal (R) at the output Q of the bistable 112 to a high level. The high going part of the returned signal (P) is delayed by 100 nanoseconds as a result of its transit through the lines 121, 126, inverters 123, 124 and buffers 122, 125. The (R) signal is thus set low by the (P) signal approximately 100 nanoseconds after the pulse train (A) from the clock 17 goes low.The (R) signal at the Q output of the bistable 112 is maintained high for 100 nanoseconds after the (A) pulse train has gone low, and (S) pulse output of NAND gate 113 ensures that the "valid address" control signal (T) on line 117 is extended for the additional 100 nanoseconds, and is applied as a timing signal (V) through a line 128 to the selector circuit 91 (Figure 5) to maintain a read/write signal on one of a- plurality of control lines 129 to the RAM 51. The timing signal (V) on line 128 is also applied to the remainder of the buffer circuit 44 to maintain the data on the bus 45 for an additional 100 nanoseconds.

The address and data from the microprocessor 16 are thus available to the RAM 51 for an additional period which is indicative of the time taken for a pulse from the clock 17 to pass to the computer 21 and to be returned to the circuit 47.

As indicated in Figure 10, both the address and data from the microprocessor 16 are available to the RAM 51 during a high level part of the pulse train (A), that is during a low level part of the pulse train (A). The microprocessor 50 may thus have access to the RAM 51 for periods which lie wholly within the high level parts of the pulse train (A) as indicated in Figure 8. It will be seen from Figure 1 p that extension by 100 nanoseconds, by means of the pulse (S), of the time during which address information and data from the microprocessor 16 are present on the bus 45 causes this information and data to be extended into the period of the next subsequent low level part of the pulse train (A). However, as indicated above, new address information initiated by the microprocessor 1 6 at the low going edge of the pulse train (A), does not stabilise for approximately 275 nanoseconds thereafter. Address information and data may thus be retained in the buffer circuit 44 during the stabilisation interval of the microprocessor 16, without prejudice to the next succeeding data and information.

The use of the delay introduced by the lines 121, 126 in addition to the fixed delays imposed by the components 122, 123, 124, 125 and 127, has the effect that any increase in the lengths of the lines 121, 126 results in a corresponding increase in the duration of the pulses (S).

Claims

1. A digital computing apparatus comprising a first digital computing device including a controlling clock for generating pulses of a first frequency, a second digital computing device including a controlling clock for generating pulses of a second frequency, a memory, a data bus interconnecting said devices and said memory, synchronising means responsive to a signal indicative of a requirement by said second device to obtain access to said memory and also responsive to a predetermined cyclic state of the clock pulse from said first device, for generating a control signal for a duration which lies within the period of one of said predetermined cyclic states, and selector means responsive to said control signal for allowing access to said memory by said second device for the duration of said control signal, and for allowing access to said memory by said first device at all other times.

2. A digital computing apparatus as claimed in claim 1 in which said synchronising means includes means responsive to said predetermined cyclic state for generating a second control signal of a duration within said period of one of the predetermined cyclic states, said second control signal commencing before said first control signal, and a further selector means responsive to said second control signal for permitting signals on said bus to pass between said second device and said memory.

3. A digital computing apparatus as claimed in claim 2 in which said further selector means comprises a multiplexing circuit located in said data bus between said memory and said first device and between said memory and said second device.

4. A digital computing apparatus as claimed in claim 2 or claim 3 in which said synchronising means includes means, responsive to a predetermined cyclic state of the pulses of said second frequency and to said signal indicative of the requirement of said second device for access to said memory, for generating a third control signal, and means responsive to said third control signal and to said predetermined cyclic state of the pulses of said first frequency for initiating said first and second control signals.

5. A digital computing apparatus as claimed in any preceding claim in which said first selector means is selectively responsive to said first control signal or to a timing signal from said first device.

6. A digital computing apparatus as claimed in claim 5 which includes means responsive to an indication from said first device of the generation thereby of a valid address in said memory, and to another cyclic state of the pulses of said first frequency, for generating said timing signal of a duration which is equal to the sum of the duration of said valid address indication and at least the transit time of data on said bus between said first computing device and said memory.

7. A digital computing apparatus as claimed in claim 6 in which said synchronising means is located adjacent said memory, and there is provided a series circuit extending between said first computing device and said synchronising means, and having both of its ends in said first computing device, means for supplying to one end of said series circuit a fourth control signal indicative of a beginning of said other cyclic state of the pulses of said first frequency, means for initiating said timing signal at the beginning of said valid address indication, and for terminating said timing signal on receipt of said fourth control signal at the other end of said series circuit.