GB2051433A - Interface device for a digital data processing system - Google Patents

Abstract

An interface device (1) for transferring digital data between an electronic digital data processor (2) and interface connections (3) providing eight ports (4), the processor including a main memory (7) connected to a multi-line main data buss (5). The device (1) includes an ancillary data buss (9) having the same number of lines as the main data buss, a first buffer for transferring data between the two busses (5 and 6), a second buffer for transferring data between the ancillary buss and the interface connections, an ancillary memory (10) connected to the ancillary buss, and control means (11) having a fixed sequence program for effecting transfer of data between the ancillary buss and the main and ancillary memories so as to transfer data between the main memory and the interface connections. A multi-line connection (13) interconnects an address buss (6) in the processor (2) and the control means (11). Logic control signals pass between the processor (2) and control means (11) on lines (14-22). <IMAGE>

Description

SPECIFICATION Interface device for a digital data processing system THIS INVENTION relates to a device for forming an interface between an electronic digital data processing system and a plurality of interface connections. In particular, the interface device of the invention is intended to enable the transfer of data between a data processing system having a multi-line data buss for parallel transfer of data within the system and interface connections which include connections for the serial transfer of data. For example, the interface device may enable data transfer between the data processing system and Post Office modems and the dialled telex network.

The invention also concerns an arrangement for implementing conditional execution of program steps during a fixed sequence program.

In accordance with the first aspect of the invention, there is provided an interface device for transferring digital data between an electronic digital data processing system and interface connections which include connections for the serial transfer of data, the processing system including a main memory connected to a multi-line main data buss for the parallel transfer of data within the processing system, the interface device including an ancillary data buss having the same number of lines as the main data buss, a first buffer connected to the ancillary data buss and for connection to the main data buss for transferring data between the two busses, a second buffer connected to the ancillary data buss and for connection to the interface connections for transferring data between the ancillary buss and the interface connections, an ancillary memory connected to the ancillary data buss, and control means having a fixed sequence program for effecting transfer of data between the ancillary buss and each of the main and ancillary memories so as to transfer data between the main memory and the interface connections.

In an embodiment of the invention, the processing system includes a multi-line address buss for carrying addresses in parallel, and the interface includes address latching means for connection to the address buss and connected to the ancillary data buss for storing main memory addresses to be accessed during reading from or writing into the main memory and presented on the ancillary data buss. The address latching means may include a low address latch for storing a predetermined lower part of an address presented on the ancillary data buss and a high address latch for storing the remaining higher part of the address.

Address decoding means are provided for connection to the address buss to decode composite addresses which are presented on the address buss and which include addresses to be accessed during reading from or writing into the ancillary memory. The address decoding means may include an address decoder for performing a comparison between a part of the address presented on the address buss and a preset address, and an address multiplexer for receiving the part of the address representing the ancillary memory address and connected to the control means for transmitting to the ancillary memory either the ancillary memory address received from the address buss or control signals received from the control means.

Reading from or writing into the ancillary memory may be initiated by the output of a transfer latching means which stores a write or read signal from the processing system in the event that the address decoding means indicates the present of an ancillary memory address on the address buss.

The control means of the interface device may include read-only memory means and means for addressing the read-only memory means to step the memory means sequentially through a stored program to provide output signals from the read-only memory means which constitute control signals for the interface device.

The means for addressing the read-only memory means may include clock means providing a master clock signal of given frequency, means for generating from the master clock signal a plurality of recurrent signals corresponding to respective clock phases, counting means for deriving from each cycle of the clock phases, counting means for deriving from each cycle of the clock phases an incremented address for applying to the read-only memory means. Preferably, the address output of the counting means is fed to the read-only memory means via an address multiplexer enabling selection of the address output of the counting or a further control signal indicating, for example, that access to the ancillary memory of the device is requested.

To permit conditional output of sequences of control signal by the read-only memory means, at least some of the outputs of the read-only memory means may be connected to output latching means which enables or disables the associated outputs of the memory means under the control of a conditioning signal selected by a condition multiplexer arranged to select, from amongst a plurality of conditioning signals, a single conditioning signal to be applied to the output latching means.

Addressable latching means connected to the ancillary buss may be provided for temporarily storing the control signals delivered by the read-only memory means.

The interface device may include an arithmetic unit connected to the ancillary buss for performing arithmetic or logic operations on data supplied thereto by the ancillary buss.

A bidirectional link may be provided between a first group of lines forming a byte of the ancillary buss and a second group of lines of the ancillary buss forming another byte to enable transfer of data between the two bytes.

In accordance with the second aspect of the present invention there is provided an arrangement for implementing conditional execution of a control function during a fixed sequence program controlling the operation of a digital device, which arrangement comprises an addressable memory means having control outputs each delivering a control signal corresponding to a respective said control function, each control signal having an operative logic state in which the respective control function is executed and an inoperative logic state in which the control function is not executed, the memory means having a plurality of addresses each corresponding to a respective stored combination of the said control signals constituting a step in the program; means for addressing the memory means wo step the memory means through the program steps in a fixed sequence; and output latching means connected to control a preselected output of the memory means and responsive to a given state of a conditioning signal to hold the control signal at the preselected output of the memory means in the inoperative state while the conditioning signal remains in its given state.

In this way, the execution of the control function corresponding to the preselected control signal, during a program step including the operative state of the preselected control signal, is made conditional on the state of the conditioning signal. Preferably, the output latching means is connected to control a plurality of preselected outputs of the memory means, whereby the execution of the control functions corresponding to all the preselected control signals is made conditional on the state of a single conditioning signal. By leaving certain of the outputs of the memory means free from control by the output latching means, parts of the stored program may be executed depending upon the condition of the conditioning signal.

The conditioning signal applied to the output latching means may be selected by a condition multiplexer arranged to select a single signal from amongst a plurality of available conditioning signals.

An arrangement in accordance with the second aspect of the present invention has the advantage of providing the equivalent of conditional branching within the stored program, without affecting the sequential nature of the execution of the stored program. This simplifies the design and ensures a fixed time for executing the program.

In order that the invention may be readily understood, an embodiment thereof will now be described, by way of example, with reference to the accompanying drawings, in which: Figure 1 is a diagram showing an interface device embodying the invention connected between a host digital processor and a set of interface connections; Figure 2 illustrates the construction of the interface device in more detail; and Figure 3 shows the control circuitry of the device in more detail.

Referring to Fig. 1, an exemplary interface device 1 embodying the invention serves to enable transfer of data between a host digital processor 2 (such as a Texas instruments 990/10 processor) and 128 interface connections 3 arranged to provide eight ports 4 (for connection to equipment such as Post Office modems and Post Office equipment DCE3A interfacing with the dialled telex network). Each port 4 consists of a serial data transmission line, a serial data reception line, seven input connections and seven output connections.

The host processor 2 includes a main or host 1 6-line data buss 5 for parallel transfer of data within the processor, a 20-line address buss 6 for parallel address transfers in the processor, a main or host memory 7 connected to the data and address busses 5 and 6, and host logic circuitry 8.

The interface device 1 includes an ancillary data buss 9 for parallel transfer of data addresses and control signals within the device, an ancillary memory 10 connected to the buss 9 for temporarily storing data, addresses and control signals within the device and ancillary logic circuitry 11.

The transfer of data between the processor 2 and the interface connections 3 involves carrying out reading and writing operations on the host memory 7 and the ancillary memory 10.

To enable transfer of data, and control of such transfer, between the device 1 and the processor 2 a number of connections are established between the device and processor as follows. A 16line connection 12 interconnects the host data buss 5 and the ancillary data buss 9. A 20line connection 13 interconnects the address buss 6 and the ancillary logic circuitry 11. The host logic circuitry and ancillary logic circuitry also have the following interconnections for logic control signals: a connection 14 for a READ/WRITE signal which indicates a read operation in one logic state (e.g. high) and a write operation in the other state (e.g. low); a connection 15 for a GO signal which changes from one logic state (high) to the other state (low) to initiate a data transfer; a connection 16 for a TERMINATE signal which goes from one logic state (high) to the other state (low) to indicate that the data transfer has been completed; a connection 17 for an IDLE signal which has one logic state (high) when the buss 5 or 9 is free and the other state (low) when the buss is busy; a connection 18 for an ACCESS GRANTED IN signal which has one logic state (high) when no higher priority access has been requested and the other state (low) denying access otherwise; a connection 19 for an ACCESS GRANTED OUT signal which has one logic state (high) when the ACCESS GRANTED IN signal is in its one state and access is not being requested and has the other state (low) otherwise; a connection 20 for a WAIT signal which in one logic state (low) suspends across to the host memory and in the other state (high) allows access completion of any suspended access; and lines 21, 22 for respective RESET signals which are normally in one logic state (high) and change to the other state (low) to reset the device.

Referring briefly to Fig. 2, the ancillary data buss 9 is connected to the host data buss 5 by a first bidirectional buffer in the form of a data buss latch 25 and to the interface connections 3 by a second bidirectional buffer 26 in the form of an output buffer store and an input buffer (i.e.

the input to the data buss 9 is not stored or latched).

Addressing means are provided in the form of a low address latch 27 and a high address latch 28 having their inputs connected to the ancillary data buss 9 and their outputs to the address buss 6 of the host processor.

Address decoding means are provided in the form of an address decoder 29 connected to the address buss 6 and an address multiplexer 30. A slave transfer latch 31 is connected to connection 14 for the READ/WRITE signal.

Control logic 32 including read-only memory provides outputs controlling the transfer and manipulation of data by the device and is connected, inter alia, to master access control logic 33 and to addressable latches 34 connected to the buss 9.

The interface device further includes an arithmetic unit 35 and a bidirectional link 36 each connected to the buss 9.

Referring briefly now to Fig. 3, the read-only memory (ROM) control logic 32 includes a master clock signal generator 37, a shift register 38, an address counter 39, an address multiplexer 40, a control ROM assembly 41, a ROM output enable latch 42, a condition multiplexer 43 and a condition inverter 44.

As indicated above, the transfer of data by the device 1 involves carrying out reading and writing operations on the host memory 7 and the ancillary memory 10. In the present description, the term "master access" is used to denote a read or write access to the host memory 7 by the device 1 and the term "slave access" to denote a read or write access to the ancillary memory 10 by the host processor.

The components of the interface device 1 shown in Figs. 2 and 3 will now be described in more detail.

The ancillary data buss 9 forms a 16-line tri-state internal parallel transfer path for data and addresses within the device 1. Each component which has its output connected to the buss 9 may have its output disabled so as to offer a high impedance to signal levels on the buss 9. The buss 9 is controlled so that no more than one output is enabled onto any line of the buss at any given time.

The data buss latch 25 which interconnects the data busses 5 and 9 is a 16-bit latch providing a bidirectional buffer store between the data busses. During master read accesses and slave write accesses, data from the host processor is temporarily stored in latch 25 prior to its transfer onto the ancillary data buss 9. During master write and slave read accesses, data from the buss 9 is temporarily stored in latch 25 prior to its transfer onto the host data buss 5. The operation of latch 25 is controlled by a 1-bit input enable signal 50, a 1-bit output enable signal 51 and a 1-bit clock signal 52 delivered by the control ROM assembly 41.The interface latch 26 which interconnects the data buss and the interface connections 3 include a number of interface elements, which depend upon the particular application of the device 1, for transferring data between the buss 9 and the connections 3. The latch 26 is controlled by appropriate control signals 53 from the ROM assembly 41.

The low address latch 27 is a 16-bit latch which is loaded from the data buss 9 with the lower 16 bits of a 21-bit address including the required 20-bit address of the host memory 7, prior to performing a master access, in response to a 1-bit input enabling signal 54 from the ROM assembly 41. During such an access, only the upper 15 bits of the address are enabled onto the address buss 6 of the host processor. The lowest, 16th bit, is delivered on line 55 to indicate which 8-bit byte within a 1 6-bit word is required. The 15-bit address output of latch 27 is enabled onto the address buss 6 by an output enable signal 56 from the master access control logic 33. The high address latch 28 is loaded from the buss 9 with the upper 5 bits of the 21-bit address in response to a 1-bit input enabling signal 57 from the ROM assembly 41.

The 5-bit address output of latch 28 is enabled onto the address buss 6 by the output enable signal 56 from the master access control logic 33.

The ancillary memory 10 includes a plurality of 16-bit words of random access memory and is organised so that data may be loaded into the upper 8 bits only, the lower 8 bits only, or all 16 bits, under the control of two 1 bit input strobe signals 59, 60 from the ROM assembly 41.

Similarly, the outputs from the upper and lower 8 bits of the memory 10 may be enabled onto the data buss 9 either independently or in parallel, under the control of two 1-bit output strobe signals 61, 62 from the ROM assembly 41. The memory 10 serves two functions. Firstly, it is used as an intermediate working storage for address, control and input/output data, during operation of the device. Secondly, the memory 10 may be accessed (slave access) by the host processor in order to write control information to the device 1 and to read status information from the device. It is by such slave accesses to the ancillary memory 10 that the host processor controls the operation of the device 1. To conserve address space in the host processor, only part of the memory 10 need be accessible through the slave access mechanism.

The address decoder 29 performs a parallel address comparison between an upper part of an address on the address buss 6 and a preset address, the bits of which may be fixed or variable, for example by means of removable links. The lower part of the address from buss 6, required to address the ancillary memory 10, is not processed by the address decoder 29 but is routed on lines 63 to the random access memory address multiplexer 30. In the event that the comparison in decoder 29 indicates that the device 1 is being addressed by the host processor, the decoder produces an output signal on line 64 to the slave transfer latch 31. The multiplexer 30 also receives from the ROM assembly 41 a 5-bit control signal on lines 65 and selects the signals on either lines 63 or 65 for application to the address inputs of memory 10.

When a slave access is attempted by the host processor and the address decoder 29 indicates that the device is being addressed, then the state of the READ/WRITE signal on line 14 is latched in the slave transfer latch 31 which also receives periodic signals 66 from the output of control logic 32. On the next signal 66 the latch 31 produces an output 67 to the control logic 32.

With reference to Fig. 3, the master clock signal generator 37 includes a suitable oscillator circuit whose output signal is delivered, either directly or after frequency division, as a master clock signal 70. The frequency of the oscillator circuit may also be chosen so that it may be used to drive a further frequency divider chain in order to generate further clock signals suitable for serial data transmission at various baud rates to and from the interface connections 3. The master clock signal 70 is used to clock the shift register 38 which is a synchronous 4-bit shift register, the highest bit of which is returned inverted to the lowest bit. Register 38 steps through six non-zero states starting from a zero condition and then returns to its zero condition.

The four bits of the register are combined to generate a six phase clock signal 71. The shift register 38 can be stopped at any phase or signal 71 by stop and restart logic 72 in response to data latch output enable control signal 51. The shift register can be restarted in synchronism with the master clock signal by logic 72.

At the start of every cycle of the six phase clock signal 71 a pulse 73 is delivered to address counter 39 to increment the counter. The outputs of counter 39 supply an incremental address 74 for application to the ROM assembly 41 to step the assembly 41 sequentially through a stored program, at each step of which the outputs of assembly 41 constitute control signals for operating the device 1. If it is desired to repeat the control program of assembly 41 while varying only a number of predetermined signals (for example to repeat for a number of identically controlled channels), the counter 39 may be extended the number of bits needed to step through these repetitions.Stop and reset logic 75 is provided to stop the counter 39 at any address 74 in response to a master access request signal 76 and to reset the counter to zero in response to a reset signal 77.

The output address 74 of the address counter 39 is fed to the ROM assembly 41 via the address multiplexer 40 which also receives a slave transfer address 78 from a slave address generator 79. The lowest two bits of the slave transfer address are determined by the state of the READ/WRITE signal 14 latched in latch 31 while the higher bits are present. The slave transfer address generator 79 therefore delivers one of two addresses of ROM assembly 41, depending on whether a read or write slave access is being requested. Normally the multiplexer 40 passes the address 74 from the address counter to the ROM assembly 41 but, in the event of a slave access request, the multiplexer is switched by signal 67 from the latch 31 to select the slave transfer address.

The ROM assembly 41 includes a plurality of application dependent read-only memories which are used to provide the control signals for the device 1. In order to ensure correct timing, various of these control signals may be synchronized with different phases of the six phase clock signal 71. The device 1 requires control signals totalling 43 bits (described particularly herein) to control the application independent hardware and further control signals 53 (not particularly described herein) to control the application dependent interface latch 26.

The output of the ROM output enable latch 42 controls the individual outputs 80 of a number of predetermined ROMs of assembly 41. The control signals generated by these predetermined ROMs are arranged so that, when the ROM outputs are disabled, the corresponding control signals revert to their inactive or unselected condition. Thus, when the enable latch 42 is in one state (high), the control functions of the predetermined ROMs are executed but, when the enable latch is in its other state (low), the control functions of the predetermined ROMs are not executed. The latch 42 may thus be used to implement the conditional execution of sequences of ROM output control functions.The enable latch 42 may be loaded conditionally, that is under the control of a 1-bit ROM output 81 which itself may be unselected by-the enable latch or unconditionally, that is under the control of a 1-bit ROM output 82 which is always enabled.

The condition multiplexer 43 selects one of a plurality of signals 83 to be used to load the latch 42 in response to a 5-bit select enable condition control signal 84 from the assembly 41.

The condition inverter 44 permits the condition selected by multiplexer 43 to be inverted, under the control of a 1-bit control signal 85, before loading into the enable latch 42.

When a slave access is requested by the host processor and the appropriate slave transfer address is selected for the ROM assembly 41, the control functions of the selected output signals are executed in the normal order and the fixed sequence program is resumed at the next cycle of the six phase clock. The necessary host processor response is generated directly from the output 67 of the slave transfer latch.

A master access is controlled by two control signals 68, 69 from the ROM assembly 41. Prior to any such access, the required address must be loaded into latches 27, 28. The first control signal 68 selects a read or write operation and the other control signal 69 initiates a master access request which is then processed by the access control logic 33 which runs synchronously with respect to the ROM assembly program. The ROM address counter 39 is stopped at the beginning of a mater access request and the ROM program loops continuously on the master access instruction until access to the host system buss is granted. During this waiting period (if any) the host system may perform slave accesses to the memory 10.When master access is granted and the counter re-started, the ROM control program resumes to generate control signals to select and strobe the address latches 27, 28 and the data latches 25, 26 to complete the transfer of data from the host processor to the interface connections 3. When the outputs of the address latches 27, 28 have been enabled onto the address buss 6 and, in the case of a write request, when the outputs of the data latch 25 have been enabled, the register 38 is halted until a transfer acknowledgement is received from the host processor. If no acknowledgement is received within a predetermined time, the access is terminated and the register restarted.

The arithmetic unit 35 is a 16-bit arithmetic logic unit containing a 16-bit register and for performing arithmetic and logical operations on data supplied thereto from the ancillary buss 9.

A 10-bit control signal 86 from the ROM assembly 41 controls the loading of unit 35 from the buss 9 and the enabling of the output of unit 35 onto the buss 9 and selects the arithmetic or logical operation to be performed by the unit. The unit 35 provides the following ten functions: CLEAR = Output all zeros SET = Output all ones INV = Set output to logical inverse of input INC = Output is input plus one AND = Output is logical "and" of input and register OR = Output is logical "or" of input and register XOR = Output is logical "exclusive or" of input and register -(XOR) = Output is logical "exclusive nor" of input and register SHIFT = Output is input shifted left by 1 bit, LEFT least significant bit = 0 The addressable latches 34 may be individually loaded by control signals from the ROM assembly 41 under the control of a 3-bit address signal 87 and a 1-bit strobe signal 88 from the ROM assembly 41. The outputs of the latches 34 may be enabled onto the ancillary data buss 9 by a control signal 89 from assembly 41 and may be cleared by a control signal 90 from assembly 41.

The internal data buss link 36 includes a tri-state link from the upper 8-bit byte of the buss 9 to the lower 8-bit byte of the buss 9 and a similar link from the lower 8-bit byte to the upper 8bit byte. These links allow the transfer of data between the upper and lower bytes of the buss 9 under the control of two 1-bit control signals 91 and 92 from the ROM assembly 41.

Claims (20)

1. An interface device for transferring digital data between an electronic digital data processing system and interface connections which include connections for the serial transfer of data, the processing system including a main memory connected to a multi-line main data buss for the parallel transfer of data within the processing system, the interface device including an ancillary data buss having the same number of lines as the main data buss, a first buffer connected to the ancillary data buss and for connection to the main data buss for transferring data between the two busses, a second buffer connected to the ancillary data buss and for connection to the interface connections for transferring data between the ancillary buss and the interface connections, an ancillary memory connected to the ancillary data buss, and control means having a fixed sequence program for effecting transfer of data between the ancillary buss and each of the main and ancillary memories so as to transfer data between the main memory and the interface connections.

2. An interface device according to claim 1, wherein the processing system includes a multiline address buss for carrying addresses in parallel, and the interface device includes address latching means for connection to the address buss and connected to the ancillary data buss for storing main memory addresses to be accessed during reading from or writing into the main memory and presented on the ancillary data buss.

3. An interface device according to claim 2, wherein the address latching means includes a low address latch for storing a predetermined lower part of an address presented on the ancillary data buss and high address latch for storing the remaining higher part of the address.

4. An interface device according to claim 2 or 3, wherein address decoding means are provided for connection to the address buss to decode composite addresses which are presented on the address bus and which include addresses to be accessed during reading from or writing into the ancillary memory.

5. An interface device according to claim 4, wherein the address decoding means includes an address decoder for performing a comparison between a part of the address presented on the address bus and a preset address, and an address multiplexer for receiving the part of the address representing the ancillary memory address and connected to the control means for transmitting to the ancillary memory either the ancillary memory address received from the address buss or control signals received from the control means.

6. An interface device according to claim 4 or 5, wherein reading from or writing into the ancillary memory is initiated by the output of a transfer latching means which stores a write or read signal from the processing system in the event that the address decoding means indicates the presence of an ancillary memory address on the address buss.

7. An interface device according to any preceding claim, wherein the control means includes read-only memory means and means for addressing the read-only memory means to step the memory means sequentially through a stored program to provide output signals from the readonly memory means which constitute control signals for the interface device.

8. An interface device according to claim 7, wherein the means for addressing the read-only memory means includes clock means providing a master clock signal of given frequency, means for generating from the master clock signal a plurality of recurrent signals corresponding to respective clock phases, counting means for deriving from each cycle of the clock phases an incremented address for applying to the read-only memory means.

9. An interface device according to claim 8, wherein the address output of the counting means is fed to the read-only memory means via an address multiplexer enabling selection of the address output of the counting or a further control signal indicating, for example, that access to the ancillary memory of the device is requested.

10. An interface device according to any one of claims 7 to 9, wherein at least some of the outputs of the read-only memory means may be connected to output latching means which enables or disables the associated outputs of the memory means under the control of a conditioning signal selected by a condition multiplexer arranged to select, from amongst a plurality of conditioning signals, a single conditioning signal to be applied to the output latching means.

11. An interface device according to any one of claims 7 to 10, wherein addressable latching means connected to the ancillary buss are provided for temporarily storing the control signals delivered by the read-only memory means.

12. An interface device according to any preceding claim, including an arithmetic unit connected to the ancillary buss for performing arithmetic or logic operations on data supplied thereto by the ancillary buss.

13. An interface device according to any preceding claim, wherein a bidirectional link is provided between a first group of lines forming a byte of the ancillary buss and a second group of lines of the ancillary buss forming another byte to enable transfer of data between the two bytes.

14. An interface device substantially as hereinbefore described with reference to, and as illustrated in the accompanying drawings.

15. An arrangement for implementing conditional execution of a control function during a fixed sequence program controlling the operation of a digital device, which arrangement comprises: an addressable memory means having control outputs each delivering a control signal corresponding to a respective 'said control further, each control signal having an operative logic state in which the respective control function is executed and an inoperative logic state in which the control function is not executed, the memory means having a plurality of addresses each corresponding to a respective stored combination of the said control signals constituting a step in the program; means for addressing the memory means to step the memory means through the program steps in a fixed sequence; and output latching means connected to control a preselected output of the memory means and responsive to a given state of a conditioning signal to hold the control signal at the preselected output of the memory means in the inoperative state while the conditioning signal remains in its given state.

16. An arrangement according to claim 15, wherein the output latching means is connected to control a plurality of preselected outputs of the memory means, whereby the execution of the control functions corresponding to all the preselected control signals is made conditional on the state of a single conditioning signal.

17. An arrangement according to claim 15, wherein certain of the outputs of the memory means are left free from control by the output latching means, whereby parts of the stored program may be executed depending upon the condition of the conditioning signal.

18. An arrangement according to any one of claims 15 to 17, wherein the conditioning signal applied to the output latching means is selected by a condition multiplexer arranged to select a single signal from amongst a plurality of available conditioning signals.

19. An arrangement for implementing conditional execution of a control function during a fixed sequence program controlling the operation of a digital device.

20. Any novel feature or combination of features herein described.