GB2049297A - Method of manufacturing printed circuitry - Google Patents
Method of manufacturing printed circuitry Download PDFInfo
- Publication number
- GB2049297A GB2049297A GB7917417A GB7917417A GB2049297A GB 2049297 A GB2049297 A GB 2049297A GB 7917417 A GB7917417 A GB 7917417A GB 7917417 A GB7917417 A GB 7917417A GB 2049297 A GB2049297 A GB 2049297A
- Authority
- GB
- United Kingdom
- Prior art keywords
- circuit pattern
- layer
- conductive circuit
- photo
- insulator material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
- H05K3/205—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using a pattern electroplated or electroformed on a metallic carrier
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09563—Metal filled via
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/01—Tools for processing; Objects used during processing
- H05K2203/0147—Carriers and holders
- H05K2203/0152—Temporary metallic carrier, e.g. for transferring material
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
- H05K2203/0703—Plating
- H05K2203/0726—Electroforming, i.e. electroplating on a metallic carrier thereby forming a self-supporting structure
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4647—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer around previously made via studs
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
A polished substrate 14 carries thin layers of nickel and copper over which a photo-resist layer 10 is applied. A film of lubricating wax 16 is optionally applied to the layer 10 before a photomask 18 is placed in position and pressed into intimate contact by passing the assembly through pressure rollers 20 and 22. Subsequently the resist layer is exposed through the mask and developed to form spaces into which the required conductive circuit pattern is deposited. The remaining photo-resist is removed, an insulating layer is laminated to the pattern and the assembly is stripped from the substrate, after which the copper and nickel layers are etched away. <IMAGE>
Description
SPECIFICATION
Method of manufacturing printed circuitry
This invention relates to a method of manufacturing high density fine line resolution printed circuitry and more particularly to a method in which the printed circuitry is formed on a polished, removable substrate using a high resolution photographic process.
Printed circuitry may be formed on ceramic, metal, resin and even flexible film substrates and is utilized to interconnect individual circuit components such as resistors, capacitors, inductors and semiconductor devices including complex integrated circuits. A conductive printed circuit pattern may vary from a simple pattern of radially extending conductors for connecting an integrated circuit chip to a lead frame to a highly complex multilayer pattern for interconnecting many complex circuit components.
The trend has been to require more and more complex printed circuitry with higher densities of printed conductors in order to accommodate increasingly complex circuit components in decreasing space to reduce costs and improve reliability.
While line resolutions of 1 micron or better have been attained on semiconductor integrated circuits, the best resolution that is currently commercially available for printed circuitry interconnecting nonmonolithic circuit components is 5 mii wide lines on 10 mil centers. Substantial irregularities in circuit conductors have thwarted attempts to attain adequate yields because of short circuits, open circuits and high resistance narrow conductor regions. These irregularities result from a number of factors including surface roughness of the substrate, diffusion and diffraction of the exposure light as it passes through the photo mask, photoresist and irregular edge development of exposed photoresist and uneven etching of masked conductive layers.
A n u m bernumber of processes for forming printed circuit ry on nonpermanent smooth substrates are described in U.S. patents 2,692,190; 2,721,822; 2,724,674; 3,181,986 and 3,350,498. However, none of these processes is capable of attaining the commercially practical, high resolution printed circuitry that is attainable with methods in accordance with the present invention.
Summary of the invention
The method of manufacturing high density, fine line resolution printed circuitry in accordance with the invention includes the steps of placing a thickness of photosensitive material on a smooth surface of a substrate; optionally applying a thin lubricating film of lubricant to the top surface of the photosensitive material; placing a photomask defining a conductor circuit pattern adjacent the surface of the photosensitive material; wringing the photomask into intimate, continuous contact with the photosensitive surface; exposing and developing the photosensitive material to expose the smooth surface in regions where a conductive circuit pattern is to be formed; forming a conductive circuit pattern on the smooth surface in said regions; removing all remaining photosensitive material from the smooth surface; laminating a layer of flowable polyamideimide dielectric material to the smooth surface-and conductive circuit pattern; and removing the insulator material and conductive pattern from the smooth surface.
It is also possible to form additional layers of conductive circuit patterns prior to removing the printed circuit. The printed circuit may be laminated to a metal or other substrate using the dielectric or insulator material as an adhesive. To form each additional level of printed circuitry a circuit layer containing a conductive circuit pattern of upwardly extending, raised via conductors or interconnects is formed on the preceding circuit layer before laminating the insulator material. The top surface of the insulator material is removed by sanding or otherwise to form a smooth surface coplanar with the tops of the raised interconnects. The process for the first layer of circuit pattern can then be repeated to construct a second level of printed circuitry that is selectively interconnected with the preceding lower level by the electroplated raised interconnects.
Brief description of the drawings
A A more complete understanding of the invention may be had from a consideration of the following detailed description, taken in conjunction with the accompanying drawings in which:
Figures 1-6 are sectional side views of a high density printed circuit in accordance with the invention illustrating successive stages in the manufacturing process; and
Figures 7A and 7B are sectional side views illustrating alternative embodiments of high line density printed circuits in accordance with the invention.
Detailed description
A printed circuit having high density, fine lines of printed conductors is manufactured in accordance with the invention on a polished substrate using an additive process in combination with photolithogaphic techniques. Referring now to Figure 1,a0.6 mil (0.001524cm) thick uniform layer of dry film photo resist 10 or other photosensitive material of suitable uniform thickness is applied to a polished surface 12 of a substrate 14. While the thickness of the dry film resist is not critical, it should be at least as thick as a desired printed conductor and greater thicknesses tend to reduce the attainable line definition. A thickness of 0.6 mil is used in the present example for both resist and printed conductors.The substrate 14 is reusable and may be a stainless steel plate of suitable thickness of about 1/8-1/4 inch with a a highly polished top surface 12. A thin layer of releasing material such as a 0.1 mil thick flash of nickel is applied to the polished surface 12 before the photoresist layer 10 is applied thereto. The releasing agent merely makes it possible to peel the printed circuit away from the substrate 14 after formation of the printed circuit is complete. In addition, thin layers of copper may be deposited on the releasing layer before the layer 12 of photoresist is placed upon the substrate.
A Avery thin layer 16 of a lubricating material such as wax is then optionally applied to the exposed surface of the photoresist. The lubricant may be a common household spray wax such as one product that is available under the trademark PLEDGE and is applied by simply spraying a thin film onto the exposed surface of the photoresist 10. The surface of the layer of photoresist 10 tends to be somewhat sticky and the layer of lubricant 16 permits fine positioning of the mask 18 while in contact with the lubricated exposed surface of the layer of photoresist 10 for proper alignment. However, fine positioning of the first layer is often unnecessary and the lubricant can be omitted.
After the mask 18 is placed atop the surface of the layer of photoresist 10, a wringing operation is performed to remove any gas or air bubbles from between the mask 18 and layer of photoresist 10 and bring the mask 18 into high integrity continuous contact with the surface of the layer of photoresist 10. By way of example, the wringing may be accomplished by passing the substrate 14, layer of photoresist 10 and mask 18 through a pair of pressure pinch rollers 20,22.
After wringing, the photoresist is exposed in a conventional manner to collimated light and developed to remove portions of the layer of photoresist 10 from the region where conductive circuit patterns are to be formed. Because the mask is brought into extremely close contact with the layer of photoresist 10 and because the prior wringing operation minimizes diffraction as light passes from the mask 18 to the layer of photoresist 10, the light exposure forms an extremely high resolution sharp line pattern in the photoresist 10 and upon developing, extremely straight, vertical walls 26 are formed at the boundaries defining the cavities from which the portions of the layer of photoresist 10 are removed.A thin layer 27 of gold or nickel is electroplated in the cavities defining the conductive circuit pattern as a mask to protect the conductive circuit pattern when the release material is later etched. A conductive material 28 such as copper, gold or nickel is then electroplated onto the conductive, polished surface 12 as shown in Figure 2 to form the conductive circuit pattern defined by the photomask 18. This additive process causes the line edges of the conductive pattern to be straight and perpendicular because they conform in shape to the walls of the photoresist. A subtractive process in which a complete layer of copper is first deposited and then selectively etched has not achieved this fine resolution because undercutting occurs beneath the photoresist mask and the etched walls are not as smooth and sharp as those attainable in the photoresist.
Although not required for single layer printed circuit patterns, if a second circuit pattern layer is to be formed, an interconnect pattern is next formed atop the first layer printed circuit patten 30 as shown in Figure 3. The interconnect circuit pattern may be formed by a conventional photolithographic process either by plating and then photolithographically etching or as illustrated in Figure 3 by first defining a desired interconnect pattern through a masking layer of photoresist material 44 and then electroplat
ing the interconnects 46 within the voids formed by
the masking layer 44.Because first portions of the
first layer of photoresist 10 are yet to be removed,
pads for the interconnects should be provided in the
first circuit layer 30 with sufficient area that the
interconnects 46 need not extend beyond underlying
portions of the first layer printed circuit pattern 30.
Thus, upon formation of the interconnects 46 both
layers 10,44 of photoresist may be stripped com
pletelyfrom the partially manufactured printed
circuit. In the absence of the smooth, polished
surface 12, additional circuit layers cannot be
obtained with the same high density line resolution
as the first circuit layer and the interconnects 46
should therefore have a minimum thickness of
approximately 1 mil and preferably 2 mils beyond
the thickness of the circuit layer 30 and should have
minimum dimensions of about 2 mils in the plane of
a second layer 48 within which the interconnects 46
and second layer of photoresist 44 lie.
Making reference to Figure 4, the first and second
layers of photoresist are completely stripped from
the partially formed printed circuit and a flowable,
somewhat plastic insulating material 50 is laminated
to the remaining conductive first layer printed circuit
pattern 30 and interconnect pattern 46. For best
uniformity, the insulating material 50 is applied as a
thin sheet of dry film material having a uniform
thickness at least as great as the combined thickness
of the first circuit pattern 30 and interconnects 46.
For example, in the present example the combined
thickness is 0.6 + 2.0 = 2.6 mil and a 4 mil thick layer
of insulating material 50 is satisfactory. The insulator
material 50 is suitably cured in a laminating press
having press plates 52, 54 and a silicone rubber pad
layer 56 between the insulating material 50 and the
opposing adjacent press plate 52.
The insulating material 50 is preferably a
polyamideimide material adhesive film which is
commercially available under the trademark Kerimid
501 from Rhodia Inc., 600 Madison Avenue, New
York, New York 10022. If this material is used it
should be cured for two hours at a temperature of
190 degrees centigrade under a pressure of 100
pounds per square inch to cause the insulating
material 50 to flow into the voids between the
conductors and attain a high strength bond with the
copper conductors. Next, excess insulator material
52 is removed from the partially completed printed
circuit to provide a top surface 60 that is flat and
coplanar with the tops 58 of the interconnects 46.
The material 50 may be removed using a suitable
process such as sanding with a very fine grade of
sandpaper. The resulting structure is illustrated in
Figure 5.
Referring now to Figure 6, a second layer printed
circuit pattern 62 may then be formed atop the
surfaces 58 and 60 by any suitable process. For
example, a complete layer of copper may be plated
and then selectively etched to leave the desired
circuit pattern. Alternatively, a thin layer of copper
may be electroless deposited upon the surfaces 58 - and 60 and electroplated to a thickness of about 0.1
mil. Photoresist is then placed on the plated surface
and a desired circuit pattern is defined as voids ithin the layer of photoresist. The thin layer of plated copper is utilized as a conductor to permit the electroplating of the desired circuit pattern within the voids in the photoresist. A thin layer 63 of nickel is electroplated as a mask atop the conductive circuit pattern.Upon stripping of the photoresist, a rapid etch removes the deposited thin layer of copper from regions where a conductive circuit pattern is not desired. The second layer circuit pattern 62 preferably has a thickness of about 2 mils. After stripping of the photoresist, a second layer 70 of flowable insulating material such as Kerimid 501 is laminated to the second layer printed circuit pattern 62 and first layer of insulating material 50 in a laminating press as described in conjunction with
Figure 4.
Athin layer or flash of nickel may be electro deposited upon the second layer printed circuit pattern 62 before laminating to provide a stronger bond between the second layer printed circuit pattern 62 and second layer of laminating material 70. Sanding may then be used to smooth the second layer of insulating material 70 as illustrated in Figure 6.
The printed circuit may then be completed as illustrated in Figure 7A or alternatively as illustrated in Figure 7B. In Figure 7A the printed circuit has been completed by laminating one or more additional layers of Kerimid 501 insulating material to the top of the structure to form a high density, flexible multilayer printed circuit. In the alternative arrangement shown in Figure 7B, the additional layers of Kerimid 501 insulating material 72 are utilized to bond a metal circuit substrate 74 to the top of the second layer printed circuit structure 62 and insulating material 70 to provide a stable printed circuit structure with good heat transfer capability.In either case, the printed circuit structure is removed from the polished surface 12 of the substrate 14 and the thin layers of copper and nickel release material may be removed from unwanted regions of the surface of the first layer printed circuit 30 and insulating material 50 by etching. It will be appreciated that additional layers of printed circuitry can optionally be formed upon the second layer printed circuit 62 in a manner similar to that in which the second layer printed circuit pattern 62 was formed upon and interconnected with the first layer printed circuit 30.
While there have been shown and described above preferred methods of manufacturing a high line density, high resolution printed circuit in accord- ance with the invention for the purpose of enabling a person of ordinary skill in the art to make and use the invention, it will be appreciated that the invention is not limited thereto. Accordingly, any modifications, variations or equivalent methods within the scope of the attached claims should be considered to be within the scope of the invention.
Claims (15)
1. A method of manufacturing printed circuitry comprising the steps of applying a layer of photosensitive material to a smooth substrate surface, placing a photomask defining a conductor circuit pattern adjacent the surface of the photo-sensitive material, wringing the photomask into intimate continuous contact with the photo-sensitive material, photo-exposing and developing the photosensitive material to remove said material from areas where a conductive circuit pattern is to be formed, forming the conductive circuit pattern in the spaces left in the photo-sensitive layer, removing the remaining photo-sensitive material, laminating a layer of flowable insulator material to the conductive circuit pattern and the smooth substrate surface and stripping the insulator material and conductive circuit pattern from the smooth surface.
2. A method as claimed in claim 1 in which the layer of photo-sensitive material is dry film photoresist material.
3. A method as claimed in claim 1 or 2 wherein a thin lubricating film is applied to the surface of the photo-sensitive material before the photomask is applied.
4. A method as claimed in claim 3 in which the lubricating film is a film of wax lubricant.
5. A method as claimed in claim 4 in which the film is applied by spraying.
6. A method as claimed in any of the preceding claims in which the wringing step comprises passing the substrate, photo-sensitive material, and photomask between a pair of pressure pinch rollers.
7. A method as claimed in any of the preceding claims in which the flowable insulator material is a dry film polyamideimide material.
8. A method as claimed in any of the preceding claims comprising the additional steps executed between the steps of laminating and stripping of:
removing part of the insulator material adjacent a surface thereof to form a planar surface of insulator material coplanar with a plane defined by a surface of the conductive circuit pattern opposite the smooth surface of the substrate; and
laminating a second layer of said flowable insulator material to the planar surface and the surface of the conductive circuit pattern.
9. A method as claimed in any one of the preceding claims comprising the additional step executed between the steps of forming the conductive circuit pattern and removing the photo-sensitive material of:
forming interconnects at selected locations atop the conductive circuit pattern, said interconnects extending away from the surface of the conductive circuit pattern to a selected thickness;
and the additional steps executed between the steps of removing the photo-sensitive material and laminating of:
removing part of the layer of insulator material adjacent a surface thereof to form a second planar surface of insulator material coplanar with a plane defined by extremities of the interconnects; and
forming a second conductive circuit pattern on said second planar surface in electrical communication with said interconnects.
10. A method as claimed in claim 9 further comprising the step of bonding a third layer of said flowable insulator material to said second planar surface and the second conductive circuit pattern.
11. A method as claimed in claim 9 further comprising the step of bonding a substrate to said second planar surface and second conductive circuit pattern formed thereon using a third layer of said flowable insulator material sandwiched therebetween.
12. A method as claimed in claim 8 wherein said step of removing part of the insulator material adjacent a surface is effected by sanding.
13. A method as claimed in any of the preceding claims, wherein the conductive circuit pattern is formed by electroplating copper to the selected thickness.
14. A method as claimed in any of the preceding claims wherein the smooth substrate surface to which the photo-sensitive material is applied is formed by a thin layer of conductive material which is etched after the formation of the conductive circuit pattern and the removal of the remaining photosensitive material.
15. A method as claimed in claim 14 wherein before the conductive circuit pattern is formed a metal mask of material different from that of the layer of conductive material is formed in areas from which the photo-sensitive material has been removed.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB7917417A GB2049297B (en) | 1979-05-18 | 1979-05-18 | Method of manufacturing printed circuitry |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB7917417A GB2049297B (en) | 1979-05-18 | 1979-05-18 | Method of manufacturing printed circuitry |
Publications (2)
Publication Number | Publication Date |
---|---|
GB2049297A true GB2049297A (en) | 1980-12-17 |
GB2049297B GB2049297B (en) | 1984-01-25 |
Family
ID=10505261
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB7917417A Expired GB2049297B (en) | 1979-05-18 | 1979-05-18 | Method of manufacturing printed circuitry |
Country Status (1)
Country | Link |
---|---|
GB (1) | GB2049297B (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0529578A2 (en) * | 1991-08-26 | 1993-03-03 | Hughes Aircraft Company | Semi-additive circuitry with raised features using formed mandrels |
EP0645952A1 (en) * | 1993-09-27 | 1995-03-29 | Rogers Corporation | Method of manufacturing a multilayer circuit |
-
1979
- 1979-05-18 GB GB7917417A patent/GB2049297B/en not_active Expired
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0529578A2 (en) * | 1991-08-26 | 1993-03-03 | Hughes Aircraft Company | Semi-additive circuitry with raised features using formed mandrels |
EP0529578A3 (en) * | 1991-08-26 | 1993-08-04 | Hughes Aircraft Company | Semi-additive circuitry with raised features using formed mandrels |
US5440805A (en) * | 1992-03-09 | 1995-08-15 | Rogers Corporation | Method of manufacturing a multilayer circuit |
EP0645952A1 (en) * | 1993-09-27 | 1995-03-29 | Rogers Corporation | Method of manufacturing a multilayer circuit |
Also Published As
Publication number | Publication date |
---|---|
GB2049297B (en) | 1984-01-25 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 19920518 |