GB2047928A - Means and Method Within a Digital Processing System for Prefetching both Operation Codes and Operands - Google Patents
Means and Method Within a Digital Processing System for Prefetching both Operation Codes and Operands Download PDFInfo
- Publication number
- GB2047928A GB2047928A GB8012813A GB8012813A GB2047928A GB 2047928 A GB2047928 A GB 2047928A GB 8012813 A GB8012813 A GB 8012813A GB 8012813 A GB8012813 A GB 8012813A GB 2047928 A GB2047928 A GB 2047928A
- Authority
- GB
- United Kingdom
- Prior art keywords
- operand
- opcode
- instruction
- processor
- instruction word
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 238000000034 method Methods 0.000 title claims description 13
- 230000001131 transforming effect Effects 0.000 claims description 3
- 230000004044 response Effects 0.000 abstract description 5
- 230000009471 action Effects 0.000 description 6
- 230000008901 benefit Effects 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 230000014509 gene expression Effects 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000000977 initiatory effect Effects 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3824—Operand accessing
- G06F9/383—Operand prefetching
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3824—Operand accessing
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Advance Control (AREA)
- Executing Machine-Instructions (AREA)
- Memory System (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Devices For Executing Special Programs (AREA)
Abstract
In a digital processing system, a memory stores instructions defining logical operations to be performed by a processor. Means operate while the processor is executing one instruction to retrieve an operation code portion of the next instruction and, in response to the operation code, an operand associated with the instruction. The operation code portion and operand are then transferred to the processor for execution. Thus, independently of and concurrently with the execution of a current instruction, a further instruction and, if appropriate, an associated operand, can be retrieved.
Description
SPECIFICATION
Means and Method Within a Digital Processing
System for Prefetching both Operation Codes
and Operands
Background of the Invention
The subject matter of the present invention
pertains to means for fetching instructions and
operands in a digital processor system.
As is known to the art, a conventional
processor-based computing system includes,
besides a processor section, a memory section for
holding information to be processed and an
input/output section for transferring information
into and out of the system. In such a conventional
system, information in the form of instructions
and operands are fetched, or read, from memory
in a sequential, as-needed manner under control
of a program counter located in the processor. As
each new instruction or operand is required, it is
fetched from memory and made available to the
processor for execution or other appropriate
action. In some known systems, provision is also
made to fetch a next instruction during the
execution of a present instruction.
A problem arises when the instruction to be
executed requires that additional information be obtained before execution can begin: for example,
a value to be combined with a first value during
an arithmetic operation. In such cases, the
processor must wait while an additional memory
access is made and the information obtained.
Such processor waiting or idling detracts
significantly from ~he overall speed and efficiency
of the system.
Summary of the Invention
The present invention is directed to a system
and method for prefetching both instructions and
operands for subsequent execution or other
action by a digital processor. More particularly,
the system of the present invention comprises a
memory control unit and method of same for
fetching a next instruction and any associated
operands while the processor is executing a
present instruction, the fetching operation being
independent of and concurrent with the execution
operation.
During the execution of a present instruction-by the processor, the memory control unit
automatically fetches the next instruction word,
decodes the command, or operation code, portion
of he word into certain preselected control
signals, and employs the control signals as
appropriate to fetch a second byte or word
containing any operands necessary for the
execution of the instruction. In many cases, both
the next-instruction-fetch operation and the
operand-fetch operation are completed before the
processor is finished executing the present
nstruction. In almost all cases, the prefetch
operation will at least have decreased the amount
of time that the processor has to wait before the
next instruction and operand are available for
execution or other action.Provision is also made for saving certain portions of a prefetched instruction word to preclude the need for a subsequent memory access and thereby further decrease the processor waiting time.
It is therefore, a principal objective of the present invention to provide a means and method within a processor-based computing system for increasing the overall efficiency of the system by decreasing the time that the processor must wait for a next instruction or operand.
It is an additional principal objective of the present invention to provide a means and method within such a system for prefetching, concurrent with the execution of a present instruction, both a next instruction and, if appropriate, a next operand for subsequent execution or other action by the processor.
It is a feature of the present invention that the program counter normally employed to provide the memory address of a next instruction is located in and controlled by a memory control unit, rather than the processor, so as to permit a next instruction to be fetched without processor intervention.
The foregoing objectives, features, and advantages of the present invention will be more readily understood upon consideration of the following detailed description of the invention taken in conjunction with the accompanying drawing.
Brief Description of the Drawing
The single figure is a block-diagram representation of the memory control unit of the present invention incorporated within a processor-based computing system.
Detailed Description of the Preferred
Embodiment
Referring to the figure, there is disclosed in simplified block-diagram form the memory control unit (MCU) 20 of the present invention incorporated within a processor-based computing system including a processor section 22, a main memory section 24, and an input/output (I/O) section 26, all interconnected as indicated in the figure with the solid lines indicating data lines and the dashed lines indicating control lines.
The processor section 22 includes, for purposes of illustration: a read-only (ROM) 30 for storing one or more pre-encoded microprograms; sufficient arithmetic circuitry 32 for receiving data words from the MCU 20, performing certain preselected logical operations, and transmitting data words back to the MCU, all in response to certain control signals produced by the ROM 30: and a processor control circuit 34 for controlling the operation of the ROM 30 and arithmetic circuitry 32 in a manner producing a desired logical operation. The information stored in the
ROM 30 comprises a series of micro-instruction words, different sequential groups of which form microprograms implementing one or more macro- instructions of the system instruction set.In response to a received macro-instruction word, the processor control circuit 34 accesses in sequence each instruction word of the associated microprogram so as to produce a series of control signals necessary to cause the arithmetic circuitry 32 to perform any desired operation. Such processor sections are conventional in nature and well known to the art.
The main memory section 24 includes, also for purposes of illustration, a read-only memory (ROM) 40, a random-access memory (RAM) 42, associated address circuitry 44 and data circuitry 46, and an associated control circuit 48, all of which are accessible via either the MCU 20 or the
I/O section 26. In the example of the figure, each memory module 40, 42 comprises 65,536 (65K) words of eight bits each, with each word being uniquely identifiable by a particular 16-bit address word and an appropriate memory-select signal. It is understood that the scope of the invention is not limited by the capacity of the memory modules or the length of the memory words. The
I/O section 26 may include such known components as cathode-ray tube displays, keyboards, joy sticks, mag-tape units, and the like.
Input to the system is accomplished by presenting data signals to the data circuitry 46 and an appropriate control signal to the memory control circuit 48, and output is accomplished by transmitting data signals from either memory 40, 42 to the I/O section, again accompanied by the appropriate control signal. Each of the main memory section 24 and the I/O section 26 is conventional in nature; however, it is advantageous if the memory section is capable of receiving, storing, and transmitting information in a byte-overlapping manner; i.e., with a lower byte of a first two-byte word forming also the upper byte of a next succeeding two-byte word. Such a memory system is disclosed in a copending application No. (filed concurrently herewith) assigned to the assignee of the instant application and will be assumed for the remainder of this discussion.
Turning now to the memory control unit 20, which forms the basis of the present invention, there is disclosed in the figure an instruction
register 60 for holding and presenting to the
processor section 22 an 8-bit instruction word, a fetch control read-only memory (ROM) 62 for
automatically transforming each instruction word delivered to the instruction register 60 into any of 256 possible 8-bit control signals, and an MCU control circuit 64 or performing certain predefined control functions in response to the control
signals produced by the ROM 62.Also disclosed
are a 16-bit program counter 66 for holding the
main memory address of the next macro
instruction word, a 16-bit input data latch 68 and
16-bit output data latch 70 for holding and
transmitting data words into and out of the
processor section 22, a memory byte latch, or
register, 72 for holding the lower eight bits of a
16-bit instruction word, and a zero/sign-extend
circuit 74 for producing eight bits of all zeros or all
ones for selective combination with the eight bits stored in the memory byte latch. As used herein, the term "instruction word" is understood to include a memory word comprising any of an operation code, an operand, or both.
Access to the main memory section 24 is by either of two independent modes: explicit and implicit. In explicit mode, the memory is accessed in a conventional manner by the processor section 22 sending an address signal via the output latch 70 and an appropriate control signal via the MCU control circuit 64 to main memory during a first timing cycle and sending or receiving a data signal via the output of latch 70 or input latch 68 during a second succeeding timing cycle.
In implicit mode, memory access is via the
MCU 20 alone independent of and without invervention by the processor 22. For ease of understanding, explanation of implicit mode accesss is given concurrently with explanation of the operation of the memory control unit 20. It is understood that the novelty of the present invention resides in the functional and operational characteristics of the memory control unit 20 in association with the processor 22 and memory 24, and that the implementation of the individual components of the control unit may be by any conventional means. The primary functions of the
MCU 20 are to prefetch instruction words for subsequent execution by the processor 22 and to prefetch any operands necessary for the instruction execution.As is known to the art, a conventional instruction word comprises generally at least one byte defining an operation code, or opcode, and one or more additional bytes defining any operands necessary for the performance of the identified operation. An exception to the general rule is the single-byte instruction not requiring an operand for its execution. In all cases, the opcode portion of the instruction contains information defining the source, if any, of the necessary operands. For instruction words of three bytes or less, the MCU 20 can prefetch both the opcodes and the necessary operands. For instruction words of more than three bytes, the operands are fetched by the processor 22 via an explicit mode access.
During execution of a present instruction not requiring any further access to main memory, the processor section 22 sends a control signal via signal line 80 to the MCU control circuit 64 of the memory control unit 20 to pre-fetch the next succeeding instruction word. Upon receipt of the prefetch signal, the control circuit 64 sends a signal via control line 82 to the memory control circuit 48 to retrieve the 16-bit memory word identified by the 16-bit memory address signal currently stored in the program counter 66 (Note that the program counter is located in the MCU 20 rather than in the processor section 22 as is the convention. Location of the program counter in the MCU permits it to be incrementally updated under control of the control circuit 64 without processor intervention. As is the convention, the program counter 16 is maintained to always contain the address of the next instruction word to be redtrieved). The upper eight bits (8-1 5) of the retrieved memory word (the opcode) are sent via data line 84 to the instruction register 60 and the lower eight bits (0--7, a potential operand) are sent via the same line to the byte latch 72.
Upon receipt by the instruction register 60, the 8bit opcode is held for later transfer to the processor section 22 and simultaneously sent to the latch control ROM 62 for automatic transformation into a control signal indicative of whether an operand is required for the opcode execution and, if so, the source of the operand address. The most common source of an operand address is the program counter 66 (now incremented to reflect the address of the next instruction word). Another common source is the second byte, or second and third bytes, of the prefetched instruction word. The fetch control
ROM 62 is, in the example of the figure, a 256 word by eight bit read-only memory that has been preloaded to produce a preselected 8-bit control signal in response to a received 8-bit opcode.
Equivalent devices of different capacities may also be employed without departing from the invention as disclosed.
If a prefetched instruction comprises an opcode only, the control signal produced by the
ROM 62 causes the eight bits stored in the byte latch 72 to be discarded as the opcode stored in the instruction register 50 is ready for transmission to the processor 22 without further operation. If the second byte of the prefetched instruction word is literal, i.e., a data constant of an offset, the control signal produced by the ROM 62 causes the eight bits stored in the byte latch 72 to be transferred together with eight bits of all zeros or all ones from the zero/sign-extend circuit 74, to the input latch 68 for subsequent transfer, together with the opcode from the instruction register 60, to the processor 22.The data lines connecting the memory byte latch 72 and the zero/sign-extend circuit 74 with the input latch 68 are arranged such that the eight bits from the byte latch are transferred to the lower eight bit positions of the input latch and the eight bits from the zero/sign-extend circuit are transferred to the upper eight bit positions. If the second byte of the prefetched instructin word is a short address, i.e.,.
from OO to FF in hexadecimal, the control signal produced by the control ROM 62 causes the eight bits stored in the byte latch 72 to be transmitted back to the main memory section 24, together with an appropriate control signal from the MCU control circuit 64 to the memory control circuit 48, to effect a memory read operation at the location defined by the eight bit signal. The retrieved 16-bit operand signal is then sent to the input latch 68 for subsequent transfer, again together with the opcode stored in the instruction register 60, to the processor section 22.
If the prefetched opcode indicates that the operands or the addresses of the operands required for its execution are contained in a third, as well as a second byte of the associated instruction word, the resultant control signal produced by the fetch control ROM 62 causes, through action of the MCU control circuit 64, the eight bits contained in the byte latch 72 to be discarded and a new memory access to be initiated at the address defined by the current contents of the program counter 66, with the retrieved 16-bit memory word being transferred to the input latch 68 if a literal, or recycled through the address circuitry 44 for a subsequent memory access if an address. In the latter case, the 16-bit memory word retrieved during the second access is also tranferred to the input latch 68 for subsequent action by the processor 22.
Only if the instruction word comprises four or more bytes is it necessary for the processor 22 to retrieve the operands via an explicit memory access; otherwise, the prefetch operation is completely independent of the processor operation, except, of course, for the generation of the initial prefetch signal.
It will be noted that although the data transfer from the main memory section 24 through the memory control unit 20 to the processor section 22 is in terms of 16-bit memory words, the execution of the prefetch operation is accomplished most efficiently if the memory is accessible in increments of 8-bits; that is, if an access at address N will return bytes N and N+1, and an access at addressed N+1 will return bytes
N+ 1 and N+2. As indicated earlier, this capability is offered by the memory system disclosed in the copending application No. (filed concurrently herewith) assigned to the assignee of the instant application.
As each prefetch operation is completed, the opcode stored in the instruction register 60 and in any operands stored in the input latch 68 are available for transfer to the processor section 22 upon command. In most cases, the prefetch operation will have been completed before the processor section is finished executing the present instruction. In those cases where the processor section finishes its operation before the prefetch operation is complete, significant time advantage is still achieved by the prior initiation of the prefetch operation.
The terms and expressions which have been used in the foregoing specification are used therein as terms of description and not of limitation, and there is no intention, in the use of such expressions, of excluding equivalents of the features shown and described or portions thereof, it being recognized that the scope of the invention is defined and limited only by the claims which follow.
Claims (11)
1. Means associated with a digital processor for prefetching an opcode portion and an operand portion of an instruction word independent of the operation of said processor, said means comprising:
(a) memory means for storing an instruction word defining a logical operation to be performed;
(b) processor means responsive to the receipt of said instruction word for performing said logical operation defined thereby; (c) means associated with said memory means for retrieving an opcode portion of said instruction word;
(d) means independent of the operation of said processor means and responsive to said opcode for retrieving an operand portion of said instruction word; and
(e) means for transferring said opcode -portion and said operand portion of said instruction word to said processor means for execution.
2. The instruction prefetch means of claim 1 wherein said operand retrieving means (d) includes means for transforming said opcode into a control signal representative of a location of said operand, and means responsive to said signal for retrieving said operand from said location.
3. The instruction prefetch means f claim 1 wherein said memory means includes a plurality of storage locations for storing a like plurality of said instruction words, each said storage location being identifiable by a unique address, and wherein said opcode retrieving means (c) includes program counter means for maintaining an address signal representative of the address in said memory means of the next instruction word to be retrieved.
4. The instruction prefetch means of claim 3 wherein said operand fetching means (d) includes means for retrieving a next instruction word at a storage location in said memory means specified by the address signal currently maintained in said program counter means.
5. The instruction prefetch means of claim 1 wherein said opcode retrieving means (c) includes means for retrieving from said memory means both an opcode portion and an operand portion of said instruction word, first register means for holding said retrieved opcode, and second register means for holding said retrieved operand, wherein said operand retrieving means (d) includes means responsive to said opcode for producing a control signal indicative of the presence in said second register means of said operand, and wherein said instruction word transferring means (e) includes means responsive to said control signal for transferring said opcode from said first register means and said operand from said second register means to said processor means.
6. A method of prefetching an opcode portion and an operand portion of a digital instruction word for subsequent execution by a digital processor, said method comprising the steps of:
(a) providing memory means for storing a plurality of digital instruction words, each of which words defines a logical operation to be performed;
(b) providing processor means responsive to the receipt of a digital instruction word for performing a logical operation defined thereby;
(c) retrieving from said memory means an opcode portion of a first said instruction word;
(d) independent of the operation of said processor means and responsive to said opcode, retrieving an operand portion of said first instruction word; and
(e) transferring said opcode portion and said operand portion of said first instruction word to said processor means for execution.
7. The instruction prefetch method of claim 6 wherein said step (d) includes the steps of transforming said retrieved opcode into a control signal representative of#a location of said operand and retrieving said operand from said location represented by said signal.
8. The instruction prefetch method of claim 6 wherein said step (c) includes the step of maintaining in a program counter the address of a next instruction word to be retrieved.
9. The instruction prefetch method of claim 8 wherein said step (d) includes the step of retrieving a next instruction word from said memory means at a storage location specified by the address currently maintained in said program counter.
10. The instruction prefetch method of claim 6 wherein said step (c) includes the steps of retrieving both said opcode portion and said operand portion of said instruction word, storing said opcode portion in a first register, and storing said operand portion in a second register, and wherein said step (d) includes producing a control signal indicative of the presence in said second register of said operand, and wherein said step (e) includes the step of transferring said opcode from said first register and said operand from said second register to said digital processor.
11. Means for fetching instructions and operands in a digial processor system, substantially as herein described with reference to the accompanying drawing.
1 2. A method of fetching instructions and operands in a digital processor system, substantially as herein described with reference to the accompanying drawing.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US3284279A | 1979-04-24 | 1979-04-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| GB2047928A true GB2047928A (en) | 1980-12-03 |
Family
ID=21867110
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB8012813A Withdrawn GB2047928A (en) | 1979-04-24 | 1980-04-18 | Means and Method Within a Digital Processing System for Prefetching both Operation Codes and Operands |
Country Status (6)
| Country | Link |
|---|---|
| JP (1) | JPS5815810B2 (en) |
| CA (1) | CA1134952A (en) |
| DE (1) | DE3015876A1 (en) |
| FR (1) | FR2455316A1 (en) |
| GB (1) | GB2047928A (en) |
| NL (1) | NL8001189A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2513410A1 (en) * | 1981-09-21 | 1983-03-25 | Racal Data Communications Inc | MICROPROCESSOR AND METHOD FOR INORGANIZING ACCESS IN MEMORY OF THIS MICROPROCESSOR |
| GB2123995A (en) * | 1981-10-02 | 1984-02-08 | Hitachi Ltd | Arithmetic operating system |
| GB2169115A (en) * | 1984-12-29 | 1986-07-02 | Sony Corp | Method of operating microprocessors |
| WO1987001482A1 (en) * | 1985-08-29 | 1987-03-12 | Ncr Corporation | Data processing system including a prefetch circuit |
| WO1997048042A1 (en) * | 1996-03-26 | 1997-12-18 | Advanced Micro Devices, Inc. | An operand cache for reducing latency of read instructions |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5053941A (en) * | 1986-08-29 | 1991-10-01 | Sun Microsystems, Inc. | Asynchronous micro-machine/interface |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3840861A (en) * | 1972-10-30 | 1974-10-08 | Amdahl Corp | Data processing system having an instruction pipeline for concurrently processing a plurality of instructions |
| JPS50128948A (en) * | 1974-03-29 | 1975-10-11 | ||
| FR2298138A1 (en) * | 1975-01-16 | 1976-08-13 | Int Computers Ltd | Data processing with stages operated to different sequential phases - using programmed memory with access to provide operating status |
| JPS51111026A (en) * | 1975-03-26 | 1976-10-01 | Hitachi Ltd | Information management equipment |
-
1980
- 1980-01-31 CA CA000344774A patent/CA1134952A/en not_active Expired
- 1980-02-27 NL NL8001189A patent/NL8001189A/en not_active Application Discontinuation
- 1980-04-18 GB GB8012813A patent/GB2047928A/en not_active Withdrawn
- 1980-04-22 JP JP55053469A patent/JPS5815810B2/en not_active Expired
- 1980-04-22 FR FR8009468A patent/FR2455316A1/en not_active Withdrawn
- 1980-04-24 DE DE19803015876 patent/DE3015876A1/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2513410A1 (en) * | 1981-09-21 | 1983-03-25 | Racal Data Communications Inc | MICROPROCESSOR AND METHOD FOR INORGANIZING ACCESS IN MEMORY OF THIS MICROPROCESSOR |
| GB2123995A (en) * | 1981-10-02 | 1984-02-08 | Hitachi Ltd | Arithmetic operating system |
| GB2169115A (en) * | 1984-12-29 | 1986-07-02 | Sony Corp | Method of operating microprocessors |
| AT396409B (en) * | 1984-12-29 | 1993-09-27 | Sony Corp | MICROCALCULATOR WITH IMPROVED COMMAND CYCLE |
| US5630085A (en) * | 1984-12-29 | 1997-05-13 | Sony Corporation | Microprocessor with improved instruction cycle using time-compressed fetching |
| US6484252B1 (en) * | 1984-12-29 | 2002-11-19 | Sony Corporation | Microprocessor with improved instruction cycle using time-compressed fetching |
| WO1987001482A1 (en) * | 1985-08-29 | 1987-03-12 | Ncr Corporation | Data processing system including a prefetch circuit |
| WO1997048042A1 (en) * | 1996-03-26 | 1997-12-18 | Advanced Micro Devices, Inc. | An operand cache for reducing latency of read instructions |
Also Published As
| Publication number | Publication date |
|---|---|
| DE3015876A1 (en) | 1980-10-30 |
| JPS55143654A (en) | 1980-11-10 |
| CA1134952A (en) | 1982-11-02 |
| JPS5815810B2 (en) | 1983-03-28 |
| FR2455316A1 (en) | 1980-11-21 |
| NL8001189A (en) | 1980-10-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP0138419B1 (en) | Central processing unit for a digital computer | |
| US4415969A (en) | Macroinstruction translator unit for use in a microprocessor | |
| US4742451A (en) | Instruction prefetch system for conditional branch instruction for central processor unit | |
| US4454578A (en) | Data processing unit with pipelined operands | |
| EP0415366B1 (en) | Microprocessor having predecoder unit and main decoder unit operating in pipeline processing manner | |
| US6654875B1 (en) | Dual microcode RAM address mode instruction execution using operation code RAM storing control words with alternate address indicator | |
| EP0199173B1 (en) | Data processing system | |
| KR100267098B1 (en) | Vector processor design to reduce register file read ports | |
| US4225920A (en) | Operator independent template control architecture | |
| US5249280A (en) | Microcomputer having a memory bank switching apparatus for accessing a selected memory bank in an external memory | |
| EP0248436A2 (en) | Method of and apparatus for processing data | |
| USRE32493E (en) | Data processing unit with pipelined operands | |
| US4223381A (en) | Lookahead memory address control system | |
| US3936803A (en) | Data processing system having a common channel unit with circulating fields | |
| US4620274A (en) | Data available indicator for an exhausted operand string | |
| US4747044A (en) | Direct execution of software on microprogrammable hardware | |
| CA1134952A (en) | Means and method within a digital processing system for prefetching both operation codes and operands | |
| US4812971A (en) | Central processing unit for a digital computer | |
| JPH0296233A (en) | Operand disignator processing | |
| US4611278A (en) | Wraparound buffer for repetitive decimal numeric operations | |
| CA2003004C (en) | Apparatus and method for executing a conditional branch instruction | |
| US4893235A (en) | Central processing unit for a digital computer | |
| US4608633A (en) | Method for decreasing execution time of numeric instructions | |
| US4258420A (en) | Control file apparatus for a data processing system | |
| US4575795A (en) | Apparatus for detecting a predetermined character of a data string |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |