GB2047461A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
GB2047461A
GB2047461A GB7913682A GB7913682A GB2047461A GB 2047461 A GB2047461 A GB 2047461A GB 7913682 A GB7913682 A GB 7913682A GB 7913682 A GB7913682 A GB 7913682A GB 2047461 A GB2047461 A GB 2047461A
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region
layer
junction
passivating layer
major surface
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GB7913682A
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Philips Electronics UK Ltd
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Philips Electronic and Associated Industries Ltd
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Application filed by Philips Electronic and Associated Industries Ltd filed Critical Philips Electronic and Associated Industries Ltd
Priority to GB7913682A priority Critical patent/GB2047461A/en
Priority to FR8008313A priority patent/FR2454702A1/en
Priority to DE19803014488 priority patent/DE3014488A1/en
Priority to JP4963580A priority patent/JPS55141732A/en
Publication of GB2047461A publication Critical patent/GB2047461A/en
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/408—Electrodes ; Multistep manufacturing processes therefor with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3192—Multilayer coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Abstract

A semiconductor device has a region (2) and a more highly doped zone (4) of opposite conductivity types which together form a p-n junction (5) which terminates at a major surface (3) of a semiconductor body (1), there being a first passivating layer (10) which covers the whole termination of said junction (5) at said surface (3) and which contains electric charge of the same sign as the conductivity type of said region (2), and a second passivating layer (12) provided on said major surface (3) to adjoin a part of the region (2) which is spaced from the termination of said p-n junction (5) and which extends laterally around the whole of this termination. This second passivating layer (12) is of semi-insulating material, for example chalcogenide material or polycrystalline silicon, sufficiently conductive to shield the surface of the underlying part of said region (2) from effects of any external electric charge in order to stabilize the blocking characteristics of the junction (5). <IMAGE>

Description

SPECIFICATION Semiconductor devices This invention relates to semiconductor devices, for example rectifier diodes, transistors and thyristors having a p-n junction which is operated under reverse-bias in at least one mode of operation of the device.
Many types of semiconductor device are known comprising a semiconductor body having a region of one conductivity type adjoining a major surface of said body, and a more highly doped zone of the opposite conductivity type also adjoining said major surface and forming with said region a p-n junction which terminates at said major surface and is operated under reverse-bias in at least one mode of operation of the device. On said major surface a passivating layer covers both the whole termination of said p-n junction at the major surface and the adjacent parts of said region and zone. It is also known for the passivating layer to comprise electrically insulating material which at least during operation in said one mode contains electric charge of the same sign as the conductivity type of said region.Preferably the passivating layer contains such charge when the layer is provided in the manufacture of the device. However, the Applicants have found that, during operation of the device in the reverse-bias mode of the p-n junction, such charge can accumulate in the passivating layer even when the passivating layer provided in manufacture was originally electrically neutral.
Such a charge-containing passivating layer enhances the breakdown voltage of the p-n junction because the charge in the layer tends to widen at the major surface the depletion layer formed around the junction under reverse-bias and also tends to reduce curvature of this depletion layer. In the absence of this charge layer, the effect of charged states at the major surface can narrow the depletion layer significantly adjacent the surface as compared with its width in the bulk of the semiconductor body so that breakdown of the junction occurs adjacent the surface and at a reverse voltage lower than that which would occur for breakdown in the bulk of the semiconductor body.
However, the Applicants have found that the stability of the junction in blocking reverse voltages for a prolonged time and/or at a high junction temperature can sometimes be adversely affected; thus, when the device is subjected to a test of its D.C. voltage blocking capability for, for example, 1,000 hours at a reverse-bias of 500 volts and a junction temperature of 1 25 C, the reverse leakage current across the junction can increase during the test to an unacceptable extent. Such instability occurs particularly but not exclusively when the device body is encapsulated in synthetic resin covering the charged passivating layer. The mechanism resulting in this instability is not precisely understood.There is a tendency for the passivating layer to become polarised when the junction is reversebiased, and so the reverse-leakage current generated in the depletion layer increases.
This tendency seems to be increased by migration and accumulation of ions in the synthetic resin under the influence of the applied electric fields. In some cases it appears that this can even invert the conductivity type of the underlying surface part of the region of the one conductivity type. Such an inversion of conductivity type may effectively extend the p-n junction to the edge of the body which can be an electrically unstable region.
According to the present invention a semiconductor device comprising a semiconductor body having a region of one conductivity type adjoining a major surface of said body, and a more highly doped zone of the opposite conductivity type also adjoining said major surface and forming with said region a p-n junction which terminates at said major surface and is operated under reverse-bias in at least one mode of operation of the device, a first passivating layer on said major surface and covering both the whole termination of said p-n junction at said major surface and the adjacent parts of said region and zone, said first layer comprising electrically insulating material which at least during operation in said one mode contains electric charge of the same sign as the conductivity type of said region, is characterised in that a second passivating layer on said major surface adjoins a part of the said region which is spaced from the termination of said p-n junction and which extends laterally around the whole of the termination of said p-n junction at said surface, said second passivating layer being of semi-insulating material sufficiently conductive to shield the surface of the underlying part of said region from effects of any external electric charge.
Such semiconductor devices in accordance with the invention have an advantageous combination of passivating layers; the first passivating layer having the electric charge can enhance the breakdown voltage of the p-n junction as in known devices, while the second passivating layer which is slightly conductive and spaced from the termination of the p-n junction helps to stabilize the block: ing characteristics of the junction. Because the second passivating layer is slightly conductive it can shield this underlying part of said region from any electric charge in overlying materials (for exampie a synthetic resin encapsulation), and can prevent inversion of the conductivity type of the underlying part of said region adjacent the surface.Also because of its slightly conductive nature the second passivating layer can reduce the lateral electric field in the underlying part of the region by gradually and gently dropping the voltage which is associated with this part under reverse-bias operation of the junction.
Preferably an insulating layer extends over said second passivating layer to protect the underlying second passivating layer and so enhance the passivation of the semiconductor surface. Such a protective layer may be deposited on said second passivating layer, or it may even be formed from said second passivating layer, for example by oxidation of its surface. Any charge-content of the protective layer need not be problematic because of the shielding effect of the second passivating layer. Thus the first passivating layer may also act as this protective layer by extending onto and over the second passivating layer. This is a particularly simple structure to manufacture.
In order to obtain high breakdown-voltages, said major surface is preferably a non-planar surface having a mesa portion adjoined by the said zone so that the said p-n junction is a substantially flat junction terminating at the side walls of the mesa portion which are covered by the said first passivating layer. A device having such a mesa structure is further characterized in accordance with the present invention in that the second passivating layer adjoins a surface portion of said region which extends laterally around the mesa portion.
Advantages of these and other features in accordance with the invention will now be described with reference to the accompanying diagrammatic drawings, illustrating by way of example some embodiments of the present invention.
Figure 1 is a plan view of a semiconductor device in accordance with the invention; Figure 2 is a cross-sectional view of part of one example of the device of Fig. 1, taken on the line lI-Il of Fig. 1; Figure 3 is a partly perspective and partly sectional view of a thyristor in accordance with the invention, and Figure 4 is a cross-sectional view similar to that of Fig. 2, but of a further semiconductor device in accordance with the invention.
It should be noted that the Figures are not drawn to scale, and the relative dimensions and proportions of some parts of these Figures have been shown exaggerated or reduced for the sake of clarity and convenience, especially in the cross-sectional views. The same reference numerals are used in the different Figures to indicate not only the same portions of the same device but also corresponding portions of different devices.
The type of semiconductor device illustrated in Figs. 1 and 2 comprises a monocrystalline silicon semiconductor body 1 having a region 2 of one conductivity type (rrtype, in the example of Fig. 2) adjoining its upper major surface 3. A more highly doped zone 4 of the opposite conductivity type (type, in the example of Fig. 2) also adjoins the surface 3 and forms with the region 2 a p-n junction 5 which terminates at the surface 3 in a closed figure shown as a dot-dash line in Fig. 1. The junction 5 is operated under reverse-bias in at least one mode of operation of the device. As will be discussed in more detail hereinafter, the p-n junction 5 of Fig. 1 may be, for example, the rectifying junction of a power rectifier diode, or the base-collector junction of a power transistor, or for example one of the blocking junctions of a thyristor.
A first passivating layer 10 is present on the surface 3 and covers both the whole of the termination of the junction 5 at the surface 3 and the adjacent parts of the region 2 and zone 4. This layer 10 is indicated in the plan view of Fig. 1 by hatching between its inner edge which is denoted by line 11 and its outer edge which coincides substantially with the outer edge of the body 1 in this example.
The layer 10 comprises electrically insulating material containing electric charge of the same sign as the conductivity type of region 2 thereby enhancing the breakdown voltage of junction 5. In the example of Fig. 2 where the region 2 has ntype conductivity the layer 10 contains negative electric charge and may be of glass, for example glass available from lnnotech Corporation, U.S.A., under the trade mark IP 820. The layer 10 can be formed in known manner using electrophoretic deposition or so-called "doctor-blading".
A second passivating layer 12 on the surface 3 adjoins a part of region 2 which is spaced from the termination of junction 5 and which extends laterally around the whole of the termination of junction 5 at the surface 3.
This layer 12 is indicated in the plan view of Fig. 1 by hatching which is transverse to that of layer 10. The inner edge of the layer 12 (which is defined photolithographically) is denoted by line 13 and its outer edge coincides substantially with the outer edge of the body 1.
The layer 12 is of semi-insulating material sufficiently conductive to shield the surface of the underlying part of region 2 from external electric fields and to prevent inversion of the conductivity type of this underlying part adjacent the surface 3. For this purpose, the material of the layer 12 will generally be chosen so as to have a resistivity of between approximately 107 and 1010 ohm-cm.
Various materials may be used for the semiinsulating layer 12, for example a chalcogenide material or oxygen-doped polycrystalline silicon. Suitable chalcogenide materials for the layer 12 are described in the article by Smeets et al in Journal of Electrochemical Society, Solid-State Science and Technology, September 1977, pages 1458 and 1459.
The formation of oxygen-doped polycrystalline silicon is described in for example U.K. Patent (GB) 1,496,814; for the type of device of Figs. 1 and 2; the oxygen content of the polycrystalline silicon layer 12 will generally be between 10 and 40 atomic per cent, for example approximately 20 to 25 atomic per cent. In some cases it may even be possible to use, for example, undoped polycrystalline silicon (which may have a resistivity of approximately 106 ohm-cm) for the layer 12.
As shown in the example of Fig. 2, the major surface 3 of the body 1 is a non-planar surface having a mesa portion 23 adjoined by the zone 4. Such a non-planar surface 3 can be obtained using a known mesa-etching technique to etch the body locally to a depth greater than that of the junction 5. The p-n junction 5 is a substantially flat junction terminating at the side walls of the mesa portion 23, and these side walls are covered by the first passivating layer 10. The semi-insulating second passivating layer 12 adjoins a surface portion of region 2 which is spaced from the mesa portion 23 and which extends laterally around the mesa portion 23. This combination of the first and second passivating layers 10 and 12 in a mesa structure permits the obtaining of high breakdown voltages for the junction 5.
In the arrangement of Fig. 2 the semiconductor body 1 is mounted on a metal base 20 which may be for example part of a copper lead-comb. The metal base 20 forms an electrical connection to a highly doped semiconductor layer 22 which is present between the rrtype region 2 and the bottom major surface 24 of the body 1. An electrode 25 which may be for example an aluminium layer contacts the zone 4 at the top of the mesa portion 23.
The body 1 is encapsulated on the base 20 by synthetic resin 26 which forms a device envelope covering the passivating layers 10 and 12 and the whole of the remainder of the top and sides of the device body.
The semi-insulating layer 12 shields the underlying part of region 2 from the effects of induced charge and migrating charge in the synthetic resin 26 and from any charge polarization and other charge-effects of the overlying part of layer 10. In this way it stabilizes the reverse-blocking capability of the junction 5 5 even when reverse-biased for a prolonged time and at a high junction temperature. Furthermore if any conductivity type inversion of the surface of region 2 occurs between the layer 12 and the termination of junction 5, the inversion layer formed terminates gradually and gently below the layer 12. Thus, such an inversion layer is interrupted gently and without needing to locally increase the doping of the rrtype region 2.This is a further advantage arising from the invention because such a local increase in doping would require the extra provision of a highly-doped n type zone (n +) beyond the extent of the depletion layer 15, and would abruptly terminate any Rtype inversion layer at a highlydoped n + boundary so that, if the surface became strongly inverted to p +, the resulting n + /p + junction extension of the junction 5 would have a low breakdown voltage.
Preferably the inner edge of the layer 12 is spaced from the termination of the junction 5 by a distance corresponding to approximately the maximum spread of the depletion layer along the surface 3 before breakdown of the junction 5. In this way a compact structure is obtained without the spread of the depletion layer being restricted by the presence of the layer 12.
The device of Fig. 2 may be, for example, a rectifier diode having a moulded plastics envelope 26. In this case, the region 2 is typically a high resistivity substrate in which the more highly doped zone 4 and layer 22 are formed by diffusion of acceptor and donor dopant respectively. The electrode 25 may contact the zone 4 via a window defined by the whole inner edge 11 of the glass layer 10.An example of such a diode fabricated by the Applicants had the following dimensions and doping: the region 2 had a thickness and resistivity of 90 microns and 40 ohm-cm respectively; the zone 4 and layer 22 had thicknesses of 50 and 70 microns respectively and respective surface doping concentrations of 1020 boron atoms/c.c. and 102' phosphorus atoms/c.c.; the depth of the recess forming the mesa portion 23 was 70 microns; the respective thicknesses of the layers 10 and 12 were 20 and 0.5 microns and the resistivity of the layer 12 was approximately 2.5 X 108 ohm-cm; the inner edge 13 of layer 12 was spaced approximately 130 microns from the termination of the junction 5, and the top of the mesa had an area of 1.5 m.m. by 1.5 m.m.With a D.C. reverse bias of 500 volts applied across junction 5 between the connections 20 and 25 at a junction temperature of 1 50'C, the reverse leakage current was approximately 200 microAmps (yA) initially and approximately 500 microAmps after 1,000 hours. This increased current level was a steady non-increasing value, there being no significant increase in the reverse leakage current after the initial 350 hours. The same test was also performed on another diode which had substantially the same structure but without the incorporation of a slightly conductive semi-insulating layer 12 below part of the glass layer 10; this other diode also had a reverse leakage current of approximately 200 microAmps (yA) initially which increased to 1700 microAmps after only 250 hours and thereafter continued to increase at this rate.
The incorporation of the layer 12 therefore significantly stabilized the blocking characteristics of the junction 5.
The device illustrated in Fig. 2, may however be a power transistor. In this case, the region 2 is typically an epitaxial layer deposited on a highly doped substrate 22 of the same conductivity type which together form the collector region of the transistor. The opposite conductivity type zone 4 then forms the base region having a base contact 25.
Junction 5 is therefore the collector-base junction. At least one emitter region of the same conducitivity type as region 2 (r-type, in the example shown) is provided locally in the base zone 4 within a part of the mesa portion 23 which is not shown in Fig. 2, and has an emitter contact also not shown in Fig. 2. The emitter and base contacts have sparate contact windows in an insulating layer on top of the mesa portion 23.
However as mentioned hereinbefore the junction 5 of Fig. 1 may even be one blocking junction of a thyristor. In this case the Fig. 2 structure is slightly modified. The region 2 is typically a high resistivity rrtype substrate in which the more highly doped zone 4 and layer 22 are formed by diffusion of the same acceptor dopant(s) in the same diffusion step.
Thus, the zone 4 and layer 22 are in this case of the same conductivity type (ptype). Except when the thyristor is a triac (which is a bidirectional device), the ptype layer 22 now constitutes the anode of the thyristor. A cathode formed by an rrtype emitter region is provided locally in the frtype base zone 4 in a similar manner to the hereinbefore described emitter region of a power transistor. Such an emitter-base configuration in a mesa-portion 23 is illustrated in Fig. 3 where the additional reference numerals 30, 31 and 32 respectively denote a cathode emitter region, a cathode contact and an insulating layer on the top of the mesa portion 23.
In the case of a thyristor the termination of the p-n junction between the rrtype region 2 and the ptype layer 22 should also be passivated. This may be effected by mesa-etching the surface 24 of the body 1 so that this p-n junction terminates below a glass layer at the side wall of the resulting mesa. This glass layer may be provided on the mesa-etched surface 24 in substantially the same manner as layer 10 on the surface 3, and a semiinsulating layer similar to layer 12 may also be provided below the glass layer.However, Fig. 3 illustrates another possible way of passivating the p-n junction 35 between the p- type layer 22 and the rrtype region 2; in this case the recess forming the mesa portion 23 in surface 3 does not.extend to the edge of the body 1 which is bounded throughout its thickness by a peripheral ptype region 37.
This peripheral region 37 extends the p-n junction 35 to the surface 3 where it terminates at the outer side of the recess below the glass layer. The semi-insulating layer 12 is present between the terminations of the two p-n junctions 35 and 5.
In the case of a triac an additional rrtype emitter region is provided in the ptype layer 22 adjacent the surface 24 and is shorted to the layer 22 by an electrode connection over the surface 24.
In the devices of Figs. 1 to 3, the glass layer 10 extends onto and over the semiinsulating layer 12 to protect the semi-insulating layer 12 against moisture and other contaminants and so to enhance the passivation of the semiconductor surface. This is a particularly simple structure to manufacture, and the layer 12 can be thin compared with the thick glass layer 10. However as illustrated in Fig. 4, the semi-insulating layer 12 may be covered by a different protective insulating layer which is denoted by reference 42 and which may be formed by, for example, deposition of silicon dioxide or in some cases oxidation of the surface of the layer 12.
It will be evident that many other modifications are possible within the scope of this invention. Thus, for example as illustrated in Fig. 4, the synthetic resin 26 encapsulating the semiconductor body 1 need not be a moulded plastics envelope but may be, for example, a silicon rubber coating on the device body 1 which is subsequently incorporated in an hermetically-sealed envelope or housing; similar instability problems due to charge effects can occur with such a synthetic resin coating as with a moulded-plastics envelope.
A further modification is shown in Fig. 4, where the surface 3 is substantially plane and does not comprise a mesa portion. In this case the zone 4 is also laterally surrounded by the region 2, and the p-n junction 5 is no longer flat but extends upwards via a side-wall portion to terminate at the surface 3. Compared with the mesa structures of Figs. 1 to 3, the junction 5 has a lower blocking voltage. In order to increase this blocking voltage capability preferably at least one or more rings 44 are provided around the zone 4 to control the spread of the depletion layer. These rings 44 are annular zones which are provided in the region 2 and are of the same conductivity type as the zone 4. Such rings are described in, for example, United States (U.S.) Patent 3,391,287. Although only one ring is illustrated in Fig. 4, it will generally be desirable to use for example as many as three. However, besides having a lower blocking voltage such a structure can require considerably more space on the semiconductor body 1 compared with the very compact mesa structure of Figs. 1 and 2.
It will also be evident that the conductivity types of all the regions of the devices of Figs.
1 to 4 may be reversed. In this case, the region 2 would be ptype so the layer 10 of glass or other insulating material (for example silicon dioxide) would contain positive electric charge. Although in the embodiments described the semiconductor device body is of silicon, it will be evident that other suitable semiconductor materials may be used to form particular devices in accordance with the invention.
In the embodiments as described so far the first passivating layer 10 has been shown as a single layer, for example of glass or silicon dioxide. However, combinations of layers may be used for the passivating layer 10, and only one layer of the combination need contain the electric charge. The charge associated with layer 10 need not be present in the bulk of such a layer but may be contained at an interface of the layer. Furthermore as mentioned hereinbefore the layer 10 need not be formed in a charged state during manufacture, but may originally be electrically neutral and accumulate the charge during operation when the junction 5 is reverse-biased. However, it is generally preferable for the layer 10 formed during manufacture to contain charge in order to enhance the breakdown voltage of the junction 5 when operation of the device is started.

Claims (10)

1. A semiconductor device comprising a semiconductor body having a region of one conductivity type adjoining a major surface of said body, and a more highly doped zone of the opposite conductivity type also adjoining said major surface and forming with said region a p-n junction which terminates at said major surface and is operated under reversebias in at least one mode of operation of the device, a first passivating layer on said major surface and covering both the whole termination of said p-n junction at said major surface and the adjacent parts of said region and zone, said first layer comprising electrically insulating material which at least during operation in said one mode contains electric charge of the same sign as the conductivity type of said region, characterized in that a second passivating layer on said major surface adjoins a part of the said region which is spaced from the termination of said p-n junction and which extends laterally around the whole of the termination of said p-n junction at said surface, said second passivating layer being of semi-insulating material sufficiently conductive to shield the surface of the underlying part of said region from effects of any external electric charge.
2. A device according to Claim 1, further characterized in that a protective insulating layer extends over said second passivating layer.
3. A device according to Claim 2, further characterized in that the first passivating layer also acts as said protective insulating layer by extending onto and over the second passivating layer.
4. A device according to any of the preceding Claims, further characterized in that said major surface is a non-planar surface having a mesa portion adjoined by the said zone, in that the said p-n junction is a substantially flat junction terminating at the side walls of the mesa portion which are covered by the said first passivating layer, and in that the second passivating layer adjoins a surface portion of said region which extends laterally around the mesa portion.
5. A device according to any of the preceding Claims, further characterized in that the second passivating layer is of chalcogenide material.
6. A device according to any of Claims 1 to 4, further characterized in that the second passivating layer is of oxygen-doped polycrys talline silicon.
7. A device according to any of the preceding Claims, further characterized in that said first passivating layer comprises glass containing negative electric charge, the said region having rrtype conductivity.
8. A device according to any of Claims 1 to 6, further characterized in that said first passivating layer comprises silicon dioxide containing positive electric charge, said region having ptype conductivity.
9. A device according to any of the preceding Claims, further characterized in that the first and second passivating layers are covered with synthetic resin which encapsulates the semiconductor body.
10. A semiconductor device substantially as described with reference to any of Figs. 1 to 4 of the accompanying drawings.
GB7913682A 1979-04-19 1979-04-19 Semiconductor device Withdrawn GB2047461A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
GB7913682A GB2047461A (en) 1979-04-19 1979-04-19 Semiconductor device
FR8008313A FR2454702A1 (en) 1979-04-19 1980-04-14 SEMICONDUCTOR DEVICE, IN PARTICULAR DIODE, TRANSISTOR, THYRISTOR COMPRISING IMPROVED PASSIVATION MEANS
DE19803014488 DE3014488A1 (en) 1979-04-19 1980-04-16 SEMICONDUCTOR ARRANGEMENTS
JP4963580A JPS55141732A (en) 1979-04-19 1980-04-17 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB7913682A GB2047461A (en) 1979-04-19 1979-04-19 Semiconductor device

Publications (1)

Publication Number Publication Date
GB2047461A true GB2047461A (en) 1980-11-26

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Family Applications (1)

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GB7913682A Withdrawn GB2047461A (en) 1979-04-19 1979-04-19 Semiconductor device

Country Status (4)

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JP (1) JPS55141732A (en)
DE (1) DE3014488A1 (en)
FR (1) FR2454702A1 (en)
GB (1) GB2047461A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0082224A1 (en) * 1981-12-22 1983-06-29 Hitachi, Ltd. Semiconductor device passivated with glass material
EP0217326A2 (en) * 1985-09-30 1987-04-08 Kabushiki Kaisha Toshiba Semiconductor device with a high breakdown voltage
EP2573814A1 (en) * 2006-09-28 2013-03-27 Fujifilm Corporation Solid-state image sensor

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1430438A (en) * 1964-04-16 1966-03-04 Northern Electric Co Semiconductor devices incorporating a conductive screen
IT951158B (en) * 1971-06-23 1973-06-30 Rca Corp SEMICONDUCTIVE DEVICE WITH MANY STABLE JUNCTIONS FOR HIGH VOLTAGES
JPS5218070B2 (en) * 1972-10-04 1977-05-19
IT1192117B (en) * 1976-07-05 1988-03-31 Ates Componenti Elettron PRO-ROOF SEMICONDUCTOR DEVICE AGAINST IONIC CHARGES OF THE ENVIRONMENT

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0082224A1 (en) * 1981-12-22 1983-06-29 Hitachi, Ltd. Semiconductor device passivated with glass material
EP0217326A2 (en) * 1985-09-30 1987-04-08 Kabushiki Kaisha Toshiba Semiconductor device with a high breakdown voltage
EP0217326A3 (en) * 1985-09-30 1987-12-02 Kabushiki Kaisha Toshiba Semiconductor device with a high breakdown voltage
US5031021A (en) * 1985-09-30 1991-07-09 Kabushiki Kaisha Toshiba Semiconductor device with a high breakdown voltage
EP2573814A1 (en) * 2006-09-28 2013-03-27 Fujifilm Corporation Solid-state image sensor

Also Published As

Publication number Publication date
JPS55141732A (en) 1980-11-05
FR2454702A1 (en) 1980-11-14
DE3014488A1 (en) 1980-10-30

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