GB2044585A - Multiple input programmable signal conditioner and commutator - Google Patents

Abstract

A signal commutator selectively passes one of a plurality of input signals to a variable amplifier (504) in an order determined by order information stored in a memory circuit (512). The gain and offset of the amplifier (504) is varied as indicated by operational information also stored in the memory circuit (512) to achieve a standard output signal as each input signal is coupled to the amplifier. Preferably there are two variable amplifiers with one amplifier being adjusted to proper settings while the other amplifier operates on an input signal. <IMAGE>

Description

SPECIFICATION Multiple input programmable signal conditioner and commutator The present invention relates to a signal conditioner and commutator for a plurality of input signals.

Conventional systems which interweave two or more input signals into a single output for transmission employ individual signal conditioners for each input signal and then pass the signals to a commutator which sequentially looks at each pre-conditioned input signal.

The conditioning typically adjusts the range and offset of each input signal to standardize the input signals for transmission. The commutator, in effect, serves only as an electronic switch with one pole and a plurality of positions, one for each input signal.

In such conventional systems, each of the plurality of input signals is being conditioned 100 percent of the time by the respective signal conditioners while the commutator is looking at only one conditioned signal at a time. Thus, if 1 28 input signals were employed, 1 27 conditioned signals are unutiiized at any given time.

Since each signal conditioner typically requires three resistors and several operational amplifiers to achieve suitable range and offset, it is apparent that such systems are rather inefficient. This inefficiently results in a system with excessive power requirements and reliability problems and with excessive volume allocated to the signal conditioning function.

Furthermore, operational flexibility in such conventional systems is severely limited by the requirement of removing and replacing various resistors for each input signal when the preconditioning function must be varied.

Flexibility is also reduced by the requirement of modifying jumper circuits when the pattern of commutation must be altered.

It is, accordingly, an object of the present invention to provide an apparatus for achieving required signal conditioning and commutating in an efficient yet flexible manner.

It is another object of the present invention to provide an apparatus of a reduced component count, volume, power consumption, and weight which achieves conditioning and commutating of a plurality of input signals.

It is still another object of the present invention to provide a signal conditioning apparatus which achieves optimum flexibility in responding to changes in signal conditioning and commutating requirements.

Additional objects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and the advantages may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims.

In accordance with the purposes of the invention as embodied and broadly described herein, a commutating signal conditioner for a plurality of input signals of the present invention comprises: (a) a variable amplifier means; (b) memory means for storing operational information for the amplifier means; (c) commutator means for selectively coupling the input signals to the amplifier means; and (d) circuit means for adjusting the variable amplifier means as indicated by the operational information for each input signal coupled to the amplifier means.

Preferably, the variable amplifier means selectively varies the amplitude range of the input signals and/or selectively offsets the input signals. Such a variable amplifier means may, for example, comprise a plurality of digital-to-analog converters and the memory means may, for example, comprise a read only memory.

The circuit means may also comprise means for stepping the commutator means in synchronism with the adjusting of said variable amplifier means to couple the input signals to the amplifier means when the amplifier means is adjusted to properly condition the specific input signal being coupled to the amplifier means. The memory means may also include means for storing order information for determining the order of stepping the commutator means.

In a more limiting sense, the variable amplifier means may comprise: (a) input and output terminals; (b) a reference source; (c) first, second, and third operational amplifiers; (d) a first resistive network coupled between the input terminal and the input to the first operational amplifier; (e) an inverter coupled between the output of the first operational amplifier and the output terminal; (f) a second resistive network coupled between the output terminal and the input terminal of the second operational amplifier, the output of the second operational amplifier being coupled to the input of the first operational amplifier; (g) a third resistive network coupled between the reference source and an input to the third operational amplifier, the output of the third operational amplifier being coupled to the input of the first operational amplifier; and (h) means for varying the resistive networks as indicated by the operational information stored in the memory means.

In another example of the preferred embodiments of the present invention the signal commutator conditioner is operable on a plurality of input signals, and the conditioner comprises: (a) first and second variable amplifiers; (b) memory means for storing operational information for the amplifiers; (c) com mutator means for selectively coupling the input signals to the first and second variable amplifiers; and (d) logic means for setting the first and second variable amplifiers as indicated by the operational information for each input signal coupled to the respective amplifiers, the logic means setting one of the amplifiers while the other of the amplifiers operates on an input signal.

The accompanying drawings, which are incorporated and constitute a part of the specification, illustrate examples of the preferred embodiment of the invention and, together with the general description of the invention given above and the detailed description of examples of the preferred embodiment given below, serve to explain the principles of the invention.

Figure 1 is a block diagram of a conventional commutating signal conditioner; Figure 2 is a block diagram of a commutating signal conditioner in accordance with the teachings of the present invention; Figure 3(a) illustrates a standard non-variable amplifier; Figure 3(b) illustrates a modified form of the non-variable amplifier of Fig. 3(a); Figure 3(c) illustrates a programmable amplifier as may be employed in accordance with the teachings of the present invention; Figure 4 is a schematic diagram of one example of a specific programmable amplifier constructed in accordance with the teachings of the present invention; Figure 5 is a block diagram of another example of a commutating signal conditioner in accordance with the teachings of the present invention;; Figure 6 is an electrical diagram of an example of a commutating signal conditioner as illustrated generally in Fig. 5; Figure 7 is a block diagram of a logic circuit suitable for use in the commutating signal conditioner illustrated in Fig. 6; and Figure 8 is a block diagram of a memory unit suitable for use with the logic circuit illustrated in Fig. 7.

The above general description and the following detailed description are merely illustrative of the generic invention and additional modes, advantages, and particulars of this invention will be readily suggested to those skilled in the art without departing from the scope and spirit of the invention.

Reference will now be make in detail to the present preferred embodiment of the invention, examples of which are illustrated in the accompanying drawings.

Broadly, the present invention relates to a commutating signal conditioner for a plurality of input signals. Such systems are known generally as telemetry systems and as timedivision multiplexing systems. A conventional commutating signal conditioner is indicated in Fig. 1 as comprising signal conditioner unit 200, commutator 202, transmitter 204, and antenna 206. Signal conditioner unit 200 comprises a plurality of individual signal conditioners 208, for example, one for each of a plurality of illustrated input signals 1-1 28.

Commutator 202 comprises a switching mechanism 210 controlled by a logic network 21 2 which causes switching mechanism 210 to sequentially connect conditioned input signals from signal conditioner unit 200 to a single input channel of transmitter 204.

Typically, transmitter 204 will require a pulse amplitude modulation with non-return to zero (PAM-NRZ) signal which has specific amplitude range and offset limitations. For example, transmitter 204 might require a PAM-NRZ signal of + 2 1/2 volts range centered or symmetrical with respect to ground or zero volts. However, input signals 1-128 may have different magnitudes of amplitude range variation and not be zero centered. It is accordingly a function of individual signal conditioners 208 to operate on the amplitude range and offset of the individual input signals, thereby molding or scaling the input signals to the standards required by transmitter 204.

Individual signal conditioners 208 may each comprise, for example, the arrangement illustrated in Fig. 3a including differential or operational amplifiers 214 and 21 6 and resistors 218, 220 and 222. Amplifier 214 has an output coupled back to a negative input terminal and serves the function of a unity gain voltage follower, or buffer, of high input impedance. The function of amplifier 214 is to prevent the signal conditioner from presenting and excessive load to the sources of the input signals. The output of amplifier 214 is coupled through resistor 222 to the negative input of amplifier 216 while the positive input of amplifier 21 6 is coupled to an appropriate bias source, such as ground.Resistors 218 and 220 are series-coupled between bias v, which may be positive or negative, and the output of amplifier 216 while the junction of resistors 218 and 220 is coupled to the negative input of amplifier 216.

As is well-known to those skilled in the art, the gain of the signal conditioner illustrated in Fig. 3a is approximately equal to minus the ratio of resistor 220 over resistor 222 while the offset is equal to minus the ratio of resistor 220 over resistor 218 times the value of bias V. Accordingly, adjustment of resistors 220 and 222 may operate to assure that the gain or attenuation of the signal conditioner establishes an output signal of desirable am plitude range while adjustment of resistors 220 and 218 may assure that the output signal is symmetrical with respect to a chosen point such as ground.

Changes of amplitude range or offset are achieved in such prior art arrangements by replacing one or more of resistors 218, 220 and 222. It is a prime purpose of the present invention to increase the flexibility of such a conventional signal conditioning system while reducing the component count required by such conventional systems to implement large telemetry systems. Additional direct benefits envisioned by the present invention are reduced volume, lower costs for assembly, decreased turn around time to implement changes, and increased system reliability.

In accordance with the present invention, a commutating signal conditioner for a plurality of input signals comprises a variable amplifier means, memory means for storing operational information for the amplifier means, commutator means for selectively coupling input signals to the amplifier means, and circuit means for adjusting the variable amplifier means as indicated by the operational information for each input signal coupled to the amplifier means. The circuit means preferably includes means for stepping the commutator means in synchronism with the adjusting of the variable amplifier means to couple the input signals to the amplifier means when the amplifier means is adjusted to properly condition the specific input signal being coupled to the amplifier means.Furthermore, the memory means may include means for storing order information for determining the order of stepping the commutator means.

As shown by way of illustration and not limitation, an example of a commutating signal conditioner in accordance with the present invention is illustrated in Fig. 2 as comprising commutator 300, programmable or variable amplifier 302, memory unit 304, transmitter 306, and antenna 308. Commutator 300 comprises a random access switching mechanism 310 and a logic network 312. Switching mechanism 310 is in effect an electronic switch with one pole and a plurality of positions, for example, 1 28 positions for 1 28 input signals. Logic network 312 may operate switching mechanism 310 to assure a sequential connection of each of input signals 1-128 from commutator 300 to variable amplifier 302. However, logic network 312 preferably operates switching mechanism 310 in any order governed by order information stored in memory 304.

Variable amplifier 302 is a programmable amplifier which has the capacity of selectively offsetting input signals and has the further capacity of varying the amplitude range or gain of input signals. Variation of amplifier 302 is achieved through attenuation, offset and/or gain control signals supplied from memory unit 304. An explanation of the operation of variable or programmable amplifier 302 may be had with respect to Fig. 3.

As explained above, a conventional signal conditioner as illustrated in Fig. 3a has the capacity of setting the gain or attenuation and offset of a single input signal. The subject invention envisions the utilization of a digital system that in addition to controlling the order of commutation also implements the functions of gain or attenuation and offset compensation in which, in essence, the three resistors 218, 220 and 222 of the signal conditioner of Fig. 3a are replaced by three multiplying digital to analog converters (MDACs) to create a variable or programmable amplifier. Each of these MDACs can, for example, comprise eight bit or 1 2 bit devices in accordance with the ultimate accuracy desired. The value of each MDAC for a particular setting is programmed by digital operational information stored in memory unit 304 of Fig. 2.

As is known to those skilled in the art, MDACs are by their nature essentially attenuation devices and accordingly the circuit of Fig.

3a needs to be modified so as to lend itself to the application of MDACs. The gain function normally controlled by resistor 222 is preferably supplemented by variation in resistor 220.

Furthermore, the gain function of resistor 220 is achieved either by raising the value of resistor 220, which is difficult when utilizing MDACs, or by attenuating the feedback signal supplied through resistor 220 which is a relatively easy operation for MDACs. An analog network to achieve gain control by reduction in feedback is illustrated in Fig. 3b.

In Fig. 3b resistors 218, 220 and 222 are supplemented by the further employment of resistors 314 and 316. Resistor 314 is shown coupled between the output of amplifier 21 6 and resistor 220 while resistor 316 is coupled between the junction of resistors 220 and 314 and bias v'. By dividing or attenuating the output of amplifier 216 through the employment of resistors 314 and 31 6, a reduced signal at the junction of resistors 314 and 316 is provided to drive resistor 220. Since the technique of signal attenuation is employed in the arrangement shown in Fig. 3b, resistors 220, 314 and 316 can be simply replaced by a gain MDAC 318 as illustrated in Fig. 3c. Furthermore, resistor 218 can be replaced by offset MDAC 320 illustrated in Fig. 3c and resistor 222 can be replaced by attenuation MDAC 322 as illustrated in Fig.

3c. A more detailed illustration of the programmable or variable amplifier illustrated in Fig. 3c is shown in Fig. 4.

In Fig. 4 by way of example and not limitation a variable amplifier means suitable for utilization in the present invention is shown to comprise gain MDAC 318, offset MDAC 320, and attenuation MDAC 322. The variable or programmable amplifier further comprises input terminal 396 and output terminal 398, and a reference bias source V.

In accordance with the present invention, a preferred variable amplifier means comprises first, second, and third operational amplifiers illustratively shown in Fig. 4 as operational amplifiers 400, 402 and 404. A variable amplifier means in accordance with the present invention further preferably comprises a first resistive network coupled between the input terminal and an input to the first operational amplifier. As illustratively shown in Fig.

4, a first resistive network comprises resistors 406a through 406n and resistors 408a through 408n. Resistors 406a through 406n are series connected between input terminal 396 and an appropriate source of bias B.

Each first end of resistors 408a through 408n is coupled to a respective ends of resistors 406a through 406n closest to input terminal 396. The free ends of resistors 408a through 408n are coupled respectively through switches 410a through 410n to a common negative input of amplifier 400.

In accordance with the present invention, the variable amplifier means further comprises an inverter coupled between the output of the first operational amplifier and the output terminal. As illustratively shown in Fig. 4 amplifier 21 6 is coupled as an inverter between the output of amplifier 400 and output terminal 398.

Further in accordance with the present in invention, the variable amplifier means comprises a second resistive network coupled between the output terminal and an input to the second operational amplifier, the output of the second operational amplifier being coupled to the input of the first operational amplifier. As illustratively shown in Fig. 4, a resistive network comprising resistors 41 2a through 41 2n and resistors 414a through 414n is shown coupled between output terminal 398 and an input to differential amplifier 402. Specifically, resistors 41 2a through 41 2n are seriesconnected between bias V' and output terminal 398 while first ends of resistors 414a through 41 4n are coupled to the respective ends of resistors 41 2a through 41 2n closest to output terminal 398.The second ends of resistors 414a through 414n are coupled respectively through switches 41 6a through 41 6n to the negative input of amplifier 402.

An additional resistor 418 provides a feedback from the negative input terminal of amplifier 402 to the output of amplifier 402. The output of amplifier 402 is coupled through resistor 420 to the negative input of amplifier 400.

In accordance with the present invention, the variable amplifier means preferably further comprises a third resistive network coupled between the reference source and an input to the third operational amplifier, the output of the third operational amplifier being coupled to the input of the first operational amplifier.

As illustrated in Fig. 4, again by way of example and not limitation, resistors 422a through 422n are respectively series-coupled to switches 424a through 424n and the resultant series combinations are connected in parallel between bias V which serves as a reference source and a positive input of amplifier 404. Bias V is connected to the negative input of amplifier 404 by resistor 426. A feedback resistor 428 is coupled between the negative input of amplifier 404 and the out put of amplifier 404. The output of amplifier 404 is coupled by resistor 430 to the input of amplifier 400.

In accordance with the present invention the variable amplifier means preferably further comprises means for varying the resistive net works as indicated by operational information stored in a memory means. As illustratively shown in Fig. 4, switches 410a through 410n, 416a through 416n and 424a through 424n comprise mechanisms whereby the re resistive networks of MDACs 318, 320 and 322 of Fig. 3c are selectively varied by digital information which may, for example, be stored in memory unit 304 of Fig. 2, with particular digital signals representing opera tional information governing the selective clos ing and opening of these switches.As will be apparent to those skilled in the art, the more resistors and switches employed in each parti cular MDAC, the more precise the scale factoring and offset compensation which can be achieved by the variable amplifier of Fig. 4.

In summary if the input signal is to be amplified, MDAC 322 should have all or as many as possible switches 41 0a through 410n closed and gain is achieved by closing an appropriate number of switches 41 6a through 41 6n associated with gain or feed back attenuation MDAC 318. If the input signal is to be attenuated, switches 41 6a through 41 6n associated with gain MDAC 318 are set to produce unity gain from MDAC 318 and the attenuation function is controlled by the setting of switches 410a through 410n of attenuation MDAC 322.Offset MDAC is controlled by the setting of switches 424a through 424n to generate either a positive or negative output voltage of required amplitude such that, when converted to a current by resistor 430, the injected current through re sistor 430 is sufficient to cancel the effects of any offset currents induced by an asymmetri cal input signal to amplifier 400 of attenua tion MDAC 322. In the case of a symmetrical input signal, centered around zero, the output of offset MDAC 320 is programmed to pro duce a zero current through resistor 430.

Memory unit 304 of Fig. 2 provides means for storing operation information for variable amplifier 302. Memory unit 304 is preferably a programmable read only memory either er asable or non-erasable, although unit 304 may comprise other forms of memory storage such as a random access memory.

Logic network 312 of Fig. 2 may simply comprise a counter which selectively energizes address locations in memory unit 304 inter laced with sequential energization of switching mechanism 310 so that proper attenuation offset and gain operational information is sup plied to amplifier 302 from memory unit 304 when each input signal is connected to ampli fier 302 by switching mechanism 310. Logic network 312 may, however, include program mable memory means which selectively alters and varies the order by which switchanism 310 couples input signals to amplifier 302 as will be explained in more detail in connection with Fig. 8. Again, for each input signal coupled to amplifier 302, logic network 312 assures that the proper address of memory 304 is energized.

Returning to Fig. 2, with amplifier 302 comprising, for example, the variable amplifier illustrated in Fig. 4, attenuation, offset, and gain information for memory unit 304 to amplifier 302 comprises digital information directed to control the operation of switches 410a through 410n, 424a through 424n, and 41 6a through 416n, respectively. The output of amplifier 302 is coupled to transmitter 306 for pulse amplitude modulation transmission from antenna 308 as is well-known to those skilled in the art.

In operation of the commutating signal conditioner illustrated in Fig. 2, an array of operational information and order information is stored in address locations of memory unit 304. Thus, logic unit 31 2 provides means for adjusting the settings of variable or programmable amplifier 302 as indicated by the stored operational information in memory unit 304 for each input signal 1-128 coupled to amplifier 302 through operation of switching mechanism 310 which is also controlled by logic network 312.More specifically, when, for example, logic network 312 closes the first position of switching mechanism 310 such that input signal 1 is passed to amplifier 302, logic network 31 2 also accesses addresses of memory unit 304 which provide digital operational information to control the attenuation of amplifier 302, the offset of amplifier 302, and the gain of amplifier 302 by, for example, setting switches 41 4a through 414n, 424a through 424n and 416a through 416n, of Fig. 4, respectively, to selected positions.

In the same manner, for whatever input signal logic network 312 determines is to be connected to amplifier 302, logic network 312 also assures that amplifier 302 is first adjusted to the proper setting of that input signal.

Thus gain MDAC 318 and attenuation MDAC 322 are controlled by operational information stored in memory unit 304 to achieve an output set to the required limits of transmitter 306. For example, gain MDAC 318 and attenuation MDAC 322 may be selectively controlled by information stored in memory unit 304 to assure that the output swing for each input signal 1-128 is no greater than 5 volts peak-to-leak whether centered about zero or not.

Furthermore, if the input signals 1-128 are not symmetrical with respect to zero, offset MDAC 320 is controlled by information stored in memory unit 304 to generate either a positive or negative output voltage of required amplitude such that an output current from offset MDAC 320 injected into the negative input of amplifier 216 is of sufficient amplitude to cancel the effects of an offset current induced by an asymmetrical input signal through attenuation MDAC 322. Of course, in the case of a symmetrical input signal, centered about zero, the output of offset MDAC 320 may be programmed to produce a zero current.

In a series of sequential operations, logic unit 31 2 configures programmable amplifier 302 for proper attenuation, offset and gain for each of the 1 28 input signals provided to commutator 300. In this manner, reliable signal conditioning is established with reduced component count, reduced volume, reduced weight and expense but with increased reliability and extreme flexibility over conventional systems with separate signal conditioning and commutating functions. It should be further understood that while three MDACs are shown employed in the illustrative example of a variable amplifier illustrated in Fig. 4, the requirements of a particular set of input signals might only necessitate the employment of one or two of the MDACs illustrated in Fig. 4.

It should also be clearly understood that the present invention is not to be limited to the employment of MDACs per se since MDACs are merely illustratively shown as components which may be employed to provide one suitable example of a variable amplifier for use in connection with the subject invention.

As will be apparent to those skilled in the art, amplifier 302 must be given time to establish proper operating conditions before input signals are allowed by switching mechanism 310 to be communicated to amplifier 302. A potentially more efficient example of the present invention which expressly deals with the problem of setting a variable amplifier prior to receipt of an input signal is illustrated in Fig. 5 wherein the input signals are divisible into first and second groups, namely even channel group 500 and odd channel group 502 which groups are associated with first and second programmable or variable amplifiers 504 and 506, respectively.

In accordance with the present invention, a commutating signal conditioner including first and second variable amplifiers further comprises commutator means for selectively coupling the input signals to the first and second variable amplifiers. As illustratively shown in Fig. 5, commutator 508 operates to communicate even channel input signals 500 to the amplifier 504 and commutator 510 operates to communicate odd channel input signals 502 to amplifier 506.

The embodiment of the commutating signal conditioner illustrated in Fig. 5 also includes a memory unit 512 which provides means for storing operational information for amplifiers 504 and 506.

In accordance with the present invention, logic means are provided for setting the first and second variable amplifiers as indicated by the operational information for each input signal coupled to the respective amplifiers, the logic means setting one of the amplifiers while the other of the amplifiers operates on an input signal. As illustratively shown in Fig. 5, logic network 514 addresses memory unit 512 to set amplifiers 504 and 506 as indicated by operational information stored in memory unit 51 2 for each input signal from even group 500 and odd group 502 coupled to the respective amplifiers 504 and 506.

Logic network 51 4 operates, as will be explained below, to set one of amplifiers 504 to the appropriate amplitude and offset compensation while the other of the amplifiers operates on an input signal. The outputs from amplifiers 504 and 506 are combined in combiner 516 to provide a unified pulse amplitude modulation signal suitable for transmission.

A specific example of the embodiment of the subject invention incorporating two variable amplifiers is illustrated in Fig. 6. In Fig.

6, a first variable amplifier is illustrated as comprising MDACs 600, 602, 604, and inverter 606. A second variable amplifier is illustrated as comprising MDACs 608, 610, 612, and inverter or operational amplifier 614. MDAC 600 receives odd signals and is coupled at its output to the input of inverter or operational amplifier 606. MDAC 602 provides an output current to the input of inverter 606 while MDAC 604 provides feedback attenuation control for inverter 606. In a similar manner MDAC 608 receives even signals and couples them to the input of inverter 614.

MDAC 610 provides an offsetting current to the input of inverter 614 and MDAC 612 provides feedback or attenuation control to inverter 614.

The settings of MDACs 600 and 608 are governed by memory unit 616, the settings of MDACs 602 and 610 are governed by memory unit 618, and the settings of MDACs 604 and 61 2 are governed by operational information stored in memory unit 620. Odd channel signals are coupled from the output of inverter 606 to output terminal 622 by FET 624 with the conduction of FET 624 governed by odd logic control signal Qo. The even channel signals are supplied from inverter 614 to output terminal 622 through FET 626 and the conduction of FET 626 is governed by even logic control signal Q.

The commutating signal conditioner includes commutator means for selectively coupling the input signals in the even and odd groups to the first and second variable amplifiers. As shown in Fig. 6, a commutator may, for example, comprise digital multiplexers 628, 630, 632, 634, 636, 638, 640, and 642 which are coupled to receive input signals as illustrated in Fig. 6. Multiplexers 628, 634, 636 and 642 are shown as receiving single ended input signals while multiplexer 632, 634, 638 and 640 are shown as receiving differential signal which are coupled into single signals by differential amplifier 660.

Each of the digital multiplexers is illustratively shown to receive eight different input signals and select one of the eight input signals through a combination of Q control signals which comprise Q control signals Q100,Q10,Q11, and Q12 for digital multiplexer 628, Q101, Q10, Q11, and Q12 for digital multiplexer 630; 0101, Q1 0, 011, and Q12 for digital multiplexer 632; Q107, Q10, Q11, and Q12 for multiplexer 634; Q100,Q10,Q11, and Q12, for digital multiplexer 636; Q106, Q10, Q11, and 012 for digital multiplexer 638; 0106, 010, 011, and Q12 for digital multiplexer 640; and Q107, 010, Q11, and Q12 for digital multiplexer 642.As will be explained below, control signals Q10, Q11, Q12, and Q100-Q107 are provided by a logic circuit to allow digital multiplexers 528 through 542 to pass particular ones of the input signals in an orderly fashion to the first and second variable amplifiers.

The commutator further comprises buffers 650 for the output of each digital multiplexer.

Digital multiplexers 628, 634, 636, and 642 are illustratively shown as receiving single ended input signals which are merely passed through the multiplexers and buffers 650.

However, for illustrative purposes multiplexers 630, 632, 638 and 640 are shown capable of receiving differential ended input signals with the first half of the odd differential input signals 17 through 31 being received by multiplexer 630 and the second half of odd differential input signals 17' through 31' being received by multiplexer 632. The first half of even input signals 50 through 64 is shown received by multiplexer 638 while the second half of differential input signals 50' through 64' is received by multiplexer 640. The outputs of multiplexer 630 and 632 and the outputs of multiplexers 638 and 640 are coupled through buffers 650 to differential circuits comprising resistors 652, 654, 656, and 658, and operational amplifiers 660. The junction of resistors 652 and 654, in each case, is coupled to one input of an operational amplifier 660 while the junction of resistors 656 and 658 provides an input for the second input to each operational amplifier 660.

The output of operational amplifiers 660 and the output of buffers 650 for multiplexers other than 630, 632, 638 and 640 are coupled to respective inputs of multiplexers 662 and 664 as illustrated in Fig. 6. Multi plexer 662 is governed by control signals Q1, Q3 and Q5 whereas multiplexer 664 is governed by control signals Q2, Q4 and Q6. The output of multiplexer 662 is coupled to a buffer 666 to provide odd signals to the first variable amplifier while the output of multiplexer 664 is coupled through buffer 668 to provide even signals to the input of the second variable amplifier.

A suitable logic network for the operation of the commutating signal conditioner illustrated in Fig. 6 is shown in Fig. 7 to comprise a 64 khz clock 670, a seven stage counter 672, a first divide by eight unit 674, a second divide by eight unit 676, a one-of-eight decoder 678 and an inverter 680. As will be apparent to one skilled in the art, each count of clock 670 provides an odd control signal Q while inverter 680 provides at its output an even control signal Q, for each positive to negative swing of clock 670.

Q is inputted to divide-by-eight unit 674 to provide outputs Q1, 03, and OS whereas even control signal 0, is provided as an input to divide-by-eight unit 676 to provide control signals Q2, Q4, Q6. Q is also provided as an input to seven stage counter 672 which, in effect, divides by 1 28 to provide a binary count of 128 at outputs Q10 through Q16.

Outputs 010 through Q1 6 are also coupled to the inputs of one-of-eight decoder 678 to provide a sequence of eight unique outputs Q100 through 0107 during each 1 28 counts of clock 670.

The outputs of the logic network illustrated in Fig. 7 are coupled as indicated in Fig. 6.

Namely, Q is coupled to the gate of FET 624; Q, is coupled to the gate of FET 626; Q1, 03 and OS are coupled to the digital control inputs of multiplexer 662; Q2, Q4 and Q6 are coupled to the digital control inputs of multiplexer 664; Q10 through Q16 are coupled to the digital control inputs of memory units 616,618 and 620; while Q10, Q11, Q12 and Q100 through 0107 are coupled to the digital control inputs of multiplexers 628 through 642.

In operation of the commutating signal conditioner illustrated in Fig. 6, operational information is stored in memory units 616, 618 and 620 indicative of the settings of MDACs 600 through 614 which are required to properly compensate each input signal 1 through 1 28 at output 622. The memories of memory units 616, 618 and 620 are sequentially energized by control signals Q10 through Q16 to energize a particular set of addresses in the memory units for each input signal.

Multiplexers 628 through 642, 662 and 664 operate as is weil-known to those skilled in the art to provide first an odd signal at the output of buffer 666 and then an even signal at the output of 668 until each odd input signal of the 1 28 input signals is coupled to the input of MDAC 600 and each of the even input signals is coupled to the input of MDAC 608.

With the logic unit of Fig. 7 coupled as illustrated in Fig. 6, MDACs 600, 602 and 604 pass an odd input signal while MDACs 608, 610 and 612 are being set as indicated by operational information stored in memory units 616, 618 and 620 to proper values for passage of the next even signal. Upon passage of the next even signal, MDACs 600, 602, and 604 are being set as indicated by operational information stored in memory units 616, 618 and 620 to pass the next odd signal received at MDAC 600. The sequential operation of MDACs 600, 602 and 604 and MDACs 608, 610 and 612 continues until all 1 28 signals are coupled to output terminal 622 at which point the operation is repeated as often as required.

Fig. 8 illustrates a memory unit 680 which provides means for storing order information for determining the order of connecting input signals 1-128 to amplifiers 666 and 668 in Fig. 6. Memory unit 680 is positioned between the outputs Q1-Q6, 010-012, and Q100-Q107 in Fig. 7 and the respective inputs for these signals in Fig. 6. Accprdingly, the use of memory 680 in connection with Figs. 6 and 7 illustrates one example of means for stepping the multiplexers of Fig. 6 in synchronism with adjusting the variable amplifiers of Fig. 6 to couple input signals to the amplifiers when the amplifiers are adjusted to properly condition the specific input signals being connected to the amplifiers.

Additional advantages and modifications will readily occur to those skilled in the art.

The invention in its broader aspects is therefore not limited to the specific details, representative operations, and illustrative examples shown and described. Accordingly, departures may be made from such details without departing from the spirit or scope of applicants' generally inventive concept, as claimed herein.

Claims (14)

1. A commutating signal conditioner for a plurality of input signals comprising: a. variable amplifier means; b. memory means for storing operational information for said amplifier means; c. commutator means for selectively coupling the input signals to said amplifier means; and d. circuit means for adjusting said variable amplifier means as indicated by said operational information for each input signal coupled to said amplifier means.

2. The conditioner of claim 1 wherein said variable amplifier means selectively offsets said input signals.

3. The conditioner of claim 1 wherein said variable amplifier means selectively varies the amplitude range of said input signals.

4. The conditioner of claim 1 wherein said variable amplifier means comprises a plurality of digital-to-analog converters.

5. The conditioner of claim 1 wherein said memory means comprises a read only memory.

6. A commutating signal conditioner for a plurality of input signals comprising: a. variable amplifier means; b. memory means for storing operational information for-said amplifier means; c. commutator means for selectively coupling the input signals to said amplifier means; and d. circuit means for adjusting said variable amplifier means as indicated by said operational information for each input signal coupled to said amplifier means, and for stepping said commutator means in synchronism with said adjusting of said variable amplifier means to couple said input signals to said amplifier means when said amplifier means is adjusted to properly condition the specific input signal being coupled to said amplifier means.

7. The conditioner of claim 6 wherein said memory means includes means for storing order information for determining the order of stepping said commutator means.

8. A commutating signal conditioner for a plurality of input signals comprising: a. variable amplifier means; b. memory means for storing operational information for said amplifier means; c. commutator means for selectively coupling the input signals to said amplifier means; d. circuit means for adjusting said variable amplifier means as indicated by said operational information for each input signal coupled to said amplifier means; and wherein said variable amplifier means comprises: i. input and output terminals; ii. a reference source; iii. first, second, and third operational amplifiers; iv. a first resistive network coupled between said input terminal and an input to said first differential amplifier; v. an inverter coupled between the output of said first differential amplifier and said output terminal; vi. a second resistive network coupled between said output terminal and an input to said second operational amplifier, the output of said second operational amplifier being coupled to said input of said first operational amplifier; vii. a third resistive network coupled between said reference source and an input to said third operational amplifier, the output of said third operational amplifier being coupled to said input of said first operational amplifier; and viii. means for varying said resistive networks as indicated by said operational information.

9. A commutating signal conditioner for a plurality of input signals, the conditioner comprising: a. first and second variable amplifiers; b. memory means for storing operational information for said amplifiers; c. commutator means for selectively coupling the input signals to said first and second variable amplifiers; and d. logic means for setting said first and second variable amplifiers as indicated by said operational information for each input signal coupled to said respective amplifiers, said logic means setting one of said amplifiers while the

10. The conditioner of claim 9 wherein said variable amplifiers selectively offsets said input signal.

11. The conditioner of claim 9 wherein said variable amplifiers selectively vary the amplitude range of said input signals.

1 2. The conditioner of claim 9 wherein said variable amplifiers comprise a plurality of digital-to-analog converters.

1 3. The conditioner of claim 9 wherein said memory means comprises at least one read only memory.

14. A commutating signal conditioner for a plurality of input signals, the conditioner comprising: a. first and second variable amplifiers; b. memory means for storing operational information for said amplifiers; c. commutator means for selectively coupling the input signals to said first and second variable amplifiers; d. logic means for setting said first and second variable amplifiers as indicated by said operational information for each input signal coupled to said respective amplifiers, said logic means setting one of said amplifiers while the outher of said amplifiers operates on an input signal; and wherein said variable amplifiers each comprises: i. input and output terminals; ii. a reference source; iii. first, second, and third operational amplifiers; iv. a first resistive network coupled between said input terminal and an input to said first operational amplifier; v. an inverter coupled between the output of said first operational amplifier and said output terminal; vi. a second resistive network coupled between said output terminal and an input to said second operational amplifier, the output of said second operational amplifier being coupled to said input of said first operational amplifier; vii. a third resistive network coupled between said reference source and an input to said third operational amplifier, the output of said third operational amplifier being coupled to said input of said first operational amplifier; ; and viii. means for varying said resistive networks responsive to said operational information.

1 5. A commutating signal conditioner substantially as hereinbefore described with reference to Fig. 2 or Figs. 5 and 6, optionally as modified by Fig. 3(c) or Fig. 4.