GB2024570A - Signal conditioning and multiplexing circuit - Google Patents

Abstract

An integrated fully programmable circuit with particular usefulness in the area of telemetry, for programmed multiplexing of multiple data inputs and for signal conditioning, utilises only one amplifier path (50) for conditioning all the channels of the multiplexed multiple data input signal. A programmable counter (41) drives a gate matrix (46) for cyclically commutating the multiple data inputs into connection with the conditioning path, the counter controlling a memory (43) so as concurrently to provide programmed inputs for switching predetermined circuit elements (54, 66) in the conditioning path corresponding to each parameter of each respective data input which is conditioned. <IMAGE>

Description

SPECIFICATION Signai conditioning and multiplexing circuit This invention relates to a conditioning and multiplexing circuit, for example for telemetry and other like systems.

In a great many information processing systems, and in particular telemetry systems such as are utilized for communicating between ground stations and airborne vehicles such as missiles, an important subsystem of the telemetry system is that portion which commutates, or multiplexes, a plurality of data inputs into a single communication channel, as well as conditioning the signals received from the multiple date input sub-channels so that they are of requisite form and condition for transmission.

In such systems, the commutating or multiplexing is suitably time multiplexing, wherein each one of a large number of data inputs is sampled for a given time interval, or channel, such that a given "frame" of the communicated signal constitutes successive sampled signal levels corresponding to each one of the respective data inputs. The multiple data inputs are derived typically from multiple sensors, operating instruments, or measuring devices, and consequently are non-uniform in terms of operating characteristics such as dynamic range, offset, source impedance, and frequency characteristics.

In order that each channel, or data input, should be uniform and be compatible with the rest of the system, i.e., interface with the remaining part of the communication system, each signal is conventionally treated or conditioned in a separate conditioning path. Such conditioning paths conventionally comprise a plurality of active circuits, typically comprising opertional amplifiers, wherein each amplifier stage is designed to condition the signal with respect to a respective difference parameter. These parameters include, e.g., gain: offset; source impedance; and bandwidth.

As is understood by those of skill in the art, such a conditioning path which is designated specifically to condition properly a signal received from a given source will not be able to condition properly a signal received from a different source.

Consequently, where N inputs must be conditioned, there are N conditioning paths.

Where N is of the order of 100, it is seen that the large number of conditioning paths adds considerably to the complexity, unreliability, and expence of the conditioning subsystem.

According to this invention there is provided a signal conditioning and multiplexing circuit for deriving a multiplexed signal from a multiplicity of data inputs, comprising: (a) timing means for providing cyclical timing signals; (b) multiplexing means, driven by said timing signals, for successively gating signals from respective ones of said multiplicity of date inputs for respective predetermined channel intervals, to derive successive channels and thereby produce a multi-channel multiplexed signal; (c) a conditioning path; having an input connected to the output of said multiplexing means and having a plurality of respective programmable conditioning stages; and (d) programming means driven by said timing signals for sussessively and synchronously programming each of said stages in accordance with successive predetermined channel programs, each such channel program lasting for the interval of each respective channel.

The invention will now be described in more detail, by way of example, with reference to the soie figure of the drawing, which is a block circuit diagram of a signal conditioning and multiplexing circuit embodying this invention.

Referring now to the drawing, there is shown a clock circuit 40, which is a conventional clock pulse generator which produces an output signal of any desired prodetermined frequency and interval. As is shown by the discussion of the overall circuit, the frequency of the clock determines the channel width, i.e., the time interval or sample duration of each of the data inputs as it comprises the final multiplexed or commutated output signal. Clock pulses are communicated to a counter 41, which is pre-wired as shown at 49 to be reset to the zero state in accordance with the number of desired channels per frame, i.e., the number of data inputs to be commutated each frame. The counter 41 may be permanently wired for a given number of channels per frame, or it may be adjustable, by being "loose" wired so that its count can be changed for different applications.In other words, a suitable arrangement would be for the counter to have a capacity to count from zero to 99, to accomodate any application where up to 100 channels might be used. If, for a particular application, 50 channels are to be used, the counter is simply wired to be automatically reset upon reaching the count of 49. If at a later time, it is desired to use the same hardware for a 35 channel system, the system can be easily modified by rewiring the counter to reset itself after a count of 34.

In the embodiment illustrated, counter 41 is suitably an 8 bit counter, having 8 outputs corresponding to the 8 different bit positions. In the drawing only 4 outputs are shown, but it is to be understood that there are actually 8 in the preferred embodiment. The output lines from counter 41 are connected both to a program circuit 42, in the form of a programmable readonly memory designated PROM #1, and a programming circuit 43, disignated PROM #2.

PROM +1 and PROM *2 are commercialjy available integrated circuits, which can be programmed as desired to take the inputted binary signals from counter 41 and output stored programmed binary-coded decimal (BCD) words.

The output of PROM#1 is illustrated as two sets of 4 lines each, with 4 bits being inputted to each of two BCD-to-decimal (BCD/DEC) converters 44A and 448 respectively. The two BCD/DEC converters each provide as an output a 1 O-line decimal signal which is connected to a gate circuit 46, converter 44A transmitting a units signal and converter 44B transmitting a tens signal. Circuit 46, designated GATES, receives the multiple data inputs, and switches a particular one of such inputs to an output terminal 48 depending upon the gating signals transmitted from converters 44A and 44B. Also inputted to circuit 46 are frame identification inputs, which are gated through in a conventional manner following sampling of each of the respective different data inputs.Thus, for the circuit illustrated, circuit 46 can provide commutations of up to 100 channels of data, less the number of channels used for frame identification (which is typically 5).

Referring now to the lower part of the figure, the commutated or time multiplexed signal at terminal 48, shown again at the bottom left of the figure, is passed through a conditioning path which is here illustrated as comprising two amplifier stages. It is to be understood that although the appartatus is illustrated with two conditioning amplifier stages, more amplifier stages may be used. The first amplifier stage comprises an operational amplifier 50, having its positive input terminal connected to ground through a resistor 52, and a resistor 51 connected to its negative terminal from the input terminal 48.

The feedback resistance is a selected feedback resistor 54, or combination of a plurality of such resistors in parallel, depending upon the input to a switch 59 which causes the switch to connect a programmed resistance between the output of amplifier 50 and the input. As is well known, the feedback resistance value, in combination with input resistor 51, sets the gain of the amplifier stage.

By switching in the desired effective resistance as the feedback resistance, the gain may be determined. This is done by gating through from PROM#2 a 4-line, or 4-bit signal. Thus, for each respective count of counter 41, which corresponds to a given one of the multiple data inputs, there is concurrently connected a respective binary signal to analog switch 59, which determines the effective feedback resistance and thus the gain of the first amplifier stage. Note that PROM#2 is programmed such that, corresponding to each binary signal it receives from counter 41, it produces a programmed 4-bit output which sets switch 59 to give the gain desired fro the channel that is being concurrently gated through circuit 46 to the conditioning path.

The operation of the second amplifier stage of the conditioning path is in many respects simiiar to that of the first stage. This stage is however illustrated as being designed to condition the amplifier to adjust for offset of the signal, so that the signal that is passed for each succeeding channel is within a predetermined voltage range.

One bit from PROM #2 is connected through to a switch 64, which has a +10 volt input and a -10 volt input. The one-bit input switches either + 1 0 volts or --10 volts through to a resistor grid 66, which comprises a plurality of resistance dividers between switch 64 and ground to provide a plurality of reference voltages. Each resistance divider has an output which is connected into an analog switch 65. Switch 65 receives a 3-line input from PROM*2, such that it receives a 3-bit switching signal which is a function of counter 41 as well as the programming of PROM #2.

Accordingly, for each channel, or respective sample of the data input, a predetermined offset voltage, either plus or minus, and of a particular value, is outputted from switch 65. This signal is connected to the input terminal of an operational amplifier 60 through an amplifier 67 and a resistor 68. The gain of amplifier 60 is set by a feedback resistor 63 and an input resistor 61, the latter being connected between the negative input terminal of amplifier 60 and the output of amplifier 50. The positive terminal of amplifier 60 is connected thrdugh a resistor 62 to ground. The resistance divider network can of course be controlled by PROM#2 in other ways.

As stated previously, any number of additional amplifier stages may be utilized, each designed to condition the commutated signal with respect to a given characteristic of that signal, and each being switchably programmed by a PROM to condition each channel in a desired manner.

The PROM units 42 and 43, as well as any other such units which are used, are commercially available circuits which can be pre-programmed as desired to give any desired translation of the binary output from counter 41 into binary coded decimal. For example, suppose the circuit shown in the drawing has been used for commutating and conditioning 46 data channels connected to 46 particular channel inputs. For such use, the two PROMs are programmed in a specific co-ordinated manner. However, if the device is to be used for a different number of channels, or if the same signal sources are wired through to different input terminals of the qate circuit 46, then the PROMs can be pre-programmed as necessary.

The circuit illustrated can in principle accommodate any number of data inputs, and carry out any number of conditioning steps. For whatever application, the gating of a specific channel is time co-ordinated with the programming of the conditioning stages. Thus, for the time interval that PROM +1 gates through a given channel, PROM #2 (and any additional PROMs as desired) sends appropriate control switches to the analog switches to set the conditioning stages as desired for that particular channel. Note also that it is not required that each channel need to be conditioned in each stage.

Thus if a given channel needs no offset adjustment, switch 65 feeds through a zero signal; if no gain is necessary, switch 59 switches in a feedback resistance equal to resistor 51, to provide unity gain.

Thus it is seen that the integrated system described has a multiplexing or commutation portion and a signal conditioning portion, the multiplexing portion providing a multiplexed output which is connected to the conditioning portion, the conditioning portion comprising a single multiple-stage amplifier path, the multiplexing and conditioning portions being synchronously programmed by clock pulses from a single clock source. The multiplexing portion is adaptable to bb programmed for handling any predetermined number of data inputs, which data inputs can be encoded in any conventional fashion, though pulse amplitude modulation is particularly suitable.

Accordingly, there is provided a universally adaptable integrated commutating and conditioning circuit, which is flexible in being programmable with respect to different system inputs, and which provides a significant saving in the space and expense required for the conditioning path.

Claims (9)

1. A signal conditioning and multiplexing circuit for deriving a multiplexed signal from a multiplicity of data inputs, comprising: (a) timing means for providing cyclical timing signals; (b) multiplexing means, driven by said timing signals, for successively gating signals from respective ones of said multiplicity of date inputs for respective predetermined channel intervals, to derive successive channels and thereby produce a multi-channel multiplexed signal; (c) a conditioning path, having an input connected to the output of said multiplexing means and having at least one programmable conditioning stages; and (d) programming means driven by said timing signals for sussessively and synchronously programming the said stage or stages in accordance with successive predetermined channel programs, each such channel program lasting for the interval of each respective channel.

2. A circuit according to claim 1, wherein the timing means comprises a clock generator in combination with a counter, the counter being adjustable to define the number of channels per frame of the multiplexed signal.

3. A circuit according to claim 1 or 2, wherein the or one of the conditioning stages comprises a switchable resistance network, and the programming means is connected to control the resistance network, whereby the said stage is controlled to provide a switchable gain function in accordance with the programs.

4. A circuit according to claim 1, 2 or 3, wherein the or one of the stages comprises a switchable voltage reference in combination with a switchable resistance divider network, and the programming means is connected to control the divider network, whereby the said stage is controlled to provide a switchable offset signal in accordance with the programs.

5. A circuit according to any preceding claim, wherein the multiplexing means privides for each of said successive channels a pulse amplitude modulated signal representing respective ones of the multiple data inputs.

6. A circuit according to any preceding claim, wherein the or each stage comprises an operational amplifier in combination with a switchable circuit having a plurality of circuit configurations providing a corresponding plurality of circuit characteristics, and the programming means is connected to control the switchable circuit, whereby the stage is controlled to provide switchable characteristics in accordance with the programs.

7. A circuit according to any preceding claim, wherein the programming means causes the switching of the or each stage to take place in time concurrence with the channel intervals.

8. A circuit according to claim 6, wherein the programming means provides that the switching of the or each stage is synchronized with the gating of the multiplexing means.

9. A circuit according to claim 8, wherein the programming means comprises at least one programmable circuit for receiving the timing signals and providing converted digital signals to the or each switchable circuit.

10 A conditioning and multiplexing circuit substantially as herein described with reference to the drawing.