GB2040128A

GB2040128A - Improvements in and relating to signal processing circuits

Info

Publication number: GB2040128A
Application number: GB7942702A
Authority: GB
Original assignee: RACAL Ltd
Current assignee: RACAL Ltd
Priority date: 1978-12-11
Filing date: 1979-12-11
Publication date: 1980-08-20
Also published as: GB2040128B

Abstract

Circuits are described for distinguishing between coherent and incoherent energy (e.g. between a signal and noise). One such circuit includes two phase-locked loops (26A, 26B) which are fed in parallel from an input signal F1 at 10 e.g. the IF signal of a superheterodyne receiver. The outputs of the VCO's (30A and 30B) in the loops are fed to a further phase comparator (37) which produces an output only when the input F1 contains coherent energy which enables the loops to lock their VCO's. A threshold level sensor (50) detects the d.c. output from the final phase comparator (37). For an input signal with a poor signal to noise ratio the phase lock loops are subject to 'statistical' lock and the circuit output at 51 varies between a maximum value and a minimum value in dependence on the signal to noise ratio. Loop operation is enhanced by down converting the input signal. The phase locked loops may be replaced by suitable coherent detector circuits. <IMAGE>

Description

SPECIFICATION Improvements in and relating to electrical circuit arrangements The invention relates to electrical circuit arrangements. In a more specific sense, the invention relates to electrical circuit arrangements for substantially distinguishing coherent and incoherent energy; the circuit arrangements can thus be used to distinguish between a signal and a noise.

According to the invention, there is provided an electrical circuit arrangement comprising two channels connected in parallel to receive an input, each channel including detecting means operative to produce a respective output which substantially follows coherent energy in the input but substantially does not follow incoherent energy therein, and output means responsive to the two said outputs whereby to detect when a predetermined phase relationship exists between them.

According to the invention, there is also provided an electrical circuit arrangement for distinguishing between coherent and incoherent energy in an input, comprising two channels in the form of respective phase-locked loops each including an adjustable oscillator and each connected to receive the said input and operative to adjust the oscillator to tend to follow the coherent energy in the input but not the incoherent energy therein, and output means comprising phase comparing means connected to receive the outputs of the oscillators and to compare their phases whereby to produce a unidirectional signal of at least a predetermined magnitude in the presence of coherent energy in the said input.

According to the invention, there is further provided an electrical circuit arrangement for detecting coherent energy in an input, comprising two channels connected in parallel to be energised from the input, each channel including detecting means operative to produce a respective output which sugstantially follows coherent energy in the input but substantially does not follow incoherent energy therein, and output means for comparing the phases of the two said outputs whereby to detect when a predetermined phase relationship exists between them, the two channels operating at respectively dif ferent frequencies.

Electrical circuit arrangements embodying the invention will now be described, by way of example only, with reference to the accompanying drawings in which: Figure 1 is a block diagram of one of the circuit arrangements; Figure 2 is a block diagram of a modified form of the circuit arrangement of Figure 1; Figure 3 is a block circuit diagram of another of the circuit arrangements; and Figure 4 is a block circuit diagram of a further one of the circuit arrangements.

The circuit arrangement shown in Fig. 1 is for producing an output indicating when a coherent signal exists on an input line 10. If only an incoherent signal, such as noise, exists on the line 10, the circuit arrangement does not produce the output.

In one specific example, the signal F1 on the line 10 may be the IF signal of a superheterodyne radio receiver.

As shown, line 10 is connected to two parallel channels 26A and 26B (e.g. through respective buffers). Each channel comprises a respective voltage controller oscillator 30A, 308, each of which feeds one input of a respective phase comparator 28A, 28B through a respective low pass filter 34A, 34B. The other input of each phase comparator receives the signal on the line 10.

Each phase comparator compares the phases of its two inputs and produces a control signal whose magnitude is dependent on the phase difference between the two inputs. This control signal is fed on a respective line 35A, 358 to the control input of the associated VCO 30A, 30B and adjusts the frequency of the VCO in such a direction as to bring the phases of the two signals applied to the inputs of the phase comparator into phase equality. Each channel 26A, 26B therefore comprises a respective phase-locked loop.

The output of the two VCO's are also fed on respective lines 36A, 36B to respective inputs of a third phase comparator 37 which therefore compares the phases of the outputs of the two VCO's and produces an output on a line 38 dependent on the relative phases of the VCO outputs.

In one specific example, where line 10 is connected to monitor the IF signal of a superheterodyne receiver having an IF of 21.4 MHz, each VCO has a nominal frequency close to 21.4 MHz.

In operation, when the input on line 10 is wholly incoherent, that is, restricted to noise, then no steady state phase relationship exists between the frequencies to which the two VCO's 20A and 20B are respectively controlled by their phase-locked loops; the phase-locked loops cannot control their VCO's so as to follow the random variations in the noise input.

Therefore, there is no steady state output from the phase comparator 37 on the line 38.

However, if a coherent signal is applied on line 10 (whether with or without noise, but normally in combination with noise), then each phase-locked loop pulls its respective VCO into phase with the signal. The phase comparator 37 therefore now begins to detect a steady state phase relationship between its two inputs and starts to produce a unidirectional output on line 38. The amplitude of this output is dependent upon the signal to noise ratio on line 10 and this is compared with a pre-set threshold, received on a line 39, in a d.c. comparator 50. The comparator 50 produces an output on a line 51 when the unidirectional input on line 30 is indicative of at least a predetermined signal to noise ratio on the input lines 10.

The circuit arrangement is therefore capable of operating and detecting a signal when the signal to noise ratio is poor.

The drawings originally filed were informal and the print here reproduced is taken from a later filed formal copy.

Figure 2 shows another circuit arrangement in which parts corresponding to those in Figure 1 are similarly referenced. As shown in Fig. 2, the input signal F1 on the line 10 is converted down in a mixer 14, to, say, 100 kHz, by being mixed with the output (at a suitablefrequency) of an oscillator 16. The lower sideband output of the mixer 11 is then selected by a filter 17 and fed to both phase-locked loops 26A and 26B. As before, the phase comparator 37 compares the phases of the outputs of the VCO's 30A and 30B and thus produces a d.c. level when both loops have locked on to coherent energy in the input signal. As before, the loops cannot lock on to incoherent energy and will therefore not produce a significant d.c. output in response to incoherent energy.

It is found that the down-conversion of the input signal produced by the mixer 11 is advantageous because the resultant lower operating frequency of the phase-locked loops considerably reduces any tendency for them to interfere with each other even though they are operating at the same frequency.

Down conversion considerably reduces tolerancing problems because the ratio Bandwidth Phase Locked Loop centre fequency can be made very much largerthan if down conversion were not used. For example, a 20 kHz IF bandwidth at 21 mHz requires tolerances of much better than 0.02 x x 100% = 0.1%, 21 which is difficult to achieve. On the other hand 20 kHz bandwidth at a centre frequency of 100 kHz gives 20 x x100% = 20%, 100 which is not at all difficult to achieve. Alternatively for comparable component tolerances, much higher sensitivity may be obtained by down-converting, because a (say) 2% change in DC output level can be much more accurately detected than (say) a 0.05% change.

Figure 3 shows another of the circuit arrangements and parts corresponding to those in Figs. 1 and 2 are similarly referenced.

As shown, the input signal F1 on line 10 is fed to one input of a mixer 14 where it is mixed with the output, F2, from an oscillator 16. The lower sideband output, F1 - F2 = F3, from the mixer 14 is selected and passed to one input of a second mixer 18 whose second input is fed from a second oscillator 20.

F1 may be 21 MHz and F2 may be 20 MHz, so that F3 is 1 MHz. These figures are given purely by way of example.

The second oscillator 20 produces an output F4 (of, say, 300 kHz) via a line 22. The two sideband outputs (F3 + F4) and (F3 - F4) from the mixer 18 are fed on a line 24 to the two phase-locked loops 26A and 26B which are as previously described.

However, the loop 26A is adjusted so that it will lock onto the upper sideband (F3 + F4) but not the lower sideband (F3 - F4), and the loop 268 is adjusted so that it will lock onto the lower sideband (F3 - F4) but not the upper sideband (F3 + F4).

Therefore, when the loops are locked, the VCO 30A is producing an outputfrequency(F3 + F4) which is fed to one input of a third mixer 40, while VCO 30B is producing an output (F3 - F4) which is fed to one input of a fourth mixer 42.

The second inputs of both of the mixers are fed with the signal F4 from the oscillator 20 via a line 44.

When the loops are locked, each of the mixers 40 and 42 therefore produces an output F3. These two outputs are selected and fed into respective inputs of a fifth mixer 36 whose output is passed through a low pass filter 48 and into the d.c. level sensing circuit 50 which supplies the output line 51.

In operation, if F1 applied to the input 10 is a coherent signal (whether with or without noise, but normally in combination with noise), then each phase-locked loop 26A and 26B pulls its respective VCO into phase with the signal as already described.

Therefore, the outputs produced by the mixers 40 and 42 will be at the same frequency. Thus, mixer 46 produces a d.c. output which is compared in the sensor 50 with a pre-set threshold. The sensor 50 therefore produces an output on line 51 when the signalto-noise ratio of the input F1 on the line 10 exceeds a predetermined value.

When the input signal F1 on input 10 is incoherent, or when the signal-to-noise ratio is very low, then no steady state phase relationship exists between the frequencies to which the two VCO's 30A and 308 are respectively controlled by their phase-locked loops cannot control their VCO's so as to follow the random variations in the noise input. Therefore, the mixers 40 and 42 do not produce equal outputs and there is no steady state output from mixer 46.

In the circuit arrangement of Figure 4, parts corresponding to those in the other Figures are similarly referenced. As shown in Figure 4, the second oscillator 20 feeds the mixer 18 through a divide-by-2 divider 60, the output of the divider being termed F4 and its input is therefore 2F4.

The outputs of the two VCO's 30A and 30B of the phase-locked loops are fed into respective inputs of a mixer 62 which therefore produces an output 2F4, and this is mixed with the signal 2F4 produced by the oscillator 20 in a mixer 64. The mixer output is fed through the low pass filters 48 to the d.c. level sensor 50 and thence to the output line 51.

In operation, when the input signal F1 on line 10 is coherent, or contains a coherent signal, then each phase-locked loop locks up, with VCO 30A locking to (F3 + F4), and VCO 308 locking to (F3 - F4) as in the case of the other circuits. Under these circumstances, the mixer 64 produces a d.c. output which is compared in the sensor 50 with the pre-set threshold to produce an output on line 51 when the signal-tonoise ratio of F1 exceeds a predetermined low value.

When the signal F1 on the line 10 is incoherent, or when the signal-to-noise ratio is very low then, as in the other circuits described, the phase-locked loops cannot control their VCO's so as to follow the random variations in the noise input, and the mixer 65 can therefore not produce a sufficiently high d.c.

output to activate the sensor 50.

The circuits of Figs. 3 and 4 have the advantage that, in each case, the two phase-locked loops 26A and 26B work at different frequencies. Therefore, even though the loops are operating in close physical proximity to each other, the risk that might exist if they were operating at the same frequency that they would sometimes lock on to each other instead of to the input signal is removed. The need for providing a high degree of isolation and screening between the two phase-locked loops is therefore removed.

The circuit arrangement of Figure 4 is slightly more economical of components than the circuit arrangement of Figure 3 and has the advantage that no one part of the circuit is working at the same frequency as any other part.

In the circuit arrangements of Figures 3 and 4, the mixer 14 and the oscillator 16 are provided to convert down the input frequency so that the following circuitry is operating at a fairly low frequency; therefore, non-critical circuitry and lay-out may be used and tolerancing problems in the VCO circuitry are avoided. However, the mixer 14 and the oscillator 16 are not essential.

Considering the operation of the circuit arrangements in more detail, the IF input F1 can be regarded not as a frequency spectrum but as a carrier phasemodulated by the noise. This is an important distinction, because the concept of lock in a phase-locked loop working in the presence of large amounts of noise becomes indistinct; lock can only be defined in statistical terms.A phase-locked loop with a sinusoidal phase detector cannot maintain lock if the difference between its input and the VCO output becomes greater than 900. Hence lock may be defined in terms of the proportion of the time the phase difference between the input and the VCO output (i.e. the phase error) is less than 900. Generally, the phase-locked loop will not be thrown completely out of lock by a 900 phase error; within a few cycles of the VCO output frequency, the loop control voltage will be in the right sense to bring the loop back into lock, or alternatively the phase of the input will sweep within 900 (or 900 + 3600 or 900 + 7200 etc.) of the phase of the VCO, causing the loop rapidly to re-acquire lock.

In the circuits shown, the loop bandwidths are made to be slightly wider than the IF bandwidth, so that the loops are just fast enough to remain in lock nearly all the time. The poorerthe signal to noise the greater will be the phase error between the phase of the input and the phase of the VCO output, and the greater will be the difference in phase between the outputs of the two VCO's. Because the input is predominantly noise, the phase errors will also have most of the properties of noise. The difference in phase between the outputs of the two VCO's will reduce the resultant DC output. This is because the output power must be a constant because its inputs (the VCO outputs) are rectangular. Hence the noise power must subtract from this constant power, the difference being the power from the DC term. Hence the DC output voltage must be reduced by noise.

This imperfect tracking of the noise phase jitter is of fundamental importance. If the two phase-locked loops tracked the noise perfectly (as would be the case if their bandwidths were very wide) then their VCO's would be coherent with respect to each other, and hence the resultant output would be a constant maximum DC level irrespective of the signal to noise ratio. In practice, the resultant output must be a maximum when there is a large noise-free input, and a minimum when the input consists only of noise.

Hence in effect, the two phase-locked loops decorrelate the input noise. The DC output can never be zero; the loops must remain in lock most of the time otherwise the capture range will become narrower than the IF bandwidth, which would cause unreliable operation (because the phase-locked loops might never 'see' an input signal if it lies outside the loop bandwidth).

The imperfect tracking by the phase-locked loops is achieved primarily by two effects. The first is overshoot in the loop transient response; the second is non-linearity in the loops, such as caused by phase detector limiting, slew rate limiting of current to the loop filter, and the fact that the phase detector output is proportional to the cosine of the phase difference at its inputs. Effectively, the two loops of each mis-track slightly differently. It is this difference between the phases of the two VCO outputs that reduces the DC output. Because of small differences in gain, distortion, loop filter response etc., the two loops will initially respond to a phase change at their inputs slightly differently, thus producing different error voltages at the phase detector output which will again cause slightly different responses to the next change of phase, and so on.The poorer the signal to noise, the larger will be the error phase noise, which will worsen the tracking by the loops.

The DC output will therefore be less than if the input signal were large and noise-free; in the latter case the two loops would be strongly locked to the input signal giving a minimum phase-error noise output between the two VCO's and thus giving a maximum resultant output.

Down converting of the input frequency can be regarded as artificially increasing noise phase jitter while not altering the signal.

Each circuit arrangement is capable of operating and detecting a signal when the signal-to-noise ratio is poor. It is largely independent of the input noise level. Furthermore, it can be operated on an unmodulated carrier or on a communication channel of any modulation type containing a phase-coherent carrier. The circuit arrangements maintain their sensitivity to correct operation in the presence of high level man-made impulsive interference.

The circuit arrangements can be modified by replacing the phase-locked loops by other detectors capable of distinguishing between coherent and incoherent energy and relatively insensitive to the absolute level of signal amplitude.

CLAIMS 1. An electrical circuit arrangement comprising two channels connected in parallel to receive an input, each channel including detecting means operative to produce a respective output which substantially follows coherent energy in the input but substantially does not follow incoherent energy therein, and output means responsive to the two said outputs whereby to detect when a predeter mined phase relationship exists between them.

2. A circuit arrangement according to claim 1, in which the output means comprises a phase com parator, whereby to produce a unidirectional signal having at least a predetermined magnitude when the said predetermined phase relationship exists.

3. A circuit arrangement according to claim 1, in which the output means includes mixing means whereby to produce a unidirectional output having at least a predetermined magnitude when the predetermined phase relationship exists.

4. A circuit arrangement according to any preceding claim, in which each detecting means comprises a respective adjustable oscillator, and means for adjusting the oscillator to follow the said coherent energy.

5. A circuit arrangement according to any one of claims 1 to 3, in which each detecting means comprises a respective phase-lock loop including a respective controllable oscillator and a respective phase comparator connected to compare the phases of the output of the respective oscillator and the said input and to produce a control signal dependent on the phase difference between them which is connected to adjust the frequency of the oscillator in a direction tending to reduce the said phase difference to zero.

6. A circuit arrangement according to claim 5, in which the two phase-lock loops are arranged to operate at different frequencies.

7. A circuit arrangement according to claim 6, including frequency changing means responsive to the input to produce two intermediate signals each dependent on the input but which differ from each other by a predetermined frequency, one phase-lock loop being adapted to be responsive to one intermediate signal and the other phase-lock loop being adapted to be responsive to the other intermediate signal.

8. An electrical circuit arrangement for distinguishing between coherent and incoherent energy in an input, comprising two channels in the form of respective phase-locked loops each including an adjustable oscillator and each connected to receive the said input and operative to adjust the oscillator to tend to follow the coherent energy in the input but not the incoherent energy therein, and output means comprising phase comparing means connected to receive the outputs of the oscillators and to compare their phases whereby to produce a unidirectional signal of at least a predetermined magnitude in the presence of coherent energy in the said input.

9. An electrical circuit arrangement for detecting coherent energy in an input, comprising two channels connected in parallel to be energised from the input, each channel including detecting means operative to produce a respective output which sub stantially follows coherent energy in the input but substantially does not follow incoherent energy therein, and output means for comparing the phases of the two said outputs whereby to detect when a predetermined phase relationship exists between them, the two channels operating at respectively dif ferent frequencies.

10. A circuit arrangement according to claim 9, in which the input is fed to the two channels through a common mixer where it is mixed with a predeter mined reference frequency, and the two channels are respectively arranged to be energised by the upper and lower sidebands of the output of the mixer.

11. A circuit arrangement according to claim 9 or 10, in which the channels comprise respective phase-lock loops each incorporating a respective adjustable oscillator which is automatically adjusted whereby to tend to follow coherent energy in the input signal but not the incoherent energy therein, and the output means comprises means for compar ing the phases of the two oscillators.

12. A circuit arrangement according to claim 11 in which the output means comprises means for separately mixing the output of each of the oscillators of the phase-lock loops with the reference frequency so as to produce two outputs which when mixed in a further mixer produce a unidirectional signal of at least a predetermined magnitude in the presence of coherent energy in the input signal but not in response to incoherent energy therein, and means for detecting this unidirectional signal.

13. A circuit arrangement according to claim 11, in which the output means comprises means for mixing the outputs of the two oscillators of the phase-lock loops together to produce an upper sideband frequency at twice the value of the refer ence frequency, means for mixing this upper sideband frequency with a frequency derived from an equal to twice the reference frequency whereby to produce a unidirectional signal of at least a predetermined magnitude in response to the presence of coherent energy in the input signal but not in response to the presence of incoherent energy therein, and means for detecting this unidirectional signal.

14. A circuit arrangement according to any preceding claim, including frequency reducing means connected to receive the input and upstream of the two channels.

15. A circuit arrangement according to claim 14, in which the frequency reducing means comprises a mixer for mixing the input with a predetermined frequency and means for selecting the resultant lower sideband.

16. A circuit arrangement according to any one of claims 2,3,8, 12 and 13, in which the output means includes amplitude comparing means connected to compare the level of the unidirectional signal with a predetermined reference level whereby to detect when the coherent energy in the said input has at least a predetermined level in relation to incoherent energy.

17. An electrical circuit arrangement substantially as described with reference to Figure 1 of the accompanying drawings.

18. An electrical circuit arrangement substantially as described with reference to Figure 2 of the accompanying drawings.

19. An electrical circuit arrangement substantially as described with reference to Figure 3 of the

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Claims

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therein, and output means responsive to the two said outputs whereby to detect when a predeter mined phase relationship exists between them.
2. A circuit arrangement according to claim 1, in which the output means comprises a phase com parator, whereby to produce a unidirectional signal having at least a predetermined magnitude when the said predetermined phase relationship exists.
3. A circuit arrangement according to claim 1, in which the output means includes mixing means whereby to produce a unidirectional output having at least a predetermined magnitude when the predetermined phase relationship exists.
4. A circuit arrangement according to any preceding claim, in which each detecting means comprises a respective adjustable oscillator, and means for adjusting the oscillator to follow the said coherent energy.
5. A circuit arrangement according to any one of claims 1 to 3, in which each detecting means comprises a respective phase-lock loop including a respective controllable oscillator and a respective phase comparator connected to compare the phases of the output of the respective oscillator and the said input and to produce a control signal dependent on the phase difference between them which is connected to adjust the frequency of the oscillator in a direction tending to reduce the said phase difference to zero.
6. A circuit arrangement according to claim 5, in which the two phase-lock loops are arranged to operate at different frequencies.
7. A circuit arrangement according to claim 6, including frequency changing means responsive to the input to produce two intermediate signals each dependent on the input but which differ from each other by a predetermined frequency, one phase-lock loop being adapted to be responsive to one intermediate signal and the other phase-lock loop being adapted to be responsive to the other intermediate signal.
8. An electrical circuit arrangement for distinguishing between coherent and incoherent energy in an input, comprising two channels in the form of respective phase-locked loops each including an adjustable oscillator and each connected to receive the said input and operative to adjust the oscillator to tend to follow the coherent energy in the input but not the incoherent energy therein, and output means comprising phase comparing means connected to receive the outputs of the oscillators and to compare their phases whereby to produce a unidirectional signal of at least a predetermined magnitude in the presence of coherent energy in the said input.
9. An electrical circuit arrangement for detecting coherent energy in an input, comprising two channels connected in parallel to be energised from the input, each channel including detecting means operative to produce a respective output which sub stantially follows coherent energy in the input but substantially does not follow incoherent energy therein, and output means for comparing the phases of the two said outputs whereby to detect when a predetermined phase relationship exists between them, the two channels operating at respectively dif ferent frequencies.
10. A circuit arrangement according to claim 9, in which the input is fed to the two channels through a common mixer where it is mixed with a predeter mined reference frequency, and the two channels are respectively arranged to be energised by the upper and lower sidebands of the output of the mixer.
11. A circuit arrangement according to claim 9 or 10, in which the channels comprise respective phase-lock loops each incorporating a respective adjustable oscillator which is automatically adjusted whereby to tend to follow coherent energy in the input signal but not the incoherent energy therein, and the output means comprises means for compar ing the phases of the two oscillators.
12. A circuit arrangement according to claim 11 in which the output means comprises means for separately mixing the output of each of the oscillators of the phase-lock loops with the reference frequency so as to produce two outputs which when mixed in a further mixer produce a unidirectional signal of at least a predetermined magnitude in the presence of coherent energy in the input signal but not in response to incoherent energy therein, and means for detecting this unidirectional signal.
13. A circuit arrangement according to claim 11, in which the output means comprises means for mixing the outputs of the two oscillators of the phase-lock loops together to produce an upper sideband frequency at twice the value of the refer ence frequency, means for mixing this upper sideband frequency with a frequency derived from an equal to twice the reference frequency whereby to produce a unidirectional signal of at least a predetermined magnitude in response to the presence of coherent energy in the input signal but not in response to the presence of incoherent energy therein, and means for detecting this unidirectional signal.
14. A circuit arrangement according to any preceding claim, including frequency reducing means connected to receive the input and upstream of the two channels.
15. A circuit arrangement according to claim 14, in which the frequency reducing means comprises a mixer for mixing the input with a predetermined frequency and means for selecting the resultant lower sideband.
16. A circuit arrangement according to any one of claims 2,3,8, 12 and 13, in which the output means includes amplitude comparing means connected to compare the level of the unidirectional signal with a predetermined reference level whereby to detect when the coherent energy in the said input has at least a predetermined level in relation to incoherent energy.
17. An electrical circuit arrangement substantially as described with reference to Figure 1 of the accompanying drawings.
18. An electrical circuit arrangement substantially as described with reference to Figure 2 of the accompanying drawings.
19. An electrical circuit arrangement substantially as described with reference to Figure 3 of the

accompanying drawings.
20. An electrical circuit arrangement substantially as described with reference to Figure 4 of the accompanying drawings.