GB2038056A - Keyboard circuits - Google Patents

Abstract

A keyboard switch circuit, e.g. for a pocket calculator, has push- button switches e.g. 321 at the crosspoints of row and column conductors. The conductors are connected via electronic switches e.g. 52, 51 to the power supply U and via electronic switches e.g. 42, 41 to inverters e.g. 72,71 having holding inverters in parallel therewith. The row inverters, via NAND 90, control the electronic switches mentioned so that actuation of a push- button switch reverses the electronic switches from the positions shown. CMOS fabrication is advantageous. <IMAGE>

Description

SPECIFICATION Keyboard circuits This invention relates to keyboard circuits for use with electronic equipment.

Electronic equipment is controlled in a great many cases via an input keyboard which consists typically of push-button switches arranged in rows and columns. Such electronic equipment may include, for example, electronic computers, electronic telephone subsets, electronic pocket calculators, or remote control units for e.g. phono equipment, radio or television receivers. The push-button switches, when actuated, establish electrical connections between input leads which may be associated with the aforementioned rows and columns. Thus, in the "IBM Technical Disclosure Bulletin", October 1966, on pages 532/33 there is described a keyboard circuit for data-processing systems in which the information is offered via the just depressed pushbutton switch in a three-out-of-eight code.The pushbutton switches as such, are simple twopole switches acting as operating contacts.

Each pushbutton switch is associated with four decoupling diodes connecting it with four of nine input leads of the data-processing system which, in turn, continuously interrogates the input keyboard with the aid of sampling signals thus detecting a depressed pushbutton switch. Accordingly this is a dynamically operating arrangement.

On page 36 of the technical journal "Electronic Engineering" for September 1976, there is described another data-processing system whose input keyboard cooperates with the integrated circuit of the typc MC 1 441 9 which is described in greater detail on pages 5/201 to 5/204 of the data book published by Motorola "Semiconductor Data Library", Vol. 5, Series B, 1976. From Fig. 4 as shown therein, it is to be seen that the pushbutton switches must be either equipped with double contacts because they, when actuated, apply a supply voltage to the respective column or row lead, or that a pushbutton switch with a single contact may be provided for when being connected to the respective column or row lead via two diodes.It is obvious that such a design or such a wiring of the pushbutton switches is more expensive than the pushbutton switches employing a single contact proposed for use by the aforementioned passage of literature. The aforementioned integrated circuit of the type MC 1 441 9 contains a two-out-of-eight encoder with a subsequently arranged code converter for obtaining a binary-coded decimal (BCD). This circuit likewise operates dynamically, i.e. there is provided a clock oscillator for controlling the code-forming sequence.

From a further data sheet published by Motorola No. E 175, June 1976, it is known to use the integrated circuit of the type MC 14422 P as realized in accordance with the known CMOS-technique, with remote control transmitters, which likewise operates dynamically and, for this purpose contains a sampling oscillator, a sampling control circuit and further additional circuits. In this arrangement it is likewise possible to use single-pole pushbutton switches. Finally, from the technical journal "Electronics", of January 6, 1977, pp. 110 to 11 2 there is known an input keyboard employing simple pushbutton switches in which the respective depressed key is ascertained with the aid of the microprocessor F8, for which the corresponding programme (software) is disclosed in the publication.

Accordingly, the two last-mentioned publications show arrangements solving the keyboard coding problem with an investment which is relatively high with respect to integrated circuits. In particular, the last-mentioned publication including the proposal of using for this purpose a commercially available type of microprocessor, is not realizable in cases where, for example with the aformentioned remote control units, the keyboard coding as well as the remaining remote control transmitter circuit is to be accommodated in one single integrated circuit. In such a case the keyboard coding arrangement must do with as little as possible crystal surface in order to leave enough crystal surface of the integrated circuit for being utilized for the actual functioning of the remote control transmitter.When looked at from this point of view it would appear to be entierly mistaken to provide a microprocessor, because substantial parts thereof would remain unused. But also the aforementioned dynamic technique is too expensive for meeting the given requirement.

According to the invention there is provided a circuit for a keyboard switch arrangement of the type having a plurality of switches each arranged at a respective crosspoint of an n by m array of column and row conductors.

wherein each column and row conductor is coupled via a first electronic switch to the circuit supply voltage and via a second electronic switch to a negative inverter, and wherein the outputs of the inverters associated with the row conductors are coupled to a NAND gate, which NAND gate controls the electronic switches.

The invention will now be described in greater detail with reference to Figs. 1 to 3 of the accompanying drawings, in which: Figure 1 in the form of a schematic circuit diagram shows one example of embodiment of the invention, Figure 2 shows various signal waveforms as appearing in Fig. 1, and Figure 3 shows a partial circuit of the arrangement according to Fig. 1 realized in accordance with the known CMOS-technol ogy.

For the sake of sim city merely tiige col umm1 leads 1 and n as well as the row leads 2 and m are shown of the possible n column leads and the m possible row leads of an m'n keyboard switch matrix arrangement, in the schematic diagram of Fig. 1. The pushbutton switches are arranged at the respective crosspoints of the row and column leads of the matrix, which switches each establish a direct connection when depressed. In Fig. 1, the pushbutton 321 is shown to be arranged at the crosspoint of the column 1 with the row 2, as well as the pushbutton switches 32n, Sml and 3mn.

The column leads 1 ...n and the row leads 2. . m are each applied across a resistor to the zero point (ground) of the circuit; accordingly, Fig. 1 shows the row resistors 61, 6n as well as the column resistors 62, 6m. Each column lead 2... m is applied via the first electronic column switch 41... 4n to the input of the column inverter 71 7n and via the second electronic column switch 51 ... sun to the supply voltage U. In an analogous way, each row lead 2... m is applied via the first row switch 42...4m to the input of the row inverter 72...7m and via the second electronic row switch 52... sum, to the supply voltage U.The hold inverter 81 .8n; 82. . 8m which is dimensioned highly resistive, is respectively arranged in an anti-parallel connection with respect to both the column and the row inver ters 71. . .7n; 72. . .7m.

The outputs of the row inverters 72. . .7m are connected each to one input of the first NAND gate 90 having n inputs, and from the output of which there may be taken a signal which is hereinafter referred to as the actuating signal B. This signal always appears when one of the pushbutton switches is depressed.

Moreover, the output signal of the first NAND gate 90 is applied to one input of the second NAND gate 91, to the other input of which there is applied a rectangular clock signal T.

The output signal F of the second NAND gate 91 is applied to the control inputs of the first row switches 42...4m and of the second column switches 51 ... sun, and is moreover applied to the input of the inverter 92 whose output signal F is applied to the control inputs of the first column switches 41 ...4n and of the second row switches 52... sum.

In Fig. 1 the row and column switches are shown to be in such a position as corresponds to non-depressed pushbutton switches; the signal waveform as shown in Fig. 2 on the left of the vertical arrow, corresponds to this.

Accordingly, the output signal F has an Hlevel, and the output signal F has an L-level.

(The H-level is the more positive one, and the L-level is the more negative one of two binary levels). Thus, all row outputs .2... cm are likewise at H-potential, while all column outputs S1 ... Sn show to have that particular switch state which existed prior to the open- ing of the first column switch 41 . .4n. This state is maintained by the hold inverters 81 .. . sun which are dimensioned highly resistive. When a new binary signal state appears at the output of the associated row or column inverter, the highly resistive hold inverter, however, will not affect the inversion.Accordingly, in the non-operative state of the pushbutton switches, an L-level will exist at the output of the first NAND gate 90 with this Llevel, in connection with the second NAND gate 91, preventing the clock signal T from reaching the output thereof. Accordingly, the signal F as appearing at the output of the second NAND gate 91 assumes an H-state, and the signal F as appearing at the output of the inverter 92 assumes an L-state, and in this way the states of both the first and the second column and row switches are exactly defined.

The aforementioned actuating signal B may be used, for example, for triggering an oscillator generating the clock signal T, so that this oscillator only starts running upon depression of the pushbutton switch. The actuating signal B, however, may also be used for other triggering purposes.

Assuming now that the pushbutton switch 32n is depressed. In that case, via the closed column switch 5n and the closed row switch 42, the supply voltage U will be fed to the input of the row inverter 72, and the output signal Z2 thereof will assume the L-level. In this way the state at the output of the first NAND gate 90 is changed from the L-level to the H-level, so that the clock signal T is transformed into the two two-phase clock signals F, F. All of the switches which are controlled by the signal F (41, 4n, 52, 5m), are closed, and the switches (42, 4m, 51, 5n) which are controlled by the clock signal F, are opened. Via the row switch 52 and the column switch 4n, the supply voltage U is now applied to the column inverter 7n so that the output signal Sn thereof will now assume the L-level. Thereupon, the previously undefined signal at the column output S1 will now assume, across the resistor 61, an H-level.

Any further periods of the clock signal T will not change the states in which the column and row outputs are in, because the column and the row inverters, as already mentioned, always remain in that particular state, via the hold inverters, which existed prior to the closing of the first column switch and of the second row switch.

Instead of the storage section formed of the respective row or column inverter with an antiparallel-connected hold inverter, it is also possible to use other storage cells; they are merely required to have the property of storing the previous state during one-half clock period of the clock signal T. Quite depending on the frequency of this clock signal it might be sufficient, under certain circumstances, to employ a simple type of RC section.

Assuming now that at any arbitary time position, the pushbutton switch 32n is released again. Relative thereto, two states are possible: (a) first row switch 42 open, second row switch 52 closed, first column switch 4n closed, second column switch 5n open: Since the column output Sn assumes an Hlevel and the row output Z2 is likewise at a Hlevel, the end of depressing the pushbutton switch 32n is not recognised, and there is effected a further change in the state of the signals F, F. Via the closed row switch 52, now also the row output signal Z2 will assume the H-state and the first NAND gate 90 will assume the L-level, thus signalling the end of the depression.

(b) row switch 42 closed, two switch 52 open, column switch 4n open, column 5n closed: The row output signal Z2 immediately assumes the H-state and will thus effect that simultaneously the actuating signal B will assume the L-state. In the course of this, the output signal Sn remains at the H-level. When consideraing that the end of actuation will in most cases block all functions, however, this H-state at the column output Sn is of no importance.

When redepressing any one of the pushbutton switches, the column signal Sn will remain at the H-level for the time of the firsthalf clock period of the clock signal T which, under certain circumstances, may lead to a double evaluation of this signal in a subsequently arranged evaluating circuit. Since such types of evaluating circuits, however, are anyway mostly provided with a fault-supervisory circuit which, in the case of many Llevels at the column outputs and in the case of more than one H-level at the column output or in the case of corresponding states at the row outputs, supplies a fault-indicating signal, the unwanted state will be recognised already during the first-half clock period and then eventually not utilized for this particular period of time.In this case the fault criterion of the row outputs may also be used as an actuation identification in accordance with the actuating signal B, so that in this case the first NAND gate 90 may be omitted.

The current flowing in the inoperative state either across the column or the row resistors, can be completely suppressed in cases where these resistors are not connected to the zero point of the circuit directly, but via additional electronic switches, in which case the corresponding clock phase F, F is to be used for controlling these switches. Thus, for example, the resistor 62 must be applied to the zero point of the circuit during the H-level of the clock signal F In Fig. 3, with respect to the pushbutton switch 3mn and the crosspoint of the respective column and row leads of the matrix, it is shown how the circuit arrangement can be realised in accordance with the known CMOS technology.The first column switch 4n and the second column switch 4m, as well as the resistors 6n, 6m are formed in this arrangement by N-channel transistors, while the second column switch 5n and the second row switch 5m are each formed by a P-channel transistor. The N-channel transistors 4m, 6m and the P-channel transistor 5m are applied to the signal F, hence to the output of the inverter 92 as shown in Fig. 1. In distinction thereto, the N-channel transistors 4n, 6n and the P-channel transistor 5n are applied to the clock signal F, hence to the output of the second NAND gate 91 as shown in Fig. 1.

This mode of operation only formally appears to be in contradiction to the statements made in claim 1, and to Fig. 1, saying that the first column switch 4n must be lying at the clock signal F; and the first row switch 42 at the clock signal F. The fact that the N-channel transistor 4m in Fig. 3 may actually come to lie at the clock signal F, and the N-channel transistor 4n may come to lie at the clock signal F, is due to that these transistors are complementary to the transistors 5m, 5n, so that accordingly, also the opposite clock phase can be used for controlling them.

Hence, there is in fact no contradiction with respect to the mode of operation.

The column inverters and row inverters 7n, 7m as well as the associated hold inverters 8, 8m are conventional CMOS inverters which do not need to be explained in greater detail herein. The high-ohmic dimensioning of the hold inverters 8n, 8m is possible by correspondingly selecting the width-to-length ratio of the channel.

Claims (7)

1. A circuit for a keyboard switch arrangement of the type having a plurality of switches each arranged at a respective crosspoint of an n by m array of column and row conductors, wherein each column and row conductors is coupled via a first electronic switch to the circuit supply voltage and via a second electronic switch to a negative inverter, and wherein the outputs of the inverters associated with the row conductors are coupled to a NAND gate, which NAND gate controls the electronic switches.

2. A circuit arrangement for an electronic equipment input keyboard comprising pushbutton switches arranged in n columns and m rows, having two terminals each, with each of said pushbutton switches, when actuated, connecting one column lead associated with the respective column, directly with one row lead associated with the respective row, and with the circuit arrangement transmitting with respect to the columns a one-out-of-n encoded signal and, with respect to the rows, a oneout-of-m encoded signal, wherein each of the column leads and each of the row leads is applied across a resistor to the zero point of the circuit wherein each of the column leads is applied via a first electronic column switch to the input of a column inverter and, via a second electronic column switch to the supply voltage, wherein each of the row leads is applied via a first electronic row switch to the input of a row inverter and, via a second electronic row switch to the supply voltage, wherein one highly resistive hold inverter is applied to an antiparallel connection to each column inverter and to each row inverter respectively, wherein the outputs of the row inverters are each connected to one of the n inputs of a first NAND gate the output of which is applied to the one input of a second NAND gate, to the other input of which there is applied at least temporarily a rectangular clock signal wherein an inverter is arranged subsequently to the output of said second NAND gate, wherein the control inputs of both said first electronic column switches and said second electronic row switches are applied to the output of said inverter, and wherein the control inputs of both said first electronic row switches and said second electronic column switches are applied to the output of said second NAND gate.

3. A circuit as claimed in claim 2, and wherein said resistors, electronic switches, inverters and NAND gate each comprises a CMOS structure.

4. A circuit as claimed in claim 3, wherein each first column switch, each first row switch and each resistor is realised by an N-channel transistor, the gate terminals of the transistors of both said first and said second row switches and of the resistor associated with the respective row, are applied to the output of said inverter, and the gate terminals of the transistors of both said first and said second column switches and of the resistor associated with the respective column, are applied to the output of said second NAND gate.

5. A keyboard circuit arrangement substantially as described herein with reference to the accompanying drawings.

6. A pushbutton keyboard arangement provided with a circuit as claimed in any one of the preceding claims.

7. An ultrasonic or infra-coil radio or TV receiver control unit employing a circuit as claimed in any one of claims 1 to 5.