GB2031683A - Vehicle speed detectors - Google Patents

Abstract

The vehicle speed detector has a transmit antenna A1 driven by a modulator MOD by way of a GUNN diode source GDS. Vehicles approaching the detector generate particular frequency signals at specific distances from the detector which are received by a receive antenna A2 and fed by way of a mixer M to filter networks F2, F3, F4 which filter particular frequencies related to the specific distances. The filtered signals are fed to respective phase lock loop circuits PLL1, PLL2, PLL3 which provide output signals, the rates of change of which, as determined by differentiating circuits D1, D2, D3, are directly proportional to the vehicle speed. The output signals are fed to respective threshold circuits TH1, TH2, TH3 and speed classification circuits S1, S2 ,S3, the latter being activated only during the positive going output from the respective phase lock loop circuit so that vehicles travelling away from the detector are discriminated against. <IMAGE>

Description

SPECIFICATION Vehicle speed detectors The invention relates to vehicle speed detectors using radar.

Known types of vehicle speed detectors use inductive loops buried in the road surface which obviously require the digging up of the road surface if the loops become faulty which is labour intensive and costly.

An aim of the present invention is to provide a vehicle speed detector which does not require inductive loops to be buried in the road surface.

According to the present invention there is provided a vehicle speed detector comprising a frequency modulated carrier wave radar system, for monitoring the speed of a vehicle approaching the radar, said radar system includes a plurality of filters, each filter corresponding with a particular range of frequencies generated by the presence of a vehicle at a particular distance range from the radar, each filter is connected to an associated speed dependant-signalling means which produces an output signal, the duration of which is governed by a threshold detector and is used to gate the output from a speed classification arrangement so that speed information relating to a vehicle moving away from the speed detector is discriminated against.

The invention will be readily understood from the following description which is of one embodiment only and should be read in conjunction with the following drawings in which: Figure 1 shows a sketch of a typical vehicular traffic situation on a range of road 37 metres long, Figure 2 shows a block diagram of the radar system, Figure 3 shows a phase lock loop voltagefrequency characteristic for the frequency range 150 KHZ to 230 KHZ and Figure 4 shows the circuitry which produces an output signal for gating the speed classification arrangement of Figure 2.

Referring to figure 1 a typical section of road is shown covering a distance of 37m split into three sections of 12m. A series of filters provides range gates to be described later of + 2m centred about distances of 12, 24 and 36m from a frequency modulated carrier wave (FMCW) radar sensor as shown by zones 1, 2 and 3. The shadow zones are also shown. A suitable FMCW radar sensor must have some form of timing mark applied to the carrier if range is to be measured. The sharper the timing mark the more accurate the measurement of range.

Frequency modulation of the carrier is widely used and the timing mark is the changing frequency. The transit time produces a difference frequency between the echo signal and the transmitter signal.

Fora stationarytargetthe difference frequency: for 2.R.f0 c or: - 4R.fm.f c where: fm = modulation rate f = total frequency deviation if we assu me fm = 10 kHz and f = 100 MHz.

At a range of 40m: f, = 4.40.104.108 fr = 3 s 1 08 fr=5.3X108HZ At a range of 4m: fr=5.3x104Hz The accuracy of measurement of a cycle counting detector is given by: R= 4cf = 3.108 = 0.75m 4f 4.1.108 This fixed error can be reduced by a number of techniques such as 'wobbling' the modulation frequency or phase of the transmitter output or alternatively using a non-counting frequency meter.

One characteristic of the frequency modulated carriver wave radar to consider is that targets in motion cause a frequency spectrum due to their Doppler frequency shift. A vehicle with a velocity of say 70 m.p.h. (31 my' ) would cause a Doppler frequency shift of: fd= 2Vfo fd = c fd= 2.31.109 =4.96KHz 3.108 Therefore at 40m range from the sensor, the received frequency from a target moving at 31 ms-1 would be shifted by an amount of 5 kHzfrom the 530 kHz value expected from a stationary target.

If a range slot were to be defined as say t 2m about 40m then a detection filter with a 10% bandwidth would be required, hence even Doppler frequency shifted targets would be adequately detected. At a velocity of 31 ms-' the total time the target would appear within the range slotwould be 130 my'. this would be an adequate period to integrate the returned signal frequency.

A suitable radar block diagram is shown in figure 2. The GUNN diode source is driven by modulator MOD and is connected to antenna Al. Antenna A2 is connected to mixer M. The level of local oscillator power fed to the mixer is most important as the noise characteristics of the mixer are dependent upon the correct level of local oscillator power. The K-band GUNN diode oscillator has an output power selectable between 10 mW and 100 mW and an elec tronictuning range of i 50 MHz.

The target range is related to frequency, hence a bandpass filter effectively defines a range gate and hence range is defined by filter centre frequency.

Referring to figure 2 in detail the block diagram of the radar apparatus is shown. The apparatus com prises a 10 KHz modulator MOD feeding a 24 GHz GUNN diode source GDS which is coupled to trans mit antenna Al via coupler C1. Antenna A2 receives reflected signals which are coupled to mixer M by coupler C2. A vehicle moving into a range gate gen erates a frequency which, for example, is 180 KHz at 14m and 130 KHz at 1 Om. The mixed signals are fed to filter F1 which filters in the range of 100-500 KHz, and fed to subsequent filters F2-F4 which filter in the range of 450-500 KHz, 290-350 KHz and 130-180 KHz respectively. The respective filtered signal is used to control a respective phase lock loop PLL1, PLL2 or PLL3 which provides a direct current output proportional to the frequency.The output voltage varies from 0v at 180 KHzto 10v at 130 KHz as shown in figure 3 for example. The rate of change of output voltage is directly related to the vehicle speed.

The output of each phase lock loop PLL1, PLL2 and PLL3 is fed to a respective differentiating circuit D1, D2 and D3, respective threshold detector TH 1,TH2 and TH3 and a respective speed classification arrangement Sl, S2 and S3 which provide output signals indicative of whether the vehicle speed is fast, medium or slow (F, M, S).

The threshold detectors could conveniently consist of a differential amplifier providing an output signal when a variable input signal on one of the amplifiers input equals or is greater than a predetermined signal applied to the other input of the amplifier. The speed classification arrangement could convenientiy consist of known counting and gating arrangements providing output signals indicative of the vehicle speed.

For vehicles travelling away from the radar sensor the generated frequency increases from 130 KHz to 180 KHz (figure 3) for example. The phase lock loop characteristic is such that the role of aquisition of lock is much faster for increasing frequency than for decreasing frequency as shown in figure 3. As shown in figure 3 the range gate filter is defined between 130 KHz and 180 KHz with the negative output of the phase lock loop going negative in the range of 180 KHz to 230 KHz. It is this latter range which is to be suppressed.

The output of the phase lock loop is fed to a differentiating circuit A by way of input lead IP, figure 4 and amplified. The pulse produced has a duration dependent on the characteristics of the loop and differentiator. The pulse is passed to NAND gate G to sharpen the rise time and then to the clear input CL of D type flip flop FF which produces an output pulse, the duration of which is determined by the Reset signal RS produced by the threshold detector TH which examines the phase lock loop output. The pulse is produced of duration equivalent to the positive going output from the phase lock loop only when the frequency increases. The output pulse OP from the flip flop FF is used to gate the speed classification arrangement SC figure 4.

The above description has been of one embodiment and is not intended to limit the scope of the invention. For example further range rate filters could be employed and the range of the radar extended.

Claims (6)

1. A vehicle speed detector comprising a frequency modulated carrier wave radar system, for monitoring the speed of a vehicle approaching the radar, said radar system includes a plurality of filters, each filter corresponding with a particular range of frequencies generated by the presence of a vehicle at a particular distance range from the radar, each filter is connected to an associated speed-dependant signalling means which produces an output signal, the duration of which is governed by a threshold detector and is used to gate the output from a speed classification arrangement so that speed information relating to a vehicle moving away from the speed detector is discriminated against.

2. A vehicle speed detector as claimed in claim 1 wherein the filters are range gate filters and have a frequency range directly related to the frequencies generated by the presence of a vehicle at predetermined distances from the speed detector.

3. A vehicle speed detector as claimed in claim 1 or 2 wherein each speed-dependant signalling means comprises a phase lock loop, the rate of change of output signal is directly related to the vehicle speed.

4. A vehicle speed detector as claimed in claim 3 wherein the phase lock loop provides a positive output signal which relates to the speed of vehicles approaching the speed detector.

5. A vehicle speed detector as claimed in claim 4 wherein the output signal from the phase lock loop is fed to an associated speed classification arrangement by way of an associated differentiating circuit and threshold detector, said speed classification arrangement being used to provide an indication that the vehicle speed is fast, medium or slow.

6. A vehicle speed detector as claimed in any preceding claim substantially as described with reference to the accompanying drawings.