GB2031193A - A reference voltage source - Google Patents

Abstract

An integrated circuit reference voltage source comprises two MOS transistors T1, T2 of the same conduction type connected in series across a supply U2. The gates of the transistors are connected together and to the drain of one transistor T2. The substrates of the transistors T1, T2 are also connected together, and the drain-to-source voltage U1 of the other transistor T1 represents the reference voltage. This may be compared with the output of a series MOS transistor regulator, to regulate the output voltage (Figure 5A not shown). The transistors are adapted to operated in weak inversion and provide a reference voltage which is proportional to the absolute temperature and further depends practically only on the dimensions of the transistors. <IMAGE>

Description

SPECIFICATION A reference voltage source The present invention relates to a reference voltage source realized in MOS transistor integrated circuit technology, and more particularly to a source providing a reference voltage which is proportional to the absolute temperature. Such a source is called hereinafter a PTAT source and can be used to obtain a reference voltage independent of the temperature or to realize a voltage level detector, for instance.

Reference voltage sources of the above mentioned type are used in analog integrated circuits such as analog-to-digital and digital-to-analog converters, as a calibration source or, as another example, in a device for checking the supply voltage provided by a battery.

Voltage reference sources to be realized in integrated MOS technology are mentioned in the article of David A. Hodges, Paul R. Gray and Robert W. Broderson "Potential of MOS Technologies for Analog Integrated Circuits", in the publication ESSCIRC, 1977, pages 43 to 47. The authors consider different possibilities of realization such as the use of a Zener diode, the use of bipolar transistors to form a band-gap reference, or the use of the difference between threshold voltages of enhancement and depletion MOS transistors. However, those solutions are to complicated and to critical for industrial application and the authors of the above article are of the opinion that it seems unlikely that instrument-quality reference sources will be achieved on-chip in a standard MOS process.

On the other hand, the possibility of using integrated MOS transistor technology with transistors working in weak inversion to achieve a voltage reference source has been indicated by Eric Vittoz and Jean Fellrath in the article "CMOS Analog Integrated Circuits based on Weak Inversion Operation", published in IEEE Journal of Solid-State circuits, Vol. SC-12, No. 3, June 1977, pages 224 to 231. The proposed circuit (see for instance figure 8 of this article) provides only a small voltage and it appears difficult to multiply the same by a stack arrangement of elementary circuits.

Objects and definition ofthe invention A main object of the invention is to provide a PTAT reference voltage source of simple structure, readily realizable in standard MOS technology. A further object of the invention is to achieve reference sources providing PTAT reference voltages of high values by using a stack arrangement of elementary circuits or additional transistors. Still a further object of the invention is the use of such PTAT reference sources for obtaining a reference voltage which is independent of temperature, or for detecting a voltage level.

According to the invention a reference voltage source comprises first and second MOS transistors of the same conduction type adapted to operate in weak inversion, the drain of the first transistor being connected to the source of the second transistor, the drain of the second transistor being connected to a first terminal of a supply voltage source and the source of the said first transistor being connected to the second terminal of the supply voltage source, the supply voltage being high enough to ensure drain current saturation of the second transistor, the gates of the first and second transistors beingzconnected to each other and to the drain of the second transistor and the substrates or wells of the first and second transistors being connected to each other, the drain-to-source voltage of the first transistor forming the said reference voltage.

Avoltage source of this type represents an elementary circuit which can be used in more elaborated circuits to obtain higher reference voltages. Thanks to their simple structure, the circuits of the invention require only very small chip area. The power consumption of the circuits is also very small, as the transistors are adapted to operate in weak inversion. They have good over-all performances and can be designed to be very well reproducible.

Brief description of the drawings Further objects and advantages of the invention will become apparent from the following description of various embodiments of realization indicated by way of example and represented in the attached drawings, in which: Figure 1A is a diagram of an elementary circuit of a PTAT voltage reference source according to the invention; Figure 1B is a diagram of a dynamic circuit corresponding to the circuit of Figure 1A; Figure 2 is a diagram of a PTAT reference source comprising a stack of circuits according to Figure 1A; Figure 3 is a diagramm of a basic circuit providing a higher PTAT reference voltage; Figures 4a and 4B are diagramms of circuits based on the circuit of Figure 3 and comprising additional transistors;; Figure 5A is a simplified diagramm of a temperature-compensated voltage reference source; Figure 5B is a graph showing the base-to-emitter voltage of an auxiliary transistor used in the crcuit of Figure 5A; Figure 5C is a detailed diagramm of a temperature compensated reference voltage source in accordance with Figure 5A; Figure 5D is a simplified diagramm of a voltage level detector, and Figure 6 is a view of the mask plan corresponding to a preferred realization of the transistors of the circuit of Figure 1A.

Description of the drawings and of preferred embodiments of the invention The elementary circuit of a reference voltage source according to the invention as shown in figure 1A comprises two n-channel MOS transistors T1 and T2 realized in a same well. The conduction pathes of these transistors are connected in series between the terminals (+, -) of a supply voltage source providing a voltage U2. The gates of these transistors are connected to each other and to the positive terminal (+) of the supply voltage source, the substrates being also connected to each other and connected to the negative terminal (-) of the said supply voltage source.

To explain the operation of the basic circuit, it might be useful to recall that a MOS transistor can be used to operate according to either one of the following modes: The quadratical mode, or strong inversion mode, in which the gate-to-source voltage is higher than the extrapolated threshold voltage of the transistor (see for instance the book of A.S. Groove, "Physics and Technology of Semiconductor Devices" edited by J.

Wiley & Sons, 1967, chap. 9. page 277; the extrapolated threshold voltage or "turn-on voltage" will be designated hereinafter by VTO); the exponential mode, or weak inversion mode, in which the gate-to-source voltage of the transistor is lower than the said extrapolated threshold voltage.

The transistion between both operation modes is continuous. It is generally considered that in saturation the transistor operates according to the weak inversion mode when ID # ssUT2, where ID = drain current ss = quadratical factor = S Cox S = geometrical shape factor = W/L W = actual width of the transistor channel L = actual length of the transistor channel CL = mobility of charge carriers in the channel Ccx = gate oxide capacitance UT = characteristic voltage = kT/q k = Boltzman constant q = elementary charge T = absolute temperature In the following description it will be understood that when a transistor is said to operate in weak inversion this implies automatically that its gate-to-source voltage is always lower than VTO and that its drain current satisfies the above mentioned inequality. Under these conditions, the drain current of the transistor is given approximately by 1D = S IDO e G T (Vs/UT) -e e (VD/UT)) (3n UT2 e ( - VTO) / nUT (e VsIUT -e - VDIUT) where 100 = characteristic current of the transistor VG = gate to substrate voltage n = slope factor in weak inversion operation Vs = source-to-substrate voltage Vo = drain-to-substrage voltage VTO = extrapolated threshold voltage In the diagramm of figure 1A the drain currents of transistors T1 and T2 are designated by 1ni and 102' respectively. If an additional current a102 is fed into point 1, the drain current of T1 becomes ID1 = ID2 + al02 where a is a constant factor which is independent of temperature. It results from the diagramm of figure 1A that ID1 = S1 ID01 eU2/n UT(1 - e-(U1/UT)) ID2 = S2 ID02 eU2/n UT(e-U1/UT) - e-(U2/UT)).

o2=521oo2eU2/UT (e (Ul/Ur) - e (U2/UT)) it is assumed that U2 - U1#UT so that transistor T2 is saturated. Practically, it will be sufficient that U2 - U1 > 3UT and, in this case, e-(U2/UT)#0 becomes negligible and the following relationship is obtained S I e u2/n UT (1 - e(U1/UT)) = S2 I 0c2 e U2/n UT e (U1/UT) (a+1).

Transistors T1 and T2 being realized in a same well looi = Indo2 and the above expression yields U1 = UT 1 n (1 + S2 (a+1 )/S).

In particular when a = 0, U1 = UT In(l + S2/S1) The voltage U1 between the drain (terminal 1 ) and the source of T1 is thus proportional to the absolute temperature T and further depends practically only on the geometrical shape factors of the transistors.

It appears that generally a small difference AV exists between the threshold voltages of the transistors used, T1 and T2, this difference being typically in the range of 0 to 20 mV. An error of the same order of magnitude results therefrom in the voltage U1, this error being equal to AVIn and being practically independent of temperature.

A way to obtain two transistors T1, T2 with exactly identic characteristics, is to use a single transistor operating alternately as a transistorT1 and as a transistor T2. It will be seen that in the circuit of figure 1A both transistors have two respective electrodes connected together, so that the realization of a commutation between the transistors becomes particularly easy.

Figure iBis the basic diagram of a dynamic embodiment of the elementary circuit of figure lA. Atransistor T operating in weak inversion, has its conduction path connected, on one hand, to a switch SW allowing to couple the corresponding transistor electrode to either one of the terminals of a supply voltage source U2.

The positions Pi, P2 of the switch correspond to the negative and positive terminals of the supply source, respectively. The gate of the transistor is connected to the positive terminal (+) of the supply voltage source and the other electrode of the conduction path of the transistor is connected through a capacitor C1 to the negative terminal (-). When the condition of the switch SW corresponds to position p" the transistor T has the function of transistor T1 of figure 1 A, and in position P2 of switch SW the transistor T operates as T2.If the capacitance of C1 is large enough to assure a continuous level of voltage U1, it can be shown that Us = UT1n(1 +t2/t1) where t1 and t2 are the durations corresponding to the conditions of switch SW illustrated by positions Pi and P2, respectively. The ratio t2/t1 thus replaces in this case the ratio between the geometrical shape factors when using two transistors. If the circuit of figure 1 B is fed from a current source, the capacitance C2 between the terminals (+) and (-) must be sufficiently large to assure the presence of a constant voltage U2 in this dynamic circuit.

The elementary circuit of figure 1A allows, practically with the usual dimensions of the transistors, to obtain voltages U1 in the range of about a hundred millivolts. To obtain PTAT reference voltages of higher value, a number of elementary circuits can be used in a cascade arrangement.

Figure 2 shows a reference voltage source formed by a stack of p elementary circuits. Each elementary circuit comprises two n-channel transistors which correspond to transistors T1 and T2 of figure 1A. The elementary circuits are each associated to a corresponding current source. As shown in figure 2, the elementary circuit of rank k, k = 1,2,3 p .., p comprises transistors Tik and T2k realized in a corresponding well and connected to each other in the same way as transistors T1 and T2 of figure 1A. The corresponding current source comprises a p-channel transistor T7k being connected to the positive terminal (+) of a voltage supply source. The gates of all of the transistors T7k are connected to each other and to the gate of a transistor T70, the drain of which is also connected to the said gates.The conduction path of T70 is connected in series with a circuit element Ro between the terminals of the supply voltage source, the element Ro being adapted to determine the drain current lo ofT70. Ro can for instance be a resistor or a current source. The currents provided by the transistors T7k are designated by lk.

The different elementary reference circuits are connected to each other in the following manner. The source of transistor T11 of the first circuit (k = 1 ) is connected to the negative terminal (-) of the voltage supply source and the source of transistor Talk of the elementary circuit of rank K is connected to the drain of transistorTi(k-1) of the circuit of rank (k - 1). In this way, transistor Tak is fed by the sum of currents lk to Ip while transistor Tic is fed by 1k only. It results therefrom that

where 51k and 52k are the shape factors of transistorsT,k and T2k, respectively.

As will be seen from figure 2, transistor T7k is connected to form a current mirror with transistor T70. In the particular case where all currents I1 to Ip are equal, the total reference voltage becomes

If all elementary circuits are similar, with 52k = S2 and Slk = Si, and if S2 Si, the reference voltage U1 becomes approximately

Thus, the circuit of Figure 2 allows to obtain a reference voltage of a high value, which is exactly proportional to UT and therefore to the absolute temperature T. The power consumption of this circuit can be adjusted by means of Ro, which is an additional advantage of this arrangement. The pairs of transistors T11, T21 to Tip, T2p can be realized in a single well in place of being realized in individual respective wells.In that case the minimal supply voltage must be higher, due to a modulation effect produced by the substrate.

Figure 3 shows another circuit arrangement to obtain higher reference voltages from an elementary circuit according to the invention. Two n-channel transistors T13 and T24, corresponding to transistors T1 and T2 of figure 1A, respectively, are connected to each other in the same way as T1 and T2. This elementary circuit is fed through a p-channel transistor T62 the conduction path of which is mounted in series with those of transistors T13 and T24, between the terminals (+, -) of a voltage supply source.

The drain of transistor T13 is connected to the gate of another n-channel transistor T35 the conduction path of which is mounted in series with the one of a p-channel transistor T51, between the terminals (+, - ). The gates of transistors T51 and T62 are connected to each other and to the drain of T51, both transistors T51 and T62 thus forming a current mirror.

The transistors are dimensioned to operate in weak inversion and the supply voltage is chosen high enough to saturate transistors T24 and T3.

The drain currents of transistors T24 and T35 are designated by 12 and 13, respectively. If S5 and Sg are the respective geometrical shape factors of transistors T51 and T62, the current mirror delivers a current 12 = 13 S6 / S5 The diagram shows furthermore that the drain current I1 of T13 is equal to I2. As the characteristic currents IDe of these transistors of the same chip are equal to each other, and as transistor T35 is saturated, the following relationship exists.

I1 = S1 ID0 eU2/n UT(1 - e-(U1/UT) = I2 = I3 S6/S5 =S3 ID0 eU1/n UT S6/S5 where Sa, S2, S3 are the geometrical shape factors of transistors T13, T24 and T35, respectively, and U1 and U2 are the voltages between the negative terminal (-) and the drains of T13 and T24, respectively, similarly to figure 1A.

In the elementary circuit T13, T24, similarly as in figure 1A U1 = UT 1n(1 + S2/S1) which yields eU1/UT = 1 + S2/S1 and the relationship Ii = 13 yields S1 eU2/nUT S2/(S1+S2) = S3 (1+S2/S1)1/n S6/S5 It results therefrom that U2 = n UT ln [(S3/S1) (S6/S5) (1 + S1/S2) (1 + S2/S1)1/n] Thus, a reference voltage U2 is obtained which is proportional to UT and further depends only on the geometrical shape factors of the transistors and on the slope factor n.

From the above it follows further that I1 = ID0 S3 (S6/S5)(1 + S2/S1)1/n and therefore the currents Ii = 12 and 13 are independent of the supply voltage. The upper limit of loo which is a characteristic value for a given technology, allows to dimension the transistors in order to assure their operation in weak inversion.

The basic circuit of figure 3 allows to obtain reference voltages of practically as high a value as desired, but of course lower than the supply voltage, by using additional transistors in the circuit.

Figures 4A and 4B show two circuits which have a similar behaviour and are derived from the circuit of Figure 3. The five basic transistors which are similar to those of figure 3 have been designated in the same way in figures 4A and 4B.

In the circuit of figure 4A, (Q - 5) n-channel transistors and (Q - 5) p-channel transistors have been added to the five basic transistors, so as to form a corresponding number of additional stages comprising each a p-channel transistor T6i,i=6,7,...,Q and a n-channel transistor T4j,j = (Q + 1), (Q + 2), ..., (2Q-5).

In each stage the conduction pathes of these transistors have been connected in series. The sources of transistors T61 are connected to the positive terminal (+) of the supply voltage source and the gates of these transistors are connected to each other and to those of transistors T51 and T62. The transistors T41 are realized in separate wells and their gate is connected to their drain, their substrate being connected to their source.

The source of transistor T4(Q+1) is connected to the drain of transistor T24 and the source of each transistor T4j is connected to the drain of the preceding transistor T4(ji).

In this way, the drain-to-source voltages of the stacked transistors T4j are added to each other and to the output voltage U2,of the basic circuit. If the transistors T4j are designed to have the same dimensions, the common geometrical shape factor being S4, and if the transistors T6j have also equal shape factors and the latter are further equal to that of transistor T62, the common value being S6, it will be seen that U2 = n Us in [s3/s1ì (Q-4) (Se/S5). (1+S,/S2) (1+S2/Sa) 3 and U21 = U2 + n UT in [S3/S4) (q-5) (S6/S5) (1+S2/Sa Thus, a total reference voltage U2XQ-1 ) appears in this circuit between the drain of the last transistor T4(2Q-5) and the source of T13, which reference voltage is always proportional to n.UT.

In the circuit of figure 4B, (Q-5) n-channel transistors T41 (j = 6, 7, 6,7..., Q) are connected in series between the elementary circuit T13, T24 and the transistor T62 providing the common drain current to all these transistors. The gates of transistors T4j are connected to their drains as in figure 4A. The transistors T4j are realized in separate wells and operate in weak inversion as previously.

The voltage U2 provided by the elementary circuit T13, T24 is given by the same expression as in the case of figure 3. Between the drain and the source of each transistor T4j, which has a shape factor S4, an additional voltage A U = n in (S)S) (i+52/Si)1 is obtained and adds to U2.

The total reference voltage obtained in this circuit between the drain of transistor T4Q and the source ofT13 becomes therefore U2XQ-5) = U2 + (Q - 5) A U.

This reference voltage is again proportional to n.UT.

In practical realizations of circuits according to figures 4A and 4B comprising only two transistors T4j with slope factor ratios not higher than 10, reference voltages of 800 mV can readily be achieved.

Furthermore, PTAT reference voltage sources as described above can be advantageously used in a circuit providing a temperature-compensated or band-gap reference voltage, i.e. a reference voltage that is independent of temperature.

An example of such a circuit schematically shown in the diagram of figure 5A. The arrangement comprises a PTAT reference source, an operational amplifier A, a bipolar transistor Ts (for instance of npn type, n+ p-well - n-substrate) a current source J, a regulating MOS transistor TR (for instance of p-channel type), and a voltage divider R, R2.

The current source J assures a constant current flow (of a value I) through the bipolar transistor Ts. It is known that under such a condition, the base-to-emitter voltage VBE of transistor Ts is a linearly decreasing function of absolute temperature. This relationship is represented in the graph of figure 5B. The value VGO iS the linearly extrapolated gap voltage of silicon at 0 K.

The voltage across the voltage divider RX, R2 (output terminal R) is designated by UR and represents the reference voltage.

The voltage across resistor R2 which is determined by a regulating loop comprising amplifier A and transistor TB, becomes b. UR = U + VBE where b = R2/(R1+R2) If.the PTAT source is dimensioned in order to provide at a given temperature, a voltage U = VGo - VBE a temperature compensated reference voltage of UR = VGO /b is obtained.

The value of this reference voltage can be selected by an appropriate value of ratio b, which also allows to correct an error, if any, of the voltage U, which may result from dissymmetrical transistors Tip, T2p of the PTAT source.

For Ri = 0 and R2 = the reference voltage UR = Vco.

Figure 5C is a detailed diagramm of a temperature-compensated voltage reference source according to the principle illustrated in figure 5A.

The PTAT source used in this embodiment corresponds to that of figure 2 and the transistors thereof have been designated in a similar manner as in figure 2.

The operational amplifier A comprises n-channel MOS transistors T16, T,7, T19, T31, T33 and p-channel MOS transistors T26, T27, T32, T34 as shown in the diagramm of figure 5C.

The voltage U which is proportional to the temperature, is applied to the gate of transistor T16 (terminal -) and the emitter of the bipolar transistor Ts is conected to the gate of transistor Ta7 (terminal +). The drain of transistor T32 (output terminal S) is connected to the gate of the regulating transistor TB, the conduction path of which is connected in seres with the voltage divider Ri, R2 between the terminals of the supply voltage source. The intermediate connection of this voltage divider is connected to the base of transistor Ts, the collector-emitter path of which is connected in series with the conduction path of a n-channel MOS transistor T20 between the terminals of the supply voltage source.

The current source J shown by way of example in figure 5C, comprises a n-channel transistor T28 operating in strong inversion. The stabilized voltage VBE iS applied to the gate of this transistor and the current supplied by this transistor therefore has a constant value I. This current I further feeds a plurality of current mirrors comprising p-channel transistors T29, T70, T71, T72, T73, T74, T75, used to bias the PTAT source.

Transistor T70 delivers a current lo for feeding another plurality of current mirrors comprising n-channel transistors T30, T20 and T19 in order to bias the bipolar transistor Ts and the operational amplifier A.

The PTAT voltage source used in this embodiment comprises five elementary ciruits connected in cascade and having, for instance, a ratio S2/S1 = 81. In order to reduce the influence of leakage currents and improve the behaviour of the circuit at higher temperatures, one can consider, depending on the technology used, to increase the number of elementary circuits, for instance by using 8 such circuits, and to reduce the ratio of the shape factors.

Figure 5D shows another application of the PTATvoltage source according to the invention. This application results from considerations made in connection with figure 5A and the same circuit elements have been designated in a similar manner in figures 5A and 5D.

It will be seen from the circuit diagramm of figure 5D that the regulating transistor offigure 5A has been left out and resistor Ri has been connected directly to the positive terminal (+) of the supply voltage source.

Thus UR = VCC, if Vcc designates the value of the supply voltage. When Vcc crosses the value VGo)b, the state of the output S of the operational amplifier A changes and the circuit thus represents a voltage detector responding to the level of the supply voltage.

The voltage reference sources described here are based on a very simple elementary circuit which is compatible with usual MOS technology. While the description of the elementary circuit has been based on the use of n-channel transistors, the circuit can obviously also be implemented with p-channel transistors.

The chip area required by the described circuits is very small and the design of the circuits allows to achieve very well reproducible characteristics, provided the following points are complied with; In order to reduce the influence of the output conductance of the MOS transistors fairly long channels have to be used. In a silicon-gate CMOS technology, typical values of the channel length L are L 3 12 um for n-channel transistors and L > 20 um for p-channel transistors.

To achieve a good control of the geometrical shape factors S1 and S2, the same channel length is preferably used for transistors T1 and T2.

To obtain a substantial difference and a precise ratio between S1 and S2, transistor T2 is preferably divided into a plurality of elementary transistors of the same dimensions as those of transistor Ti, the said elementary transistors being mounted in parallel to each other.

Figure 6 shows the mask design of a preferred embodiment of the circuit according to figure 1A. Transistor T2 is divided into elementary transistors T2, T2, T2f, and T2-v, which are arranged symmetrically with respect toT1 to avoid the effect of possible gradients of the gate oxide thickness on the silicon substrate. Lines 61, 61', 61", 61"' and 61 Zv of figure 6 indicate the limits of the diffusion zones and lines 62 indicate the outline of the polycristalline silicon gate. Contact openings such as 63 are shown by full lines inside the diffusion zones. Metallized zones 64, 65, 66, 67 are indicated by dashed lines. Zone 64 forms the connection 1 of figure 1A and zones 66 and 67 form the connections with the supply voltage terminals (+) and (-), respectively.

Finally, the outline 68 marks the zone of anchoring to the well or to the substrate.

Claims (13)

1. A reference voltage source realized in MOS transistor integrated circuit technology, comprising first and second transistors of the same conduction type adapted to operate in weak inversion, the drain of the first transistor being connected to the source of the second transistor, the drain of the second transistor being connected to a first terminal of supply voltage source and the source of the said first transistor being connected to the second terminal of the supply voltage source, the supply voltage being high enough to ensure drain current saturation of the second transistor, the gates of the first and second transistors being connected to each other and to the drain of the second transistor and the substrates or wells of the first and second transistors being connected to each other, the drain-to-source voltage of the first transistor forming the said reference voltage.

2. A reference voltage source as claimed in claim 1, wherein a current source is connected to the drain of the first transistor, the ratio between the current suppled by the said source and the drain current of the second transistor being constant and in particular stable with temperature.

3. A reference voltage source realized in MOS transistor integrated circuit technology, comprising a MOS transistor adapted to operate in weak inversion, and further comprising a switching device adapted to couple a first connection of the conduction path of the said MOS transistor alternately to a first and to a second terminal of a supply voltage source, the supply voltage being high enough to ensure drain current saturation of the said MOS transistor, the gate of this transistor being connected through a capacitor to the second terminal of the supply voltage source, the voltage appearing across the said capacitor forming the said reference voltage.

4. A reference voltage source realized in MOS transistor integrated circuit technology, comprising at least two MOS transistors of the same conduction type adapted to operate in weak inversion, and at least two current sources supplying currents the ratio of which is constant and in particular stable !with temperature, the drain of a first MOS transistor being connected to the source of a second MOS transistor, the drain of said second transistor being connected through a first current source to a first terminal of a supply voltage source and the source of said first transistor being connected to the second terminal of the said supply voltage source, the gates of the first and second transistors being connected to each other and to the drain of the second transistor and the substrates or wells of the said transistors being connected to each other and to the source of the first transistor, the drain of a third MOS transistor being connected to the source of a fourth MOS transistor, the drain of the said fourth transistor being connected through a second current source to the first terminal of the supply voltage source and the source of the third transistor being connected to the drain of the first transistor, the gates of the said third and fourth transistors being connected to each other and to the drain of the fourth transistor and the substrates or wells of the third and fourth transistors being connected to each other and to the source of the third transistor, the supply voltage, the current sources and the said first to fourth transistors being so dimensioned that the said first to fourth transistors operate in weak inversion and that the second and fourth transistors are saturated, the voltage appearing between the drain of the third transistor and the source of the first transistor forming the said reference voltage.

5. A reference voltage source as claimed in claim 4, comprising p pairs of transistors of the same conduction type and p corresponding current sources, p being greater than 2, a first pair comprising the said first and second transistors and the other pairs comprising transistors similar to the said third and fourth transistors, two consecutive pairs being connected to each other by having the source of each transistor corresponding to the said third transistor connected to the drain of the transistor corresponding to the third transistor of the preceding pair of transistors, all the transistors of the different pairs of transistors being dimensioned and fed in a similar manner as the first to fourth transistors, the voltage appearing between the drain of the transistor of the last pair which corresponds to the third transistor, and the source of the first transistor forming the said reference voltage.

6. A reference voltage source as claimed in claims 1,2,4 or 5, wherein the said first and second transistors or the transistors of each pair similar to the said first and second transistors are realized in a same well.

7. A reference voltage source realized in MOS transistor integrated circuit technology comprising at least a first and a second MOS transistor of the first conduction type, connected to form a current mirror, the sources of the said transistors being connected to a first terminal of a supply voltage source, the gates of the said transistors being connected to each other and to the drain of the first transistor, and comprising at least a third and fourth MOS transistor of a second conduction type, said third and fourth transistors being fed and dimensioned so as to operate in weak inversion, the drain of the said third transistor being connected to the source of the fourth transistor, the source of the third transistor beig connected to the second terminal of the supply voltage source and the drain of the fourth transistor being fed by the current flowing through the second transistor of the current mirror, the gates of the said third and fourth transistors being connected to each other and to the drain of the fourth transistor and the substrates or wells of these transistors being connected to each other and to the source of the third transitor, and further comprising a fifth transistor of the same conduction type as the third and fourth transistors, the drain of the said fifth transistor being connected to the drain of the first transistor of the current mirror, the source of the fifth transistor being connected to the second terminal of the supply voltage source and the gate of the fifth transistor being connected td the drain of the third transistor, the supply voltage being such that the fourth and fifth transistors are saturated, the voltage appearing between the drain of the said fourth transistor and the source of the third transistor forming the said reference voltage.

8. A reference voltage source as claimed in claim 7, comprising 6th to Q-th MOS transistors of the first conduction type having their sources and gates connected in a similar manner as the said second transistor, and (Q+1) -th to (2Q-5)-th MOS transistors of the second conduction type, fed and dimensioned so as to operate in weak inversion, each of the latter transistors being connected by its source to the drain of the preceding transistor and by its drain and its gate to the drain of a corresponding transistor of the first conduction type, the source of the (Q+ 1 ) -th transistor being connected to the gate of the fourth transistor, the substrates or wells of each of the said transistors being each connected to the source of the same transistor, the voltage appearing between the drain of the (2 Q-5) -th transistor and the source of the third transistor forming the said reference voltage.

9. A reference voltage source as claimed in claim 7, comprising 6th to Q-th MOS transistors of the second conduction type, fed an dimensioned so as to operate in weak inversion, the conduction pathes of these transistors being connected in series between the drain of the fourth transistor and the drain of the second transistor of the current mirror, the gates of each of the said transistors being each connected to the drain of the same transistor and the substrates or wells of the said transistors being each connected to the source of the same transistor, the voltage appearing between the drain of the Q-th transistor and the source of the third transistor forming the said reference voltage.

10. A reference voltage source as claimed in claims 7,8 or 9, wherein the said third, fourth and fifth transistors are realized in a same well.

11. A temperature compensated reference voltage source comprising a PTAT reference voltage source, an operational amplifier, a regulating MOS transistor, a bipolar transistor and means for maintaining the emitter current of the said bipolar transistor approximately constant, a first input of the said operational amplifier being connected to the output of the said PTAT reference source, a second input of the operational amplifier being connected to the emittor of the said bipolar transistor, the collector-emitter path of the said bipolar Iransistor being connected in series with said means for maintaining the emitter current constant, between the terminals of a supply voltage source, the output of the operational amplifier being connected to the gate of the said regulating transistor, the conduction path of the said regulating transistor being apart of the collector-base circuit of the said bipolar transistor, the voltage appearing between the base of the said bipolar transistor and the terminal of the supply voltage source opposite to the terminal which is connected to the collector of the said bipolar transistor, forming the said temperature compensated reference voltage.

12. A temperature compensated reference source as claimed in claim 11, wherein a voltage divider is connected in series with the conduction path of the regulating transistor between the terminals of the supply source, the base of the said bipolar transistor being connected to an intermediate point of the said voltage divider.

13. A voltage level detector comprising a PTAT reference voltage source, an operational amplifier, a voltage divider, a bipolar transistor and means allowing to maintain the emitter current of the said bipolar transistor approximately constant, a first input of the said operational amplifier being connected to the output of the said PTAT reference source, a second input of the operational amplifier being connected to the emitter of the said bipolar transistor, the collector-emitter path of the said bipolar transistor being connected in series with said means for maintaining the emitter current constant, between the terminals of a supply voltage source, the base of the bipolar transistor being connected to an intermediate point of the said voltage divider, said voltage divider being connected between the terminals of the supply voltage source, the output of the operational amplifier forming the output of the voltage level detector responsive to the level of the supply voltage.