GB2030401A - Semiconductor circuit arrangements - Google Patents

Abstract

A monolithic integrated semiconductor circuit arrangement comprises at least one injection logic circuit (e.g. T11) and at least one further circuit (B). The supply currents (Iq) of the further circuits (B) are derived from the injection logic circuit, for example by providing an extra collector zone (4, in Figures 5 and 6) adjacent the injector (1, in Figures 5 and 6) of the injection circuit. In this way problems are avoided which arise when the further circuits (B) which may be interface circuits are supplied from a special peripheral power supply circuit via an intricate conductor configuration, and a fixed ratio between the injector current (Is) of the injection logic circuit (T11) and the supply currents (Iq) for the interface circuits (B) can be maintained. <IMAGE>

Description

SPECIFICATION Semiconductor circuit arrangements The invention relates to a monolithic integrated semiconductor circuit arrangement, comprising at least one injection logic circuit and at least one further circuit.

Injection logic circuits are known, for example from the articles in VALVO-Berichte, Vol. XVIII, No. 1/2, pages 21 5 to 226, and Philips Technical Review, Vol. 33, No. 3 (1973), pages 76 to 85.

Figure 1 of the accompanying drawings diagrammatically represents a cross-section through a semiconductor body showing an example of an injection logic circuit, and Figure 2 is the associated equivalent diagram. The injection logic circuit comprises a PNP transistor the emitter zone 1 of which constitutes the so-called injector, and at least one inversely-operated NPN transistor T2, which is energized by the injector.

The transistor T1 receives a current Is. As a result of lateral transistor action between the zones 1, 2 and 3 in Figure 1 a current ij flows into the base of the transistor T2 which produces a logic inversion of the base signal. Because the transistor T2 is inversely operated the N-regions in its base zone 3 act as multiple collectors (instead of emitters).

It is common practice to include such injection logic circuits, isolated from other circuit sections, in a monolithic integrated semiconductor circuit arrangement. This has the advantage that logic circuits can be combined in one monolithic circuit arrangement with linear circuits, such as operational amplifiers, pulse shapers, oscillators, power outputs etc. In many cases the linear circuits are interface units, which adapt the external signals to the internal logic level and vice versa.

Figure 3 of the accompanying drawings diagrammatically represents the plan view of a monolithic integrated semiconductor circuit arrangement, in which an injection logic circuit A is combined with a plurality of further circuits B which do not include injection logic. Both the injection logic circuit and the further circuits B require for their operation quite accurately defined current supplies (either sources or sinks) which determine the operating point. These currents are applied to the individual circuits by a power supply circuit C, situated at the periphery of the arrangement, via supply lines not shown in Figure 3 for the sake of clarity.

As the complexity of the system to be integrated increases, this method of power supply gives rise to two problems: 1. It becomes more and more difficult to feed these currents via conductors from one point at the periphery of the arrangement to all the further circuits of the arrangement.

2. The supply currents required for the operation of the interface circuits generally are of the same order of magnitude as the injector current to be applied to an inverter of the injection logic circuit. As the logic section becomes larger the ratio of the total injector current to the individual supply currents of the complete circuit arrangement increases accordingly. When developing suitable current supply circuits it is found that, as this ratio increases, it becomes more and more difficult to generate currents which bear a fixed ratio to each other.

In order to mitigate these problems to some extent, it is known to connect a plurality of injection logic circuits contained in a monolithic integrated semiconductor circuit arrangement in series in respect of their supply currents. The complete logic to be provided is then divided among several injection logic circuits, i.e. a plurality of islands, and the injector current, which is applied to the injectors of the first injection logic circuit via one supply conductor is applied from said circuit to the injectors of the second injection logic circuit via a further conductor etc.

It is an object of the invention to construct a monolithic integrated semiconductor circuit arrangement comprising at least one injection logic circuit and at least one further circuit in such a way that the conductor configuration can be simplified and that the relative variation between the current levels of the inverters of the injection logic circuits and the supply currents of the further circuit(s) can be reduced.

According to the invention a monolithic integrated semiconductor circuit arrangement, comprising at least one injection logic circuit and at least one further circuit, is characterised in that the supply current of the at least one further circuit is derived from the injection logic circuit.

Advantages which can be obtained by using the invention are mainly attributable to the fact that the problems of long supply-current conductors can be reduced. Furthermore, the relative spread between the current levels of the injection logic circuits and the further circuits thus supplied can be reduced. This means that output inverters of the injection logic circuits, which take over currents to be swtiched from the further circuits, can be dimensioned more precisely.

Embodiments of the invention will now be described, by way of example, with reference to the further Figures of the accompanying drawings, in which: Figure 4 is the equivalent diagram of a part of a circuit arrangement in accordance with the invention, Figures 5a and Sb show an example of the transistor structures T3 and T4 of Figure 4, in cross-sectional and plan views respectively, Figures 6a and 6b show another example of the transistor structures T3 and T4 of Figure 4, in cross-sectional and plan views respectively, Figure 7 is the equivalent diagram of a further embodiment of a circuit arrangement in accordance with the invention, Figure 8 is the equivalent diagram of yet another embodiment of a circuit arrangement in accordance with the invention, and Figure 9 is the equivalent diagram showing an example of a circuit B which can be supplied with current in the Figure 7 arrangement.

The Figure 4 equivalent diagram of a part of the semiconductor circuit arrangement in accordance with the invention shows by way of example three series-connected injection logic circuits, which are schematically designated T1 1, T12 and T1 3. The significance of the references used for these circuits is as follows: T1 1 denotes a combination including a first injector (T1) with a first inverter transistor (T2); 112 denotes a combination including the same first injector (T1) with a second inverter transistor (T2), and Tri 3 denotes a combination including the same first injector (T1 ) with a third inverter transistor (T2).Each of these injection logic circuits T1 1, T12, T13 is represented in Figure 4 by a diode symbol for the following reason: as can be seen from Figure 2 each combination of an injector (T1 ) and inverter (T2) viewed between its supply terminals (the emitter of T1 and the grounded base of T1 ) acts as a diode junction comprising the base-emitter junction of injector T1 ; in an integrated injection logic circuit Ti 1 including parallel injectors all base-emitter junctions of all the injectors are in parallel so that the injection logic circuit such as Tri 1 when viewed between its supply terminals can be seen as a diode.More than one injection logic circuit can be connected in series for supply purposes; thus, for example, Figure 4 shows three such circuits T1 1, to 2 and T13 connected in series.

Figure 4 also shows how, with the aid of the injector current Is, current sources are formed by means of which sources further circuits B (which are linear circuits, not including injection logic) can be energized. For this purpose there are provided further injector transistor structures T3 and T4, which are connected in parallel with the injectors of the injection logic circuit T1 1.

Figures 5 and 6 show examples of such injector transistor structures. Figure 5a is a cross-section through the relevant section of the semiconductor arrangement and Figure Sb is a plan view of this section. Only one injector (T1 ) and one inverter (T2) of a complete injection logic circuit (e.g. T1 1) are shown in Figures 5a and Sb In order to form the current source a further zone 4 of the same conductivity type is provided adjacent the emitter 1 of the injectorT1 of the injection logic circuit T1 1. This zone 4 acts as a collector which with the injector (emitter zone 1) constitutes a further injector transistor structure. From the zone 4 the desired supply current lq for the further circuit section B is derived.From the geometry of this arrangement it is apparent that the current Iql when the Early effect is neglected, has the same magnitude as the base current of a logic inverter.

As a result of the Early effect the current lq becomes slightly greater, but it is always in a fixed ratio to the base current of the inverter. If a supply current Iq with a small spread is required, a design of the current source in accordance with Figure 6 is preferably chosen. Here the collector zone 4 at least partly surrounds the injector emitter zone 1 in any annular fashion.

Figure 7 shows the circuit diagram of a further embodiment of a circuit arrangement in accordance with the invention. In this arrangement the supply current Iq for the further circuits B is determined by an inverter T20 ore21 of the injection logic circuit T1 1. The inverter (as illustrated for the inverter T2 1 ) may then directly energize the further circuit B, or (as illustrated for the inverter T20) it may be arranged as a current mirror.

Figure 8 shows a further circuit arrangement in accordance with the invention. The logic condition of the circuit section C is determined by the supply current 1 q and the drive current 1St of the inverter T22. The current mirrorT25 ensured that the ratio of the drive current 1St to the current Iq' is independent of the injector current Is and is greater than unity. This ensures a well-defined drive of the circuit section C.

Figure 9 shows an example of a circuit B which can be supplied in the Figure 7 arrangement. The current Iq from transistorT2i in Figure 7 is mirrored in the current mirror comprising transistors T90, T9 1 and T92 and after mirroring supplies an output amplifier comprising transistors T93 to T96. This output amplifier controls the current through a load resistor R1 via a transistor T97 which is not incorporated in the integrated circuit. The output amplifer is controlled via a transistor T98 by a signal current 15t supplied by one of the other circuits B in the Figure 7 arrangement.

Claims (7)

1. A monolithic integrated semiconductor circuit arrangement, comprising at least one injection logic circuit and at least one further circuit, characterised in that a supply current of the at least one further circuit is derived from the injection logic circuit.

2. A circuit arrangement as claimed in Claim 1, characterized in that said supply current is taken from a collector zone of an injector transistor structure of the injection logic circuit.

3. A circuit arrangement as claimed in Claim 2, characterized in that the said collector zone at least partly surrounds an emitter zone of said injector transistor structure.

4. A circuit arrangement as claimed in Claim 1, characterised in that the supply current is provided by at least one inverter in the injection logic circuit.

5. A circuit arrangement as claimed in Claim 4, characterized in that the at least one inverter is arranged as a current mirror.

6. A circuit arrangement as claimed in any of the preceding Claims, characterized in that a plurality of the injection circuits are connected in series in respect of their supply currents.

7. A monolithic integrated semiconductor circuit arrangement substantially as described with reference to any of Figures 4 to 9 of the accompanying drawings.