GB2027297A - Digital frequency discriminator - Google Patents

Abstract

In a digital frequency discriminator the instantaneous frequency of a signal is formed from the difference between two successive instantaneous phase values derived by sampling the signal x(t) and the associated quadrature component y(t) and forming a digital phase word by simple logic operations from SIGN X and SIGN Y and the magnitudes ¦x¦ and ¦y¦ of the signals x(t) and y(t). Interpolation between the levels discriminated by comparison between two successive phase words may be achieved by weighted averaging of a plurality of successive phase words. <IMAGE>

Description

SPECIFICATION Digital frequency discriminator The present invention relates to a digital frequency discriminator. Known frequency discriminators operate, for example, on the principle of edge demodulator, push-pull edge demodulator, Riegger circuit, ratio detector, f-detector, entrained oscillator or power demodulator (Meinke/ Gundlach, 3rd edition, page 1 383 et seq.).

A feature common to all principles is the use of one or more bandpass filters, which on account of their natural frequency behaviour set limits to a frequency measurement in a very short time. For the same reason, the use of these frequency discriminators at very low frequencies presents problems, because band-pass filters with the necessary quality are very difficult to manufacture.

Also the known counting discriminator, which by counting out passages through zero over a predetermined averaging period makes possible a statement about a measured average frequency, fails at very low frequencies, because the measuring times become too long. The same disadvantages are suffered by a frequency discriminator operated by means of PLL (= phase-synchronized control loop).

None of the described frequency discriminators is capable of making a statement about the signal frequency before the expiry of a signal period, although this would be desired, for instance, for measurements of very low frequency signals.

According to the present invention there is provided a digital frequency discriminator comprising a means to sample a signal at a sampling frequency fs, means to determine the difference between two successive instantaneous phase values of the signal, and means to form therefrom the instantaneous frequency of the signal.

The instantaneous frequency of a signal is determined from the intantaneous phase, whereby, from a given, time-discrete complex signal z(t) = x(t) + jy(t), consisting of a real part signal x(t) and an imaginary part signal y(t) separated in phase by 90", the signs and magnitudes of the part signals x(t) and y(t) are obtained. From this information, a 3 + k-bit phase word is formed.

By subtraction of two successive phase words, a 3 + k-bit frequency word is obtained, which can be further processed by known means.

The frequency discriminator is in principle free of time constants-with the exception of the sampling interval Ts = fs -and therefore is capable of reacting directly to frequency jumps.

In the complex signal z(t) the production of the "quadrature component" y(t) is carried out from the "in-phase component" x(t), for instance in a so-called Hilbert-transformer, which operates as a wide-band 90 phase-displacer.

In digital signal processing, use is frequently made also of the preparation in "in-phase" channel or "quadrature" channel through quadrature mixers with carrier signals displaced by 90".

In the latter case, a frequency conversion takes place into the range about f = O; as a consequence of the complex signal processing, positive and negative frequencies in the range

are distinguishable. Due to the band limitation through the low-pass filters with the limiting frequency B fg = 2 in both the real-part and the imaginary-part channels sampling can be carried out without harming the sampling theorem, using for each the sampling frequency f5= 2fug= B.

If one assumes the presence of a signal pair x(t), y(t), the production of which is possible, as described above and if it is further assumed that the signals x(t), y(t) are time-discrete values, that is sampling values, which follow one another at the time intervals 1 Ts = - where fs Ts = Sampling period, and fs = Sampling frequency then advantageously the following steps may be carried out.

1st step The sign of the time-quantized signals x and y is determined. If these are analogue sampling values, then sign comparators which provide the sign information SIGN Y and SIGN X are necessary for this purpose. If the sampling values x and y are already available in digitalized form, for example m-bit-amplitude-quantized, then the most significant bit (MSB) already constitutes this sign information, and the two comparators are superfluous.

The logic sign signals are defined as follows:-

0 for Y#0 SIGN Y= L for Y < O 0 for x#0 SIGN X = L for x < O In the same manner, the MSB is also established in the "one's complement"-"two's complement"-and "sign + magnitude"-code.

2nd step The amounts or magnitudes Ixl and lviof the input signals x and y are obtained.

In the case of analogue sampling values, a respective full-wave rectifier for each is provided for this purpose. For digitalized sampling values x and y, the formation of the absolute value must be carried out having regard to the computing rules specific for the respective code. Thus for example, in the "sign + magnitude"-code the value is simply obtained by omitting the sign bit (MSB).

in the "one's complement" code, when a negative sign of the signal is present (MSB = SIGN = L) all the bits must be inverted, in the "two's complement" code the value L must be added in addition in order to obtain the absolute value.

3rd Step The magnitudes Ixl and lyl are compared with one another in a comparator. The following applies for the logic comparator output signal:

O for |y|#x K = L for |y|#x 4th Step As a function of the signal K a polarity inverter is actuated, at the two inputs of which the signals lxiand lvi appear and at the outputs of which the signals x0and y0appear. If |y|#|x|, the signals lxiand lvi are applied non-transposed to the outputs x0and y0.For |Y| zjyl > lxj,|X| and |v| are supplied transposed to the outputs, and therefore for

Owe have x0 = lxi |x| and y0 = lvi # = L we have x0 = lvl and y0 = lxi The polarity inverter can also comprise a 2:1 demultiplexer. In every case, the following relationship therefore exists for the signals x0 and y0 Y0#x0 5th Step To produce a (3 + k)-bit phase information, the signal x0 is evaluated with the weighting factors W1,W2. . .W2k-1 for a total of (2k ) 1) times. The results are then compared in 2k comparators with the value yO. The weighting factors should be determined according to the following rule:

W1 = tan( ) . 45') W2= tan( ~ . 4501 2k

2k - 1 W2k-1 = tan 2k;1 45 2k therefore

= tan( n. 45 ) The following applies for the comparator output signals:

0 for y0#x0 . W, K1 = L for yO > xO . W, O for y0#x0 . W2 K2 L for y0 > x0 . W2 0 for y0#x0 . W2k-1~ K2k-1 = Lfory0 > x0= W2k1 L for y0 > x0 . W2k~1 6th Step The comparator output signals K1, K2... K2k-1 are applied to the input of a "threshold value logic", which possesses 2k - 1 inputs and k outputs. Its function is to convert the sum of the Lbits, which occur always without gaps and flush at the left in the (2k - 1)-bit word K1, K2 . K2k1, into a k-bit binary word (transverse summation).

In general, for any chosen value of k, the following relationship exists between the output bits of a threshold value logic b0, b1 . . . bk-1 and the input bits K1, K2. . K2k-1 supplied from 2k - 1 comparators:

LSS (Least Significant Bit) by K2k-l MSB (Most Significant Bit) 7th Step The (3 + k)-bit phase word required for obtaining a (3 + k)-bit frequency word is obtained as follows: (a) The most significant phase word bit is the logic sign information of the y-signal: MSB1 =SIGN Y (b) The second most significant phase word bit is the modulo-2-addition, i.e. the EXCLUSIVE OR linking of the sign information of the signals y and x:: MSB2-SIGN SIGN X (c) The third most significant phase word bit is the modulo-2-addition or the EXCLUSIVE-OR linking of the sign information of the signals y and x and of the comparator signal K: MSB3 = SIGN YGSIGN X + K or MSB3 = MSB2#K (d) The still lacking k phase word bits are the EXCLUSIVE-OR linkings of MSB3 and each of the bits ....... b0, which come from the threshold value logic: MSB4 = MSB3O+bk1 MSB5 = MSB3#bk-2 LSB = MSB3(3bo (e) The (3 + k)-bit frequency word is obtained by subtraction of two successive (3 + k)-bit phase words spaced at the sampling interval T,=-- .

fs For this purpose, the (3 + k)-bit phase word is applied to the input of a delay storage with the delay time Ts= The delayed phase word passes, after the inverting of all 3 + k bits, to the second input E2 of a full adder. The undelayed phase word is applied to the first input E, of the full adder.If the "carry-in' '-bit of the full adder is applied to "L", then at the adder output A frequency words are obtained which are also (3 + k)-bit quantized and follow one another at the sampling interval 1 Ts= fs Embodiments of the present invention will now be more particularly described by way of example with reference to the accompanying drawings in which:: Figure 1 shows oscillations of real part, quadrature component and associated phase +(t) over a signal period T, Figure 2 is a diagram illustrating the instantaneous phase +(t), Figure 3 shows the sub-division of the complex x, y plane, Figure 4 shows a non-recurring integrator to improve the frequency resolution, Figure 5shows a first logic circuit embodying the invention, Figure 6 shows another logic circuit embodying the invention, Figures 7, 8, 9 show threshold value logics for different values of K, Figure lOis a time diagram for phase determination in a 5-bit discriminator, Figure ii shows a yet further embodiment of a circuit, and Figure 12 shows a threshold value logic circuit for another value of K.

Referring now to the drawings, in Fig. 1 a signal period T of the complex signal z(t) is shown in the form of a cos-oscillation of the real part component x(t) and a sin-oscillation of the quadrature component y(t). Furthermore, the associated phase t) and its time derivative (t) are also plotted. The frequency information can be obtained directly from the sign-evaluated increase in the phase pattern, that is indirectly from the signs and values of the part signals x(t) and y(t). In the complex plane, the pointer z(t) = x(t) + jy(t) rotates, for example anti-clockwise at a constant angular speed, the length of the pointer remaining constant and the tip of the pointer consequently describing a circle (Fig. 2).

The instantaneous phase f(t) may be calculated from

y(t) tan-1 - for x~O x(t) f(t) = tan - 1 tan - ' - + # for for xtO x(t) Its first time derivative f(t) is the angular speed of the revolving pointer or the instantaneous frequency of the complex signal #(t) = #(t) A pointer rotation anti-clockwise through the quadrants I, II, III, IV in Fig. 2 is defined as positive frequency and a clockwise rotation in the sequence IV, III, II, I as negative frequency.

In obtaining the phase f(t), the complicated formation of the tan-l of the quotient y(t) x(t) may be avoided by sub-dividing the complex x, y-plane into 2" = 23+k sectors of equal angle.

Fig. 3 shows for this purpose an example with k = 1 comprising 24 = 16 sectors each of angle 22.5 .

A number in the form of a (3 + k)-bit binary word can be uniquely associated with each sector, the obtaining of which numbers is explained below. This sector number therefore does not exactly characterize a phase value, but a phase range, within which the accurate phase value is present at a specific instant. With the 16 sectors of the above example no phase values are distinguishable within a sector having a subtended angle of 7r 22.5' - - 8 There is thus not a continual phase pattern over a signal period as in Fig. 1, but a step-shaped pattern comprising 16 steps.

As a consequence of this sub-division into phase sectors, certain features result in the determining of frequency by subtraction of phase values following one another at time intervals of Ts= fS Assuming that the complex signal, consisting of a cos-oscillation (real part) and a sin-oscillation (imaginary part) is sampled with exactly the 1 6-times signal frequency, that is f 1 = 16f or - = f, 1 6 in such a way that the sampling points do not coincide with the change of the phase sectors (discontinuity points of the phase staircase).

The difference of successive phase values is always exactly equal to 1, because in each case jumps take place, exactly from the centre to the centre of adjacent phase sectors. A unique frequency indication also results if 1, 2, 3 or more phase sectors are jumped over exactly on each occasion.

Unique frequency values are supplied by a frequency discriminator with a sub-division into 16 phase sectors, only if f k - = --, where 8~k~ + 7.

fS 16 In general, k will not be a whole number. Let us assume, for example that the relationship is T fs f 1 1/3 - = - = 48, or - = - = - Ts f f5 48 16 i.e. a signal period is sampled with 48 sample pulses. At each step of the "phase staircase", 3 sampling pulses occur. The difference between successive phase values therefore gives on each occasion twice in succession the value 0 and then when the phase sector changes, the value 1/,6.

The results at the output of the frequency discriminator thus oscillate periodically between the two values f f 1 --0and - fS fs 16 since the following relationship is true 1 1 48 16 48 16 Apart from the statement that the measured frequency lies between the value 0 and 1/,6, averaging with respect to time over a plurality of samples (in the present case over 3 sampling values) enables the resolution to be still further improved: of three sample values, one of them then reaches the value 1/,6 and two reach the value 0, and therefore the sampling ratio of the oscillation between these two values is 1/3.At the output of an averaging circuit connected after the frequency discriminator (e.g. a non-recurring integrator of m samples), the following exact frequency value consequently appears f 1 1 1 f5 3 16 48 In a second example the following is chosen:: T f5 f 1 1/2 - = - = 32, or - = - - - Ts f f5 32 16 At each step of the phase staircase, two sampling values occur, the phase subtraction alternately the values f f 1 -=0 and- = f5 f5 16 Here the two values occur with equal frequency, and the sampling ratio of the fluctuation is +, from which one can conclude by averaging that the actual frequency is: fly 1 2 2 16 32 The described embodiment of the frequency discriminator therefore normally supplies continually at the sampling interval at its output values which continuously oscillate to and fro by one quantization step.The frequency grid in the range - 0.5= - +0.5 fS is determined by the number of the phase sectors (e.g. 16). The frequency to be measured always lies between those values of the frequency grid about which the discriminator output oscillates.

A desired frequency resolution can always be achieved by a correspondingly large number of phase sectors. Even with a relatively coarse phase- and frequency-grid, it is possible from the frequency distribution at which the adjacent frequency values occur to draw conclusions about the frequency to be measured. A non-recurring integrator makes possible an improved frequency resolution within the original frequency grid (interpolation) (Fig. 4).

In our chosen example comprising 1 6 phase sectors, the largest possible "positive" frequency f 7 ~ = + ~ fs 16 is indicated when according to Fig. 3 the phase sectors are passed through in the sequence 0, 7, - 2, 5, - 4, 3, i.e. that six sectors are always jumped over.

When a signal period is sampled with exactly two samples

{f 1\ fs 2 , the phase sectors 0, - 8, 0, - ..... or any other combination of opposite sectors are passed through, seven sectors always being jumped over. In principle, this case of the half sampling frequency can be interpreted both as the largest "positive" and also as the largest "negative" frequency, since opposite phase sectors in the complex x, y-plane can always be reached by two routes, namely by rotating anti-clockwise (+) or clockwise (-). The nature of the Two's Complement Code here results, however, in the frequency output f 8 fas 16 and thus uniquely associates a negative sign when half sampling frequency exists.

Finally, when more than seven phase sectors are jumped over in the sampling, as in the case 0, - 7, 2, - 5, 4, - ..... in Fig. 3, then one is travelling clockwise in the complex x, y-plane and consequently one obtains "negative" frequency results, e.g.

f 7 f5 16 The smallest (in magnitude) negative frequency f 1 f 16 is indicated by the frequency discriminator when the sectors are sampled in the sequence 0, -1, 2, -3,.

To summarize: Where the complex signal plane is sub-divided into 16 phase sectors, the complex signal is recognized for the sampling cases f 7 0- --- as a positive frequency (cos, sin-signal) fs 16 and for 8 f 15 ft6 -'=- as a negative frequency (cos, -sin-signal).

Is fS 16 The simplest embodiment of frequency discriminator is represented by the circuit of Fig. 5. A signal period is sub-divided into 8 phase sectors, each covering a range of 45 , the digitalized real part values x and the imaginary part values y are supplied word-parallel at the sampling interval 1 Ts = to the two inputs. There is a free choice of the amplitude quantization and thus of the word length, and also of the method of representation in "sign/magnitude"-, "one's complement' '-or "two's-complement-" code. A 3-bit phase word (23 = 8) corresponds to the 8 phase sectors, which can be obtained in a simple manner from the sign bits (MSB's) of the signals x and y and the decision K (compare the values lxi and lvl by EXOR-linking.The associations can be easily constructed by using "logic tables". The difference between successive phase words can be obtained according to the rules of the "Two's-complement" by subtraction of the phase word preceding in time by Ts from the present phase word. For this purpose, all three bits at the output of a delay-line storage should be inverted and applied to the input of a full adder E2, at the other input E1 of which the undelayed phase word occurs. The "carry-in" input of the adder is at logic "L". The 3-bit output of the summator represents the output signal of the frequency discriminator, and the overflow bit is ignored.

Fig. 6 shows the realization of a frequency discriminator which supplies 5-bit frequency words at its output. This requires additional to the 3-bit circuits a polarity reverser controlled by the comparator output K, three evaluators W1 to W3, three comparators K, to K3, a threshold value logic and two further EXOR functions.The signal x0 evaluated with the weighting factors W1=tan 1 1.25 = 0. 199 W2=tan 22.50 = 0.414 W3=tan 33.75 = 0.668 is compared in three comparators with the signal yO. The results K1, K2, K3 are converted by the threshold value logic for k = 2 (Fig. 8) into the logic signals K2 and K10K20K3. By EXOR linking of these signals with MSB3, the last two bits MSB4 and LSB of the 5-bit phase word are produced. The obtaining of 5-bit frequency is carried out in the same manner as before: except that the delay-line storage with inverter and the full adder are 5-bit versions.

Fig. 10 represents a time diagram for phase-obtaining in the 5-bit frequency discriminator. For the sake of easy understanding, the signals are not represented by sampled values but are shown as continuous in time. Any kind of sampling situation can therefore be incorporated in the same figure. By simple modulo-2-additions, the leading bits MSB1, MSB2 and MSB3 are obtained from the sign bits SIGN Y, SIGN X of the input signals and from the comparator signal K. At the input of the threshold value logic the signals K1, K2, K3 are present; their outputs K2 and K1Q+K2e+K3 are converted by inverting with signal MSB3 into the least significant phase word bits MSB4 and LSB.

Finally, Fig. 11 shows an embodiment for the general case of obtaining a 3 + 4-bit phase word. By comparison with Fig. 6, the logic structure does not need to be changed but only the number of logic elements needs to be extended: those required are, (2k - 1)-evaluators W1 to Wok 1' (2k - 1) comparators, one threshold value logic for k bits and a total of (k + 2)-EXOR functions.

Threshold value logics for k = 1, 2, 3, 4 are shown in Fig. 7, 8, 9 and 12 with the associated logic tables. EXOR-linking of several logic variables can with advantage be carried out by ''parity-check" circuits (Fig. 12). These supply, for instance, a "L" at the output, when the number of L-values at the one input is an odd number and a "0" when it is an even number.

Claims (10)

1. A digital frequency discriminator comprising a means to sample a signal at a sampling frequency fs, means to determine the difference between two successive instantaneous phase values of the signal, and means to form therefrom the instantaneous frequency of the signal.

2. A digital frequency discriminator as claimed in claim 1, comprising means to form a (3 + k)-bit frequency word, where k is a positive integer or zero, from the difference between two (3 + k)-bit phase words, and means to form the two (3 + k)-bit phase words by logic operations from respective signs SIGN X and SIGN Y and from respective magnitudes lxi and lvi of a signal value x sampled at the sampling frequency f, and of an associated quadrature component y of the signal value x.

3. A digital frequency discriminator as claimed in claim 2, comprising two respective sign comparators to give SIGN X and SIGN Y, where SIGN = 0 for x, yO and SIGN = L for x, y < O, and a full-wave rectifier to form the magnitudes Ixl and lvi.

4. A digital frequency discriminator as claimed in claim 2, comprising means to form the magnitudes Ixl and lvi in the "sign + magnitude"-code by omitting the sign bit, in the "One's Complement" code with negative sign (MSB = SIGN = L) by inverting all the bits, and -in the Two's Complement"-code by inverting all the bits and adding the value L.

5. A digital frequency discriminator as claimed in either claim 3 or claim 4, comprising a comparator to compare the magnitudes |x| andand lvi and to supply an output signal K = 0 for |y|#|x| or an output signal K = L for lvi > lxi, a polarity inverter having input signals Ixland lvi and so actuatable as a function of the signal K, that for K = 0, the signals lxi and |y|-are non- transposed to give output signals x0 and yO, and that for K = L, the signals Ixl and lvi are transposed to give the output signals x0 and yO,a means to evaluate the signal x0(2k - 1)times with weighting factors Wn,where n is a cqnsecutive index from 1 to (2k - 1) and

Wn=tan( . 450 1 t (2k 1) comparators each to compare a respective one of the signals xO. Wn with the signal yO and to give comparator output signals Kn where Kn = 0 for yO=xO Wn and Kn = L for yO > xO. Wn, and a threshold value logic having (2k - 1) inputs and k outputs and to convert the sum of the L-bits of the (2k - 1) comparator outputs into a k-bit binary word, whereby the k outputs designated b0 to bk~, are linked to the comparator output signals Kn by the formulae

wherein m is the consecutive index from zero to (k - 2) and (3 is the symbol for an exclusive-orlinking (EXOR), the most significant phase word bit being the logic sign information of the quadrature component y, therefore MSB1 = SIGN Y, the second most significant phase word bit being the EXOR-linking between the sign informations of x and y, therefore MSB2 = SIGN YOSIGN X = MSB1GSIGN X, the third most significant phase word bit being the EXOR-linking between the second most significant phase word bit and the comparator output signal K, therefore MSB3 = MSB23K, the next most significant phase word bits being the EXOR-linking between the third most significant phase word bit and a consecutive one of the outputs of the threshold value logic bk~, to b,, therefore MSB4 = MSB2Gbkl and least signficant bit LSB = MSB3Q+b0.

6. A digital frequency discriminator as claimed in claim 2, comprising a delay storage with a delay time 1 T2 = - f to which the (3 + k)-bit phase word is applied as an input, a means to invert the delayed phase word, and a full adder to the second input of which is applied the inverted delayed phase word and to the first input of which is applied the undelayed phase word, the "carry-in" bit of the full adder being on "L" and the output of the full adder supplying (3 + k)-bit words, at a sampling spacing of Ts= -.

fS

7. A digital frequency discriminator as claimed in claim 2, wherein a non-recurring integrator averages through R successive (3 + k)-bit frequency words, where R is a positive whole number.

8. A digital frequency discriminator substantially as hereinbefore described with reference to Figs. 3 to 5 of the accompanying drawings.

9. A digital frequency discriminator substantially as hereinbefore described with reference to Figs. 3, 4 and 6 of the accompanying drawings.

10. A digital frequency discriminator substantially as hereinbefore described with reference to Figs. 3, 4 and 11 of the accompanying drawings.