GB2027237A - Method and arrangement for guaranteeing the coherence of data between masks and other memories on a data-processing system which operates by multiprocessing - Google Patents

Abstract

In an arrangement for ensuring the coherence of data or information in a multiprocessing system, which data or information is recorded in a memory assembly formed by a central memory (MC) and at least two caches stores (C1, C2) associated with respective processors (P1, P2) forming part of the system, when one of the processors belonging to the system alters or updates an item of information, this updated item of information is stored at a single location in the memory assembly, the original non- updated item of information is invalidated in any cache stores in which it may also be present, and any updated item of information is maintained unique in the memory assembly of the system. <IMAGE>

Description

SPECIFICATION Method and arrangement for guaranteeing the coherence of data between masks and other memories in a data-processing system which operates by multi-processing The present invention relates in general to a digital data or information processing system and in particular has as an object a method and an arrangement for guaranteeing the coherence of data or information between masks and other memories, in particular the central memory, of a system which operates by multiprocessing, that is to say which has a plurality of processors.

A mask, which is also called a pre-memory in the literature, is an easily accessible memory of small capacity which is fitted to the processor of a data processing system and whose access time is shorter than the access time of the main memory. The effectiveness of a mask depends in essence on the number of times that the associated processor calls up the same data in the course of executing a programme.

Various schemes may be envisaged for operating a mask, principally as a function of the characteristics of the processing system.

In general terms, since the contents of a mask may have to be altered at any time, it is necessary, inter alia, to perform transfers of data between the central memory and the mask, to update the data in the mask, and to retransmit all or part of the data from the mask to the central memory.

None of these various operations in fact presents any major problems in the case of a data-processing system having only one processor. In fact, the only problem is reducing to a greater or lesser degree the duration of these operations and the frequency with which the mask is emptied.

It should be mentioned that in cases where only one processor is used, it is perfectly possible to defer the writing in the central memory of an item of data or information which has previously been updated in the mask. However, in certain cases, to avoid the transfer involved, the item of data is in fact updated simultaneously in the mask and the central memory.

Although there is no problem in deferring the writing in the central memory of an item of data which has been updated in a mask in the case of a mono-processor, this is not true of a system which operates by multiprocessing. In effect, since it is possible for any processor to alter an item of data present in its mask and because this item of data, in its unaltered form, may also be present in another mask or neighbouring mask, conflicts may very soon arise which are liable to cause major errors in processing.

A A chief object of the invention is to remedy this deficiency by employing a scheme which in particular enables deferred writing to take place between a mask and the central memory of a multiprocessor processing system, that is to say which enables coherence to be guarenteed between the data or information in the masks and the central memory while, of course, at the same time enabling a plurality of jobs to be executed concurrently by the various processors or the same job to be performed in succession by different processors.

To this end, the invention provides a method of ensuring coherence in the data or information in a data processing system which operates in particular by multiprocessing, which data or information is recorded in a memory assembly formed by at least one central memory and at least two masks associated with respective ones of two processors belonging to the system, which method is characterised in that it consists, when one of the processors belonging to the system alters or updates at least one of the items of information in the memory assembly, in recording this updated item of information at a single location in the memory assembly, in invalidating the original, non-updated item of information in the neighbouring masks in which the said information may also be present, and in keeping any updated item unique in the memory assembly of the system.

In accordance with another feature of the method according to the invention, when a processor belonging to the system wishes to write an item of information, this item is written in the mask associated with the processor which makes the request.

In accordance with another feature of the method according to the invention, when the selected address in a mask at which an item of information is to be written already contains an updated item of information which cannot be erased, the item of information least recently used is first of all found in the mask and then transferred to the central memory, which amounts to the deferred writing of this item of information.

In accordance with another feature of the method according to the invention, when a processor belonging to the system asks for an updated item of information present in another mask to be transferred to its own mask, this updated item of information is transferred to the mask of the processor making the request, possibly after space has been made, in the mask as above, and the same item of information is then invalidated in the other mask.

The invention also provides an automatic data processing system which operates in particular by multiprocessing, of the kind comprising a memory assembly formed by at least one central memory, at least two masks associated with respective ones of two processors, at least one main bus for transmitting data or information between the memory assembly and the processors, and in which each mask is for example divided into m levels containing n columns, each level being associated with an identifying index having m levels and p columns, n being a multiple of p a comparison circuit being associated with each level of the index, which is characterised in that with each column of the index is associated a memory in which are recorded two items of data which refer to the items of information identified by the index which are present in the mask and which relate respectively to the validity of these items of information and to their updated or non-updated status.

In accordance with another feature of the arrangement according to the invention, the above-mentioned two items of data are recorded in the index associated with each mask.

In accordance with another feature of the arrangement according to the invention, all the transfers of information in the system take place along one single main connecting bus.

Other features, advantages and details will be more clearly apparent from the following explanatory description, which is given with reference to the accompanying drawings, which appear solely by way of example and in which: Figure 1 is a schematic view in block-diagran form of a data processing system which operates in particular by multiprocessing: Figure 2 shows, in the form of a flow chart, the process of writing an item of information asked for by one of the processors of the system, Figure 3 shows, in the form of a flow chart, the process of reading an item of information asked for by one of the processors of the system, and Figure 4 shows, in a simplified form, the structure of a mask belonging to a processor in the system, to illustrate the above reading and writing phases.

Fig. 1 is a schematic view of a data processing system which operates in particular by multiprocessing. In other words, the system comprises at least one central memory MC, a plurality of processors P1, P2, . . Pn with which are associated respective masks C1, C2, . . Cn, and at least one input/output processor P E/S which in turn is connected to a plurality of peripheral units T,, T2 Tnt the processors and the central memory communicating with one another via a single connecting bus BS. Each processor is connected to its mask by a unidirectional address bus AD and a bidirectional data bus DT.

Referring more particularly to Fig. 4, a mask C1 or C2. . or Cn has the following structure: -a memory section proper M in which information is recorded. This memory section M M is divided for example into four levels, 0, 1, 2, 3 each containing 1024 words. Each level is divided for example into 256 columns each holding a block of four words each of four octets.

~an index section R which is similarly divided into four levels 0, 1, 2, 3, corresponding to respective ones of the four levels of the memory section M. Each level is divided into 256 columns, each column holding an item of data relating to the information in the corresponding block in the memory section M.

In a known fashion, the memory section contains the information or data proper. In a column of the index section R are recorded the most significant bits of the main memory address of the block in the memory section M which is identified by this column of the index. The least significant bits of the same address are used to identify both a column in the index section R and a column in the memory section M of a mask.

Each column on each level of the index R of a mask contains two additional items of data relating to the items of information or data contained in the block recorded in the corresponding column of the memory section M, namely an item of data relating to the validity of this block and an item of data relating to the altered or unaltered status of at least one of the items of information contained in this block. These two items of data are represented by respective ones of two additional bits V and M which are either in the 0 state (block invalid or block not updated) or in the 1 state (block valid or block altered).

With particular reference to Fig. 2, a description will now be given of the process of writing an item of data Y, which is initiated by a a write instruction E coming from processor P, for example.

As a first step, it is necessary to find whether or not this item of data y is present in the mask C, associated with processor P,. If it is, if is found whether the item of data Y is an item which has already been updated, in which case it is unique and can be replaced by the new updated item of data Y transmitted by processor P,. If the item of information Y Y originally present in mask C, is not an altered item of information, it is necessary to find whether it is present in one or more of the neighbouring masks C2, C3, . . Cn. If this is not the case, the updated item of data Y transmitted by processor P, can be written in its mask C, in place of the original item of data Y, at the same time as the M bit in the column of the index R which has enabled the presence of the original item of data Y to be identified is set to 1. In other words, the new item of data Y is now considered as an updated item of data which is unique.

If on the other hand the initial item of data Y is present in at least one of the neighbouring masks, once the item of data Y has been updated as above in the mask C, associated with processor P1, it is necessary to invalidate the original items of data Y present in the neighbouring mask or masks. For this, it is merely necessary to set to zero the V bit in the column in the index R which enabled this original item of data Y to be identified in the neighbouring mask or masks.

In cases where the item of data Y to be written is not originally present in the mask C, associated with the processor P, making the request, it is queried whether the write instruction is a partial write instruction (only part of a block is to be modified) or a total write instruction (the whole of the block is to be modified).

In cases where the write instruction is a total write instruction, in the knowledge that the item of data Y is not present in mask C, but that in any case it will be written in mask C1, it is first of all checked that there is in fact space available in mask C,. For this, it is found whether there is an invalid block (V bit at 0) among the four columns on the four levels of the index R which are identified by the least significant bits of the main memory address of data item Y. If one of the four blocks is invalid, data item Y is written in the corresponding block in the memory section M of mask C,.If the item of data Y to be written is equivalent to the updating of an original item of data Y present in one or more of the masks neighbouring on mask C1, the items of data concerned are invalidated by setting to O the V bit in the column of the index which identifies the original item of data. The item of information Y has to be unique since it corresponds either to the updating of an item of data already altered in a mask, or to the updating of an unaltered item of data in the central memory and it is for this reason that the M and V bits in the column of the index R of the mask C, which receives the item of information Y are set to the 1 state.

In cases where all four blocks in the index R of mask C, have their V bit at 1, that is to say where all the blocks are valid, it is necessary to make space without losing the information contained in these blocks. Thus, the oldest block (that is to say the least recently used block) is found and this block is then transferred to the central memory before being replaced by the item of information Y to be written. As before, if the item of data Y to be written is equivalent to the updating of an item of data present in another mask this latter item of data is invalidated.

In cases where the write instruction is a partial write instruction, it is found whether the item of information Y is equivalent to the updating of an item of data contained in one or more masks other than mask C,. If not, the item of information Y is simply written in the central memory. If it is, it is checked whether the item of information Y to be written corresponds to an already updated item of data (M bit at 1). If this is the case, the item of information Y is written in the mask Ci in which the original item of information is situated, which item of information is unique because it corresponds to an item of data already altered.If the item of information Y corresponds to the updating of an item of data which has not already been updated, it is written in the central memory after the invalidation of the original item of information in the mask Cj in which is situated the item of data to be updated.

With reference in particular to Fig. 3, a description will now be given of the process of reading an item of information Y present in the memory assembly of the processing system which operates in particular by multiprocessing. Let it be assumed that processor P, issues an instruction for an item of data Y to be read. As a first step, it is found whether this item of data Y is present in the mask C, of the processor P, making the request, in which case the item of data Y is transmitted from mask C, to processor P,. In the reverse case, it is found whether the item of data Y is present in one of the neighbouring masks C2 to Cn. If this is not the case, item of data Y is situated in the main memory and will therefore be transferred to the processor P, making the request while at the same time being written in the mask C, belonging to processor P,.However, before the item of data Y from the central memory is written in mask C1, it is necessary to check that there is in fact space available in mask C,. For this, the procedure is identical to that described above in relation to the writing of an item of data in a mask, that is to say it is found whether one of the columns on the four levels of the index R which are identified by the least siginificant bits of the address of data item Y has its V bit at 0, in which case data item Y can be written in the block of the memory section M of the mask C, identified by the said column. If none of the four columns has its V bit at 0, it is necessary to make space in mask C1. For this, the item of information least recently used is found and is then transferred to the central memory before the data item Y from the central memory is written in mask C,.In the column of the index which identifies this data item Y in mask C1, the M bit is set to O (because the item of data in question is not an updated item) and the V bit is set to 1 (to idicate that the data item is valid).

In cases where the item of data Y to be read is situated in a neighbouring mask Cj, it is necessary to discover whether or not it is an updated item of data. If not, data item Y is read from the central memory as before.

When transmitted to processor Pt, this item of data is also written in mask C1, possibly after space has been made in the latter.

In cases where the item of data Y to be read is present in a mask neighbouring on the mask C, belonging to the processor P, making the request, the item of data will be read from the mask C, in question, and will be transferred to processor P, and simultaneously written in mask C1, possibly after space has been made in the latter. In the flow chart, the variable x is set to 1 enables a switch to be made either to the central memory as above or to mask Cj in the present case. Once written in mask C1, the item of data Y must be considered as valid and updated, that is to say the M and V bits in the column of the index R which identifies this item of data are set to the 1 state.The original item of data Y present in mask Cj on the other hand is invalidated by setting the V bit to O in the column of the index which identifies this item of data.

Thus, with a scheme of this nature for writing and reading data, an updated item of data can be situated at only one point in the memory facility fo the system, while a nonupdated item of data can be found at a number of points and in this case may be identical with the item of data recorded in the central memory.

With particular reference now to Fig. 4, a more detailed description will be given of the various reading and writing operations which take place at a mask.

Referring to Fig. 4, the structure of a mask C is shown in simplified form. As explained above, the mask comprises a memory section M containing the information or data proper which comes originally from the central memory MC of the system, and an index section R which enables the data in the memory section M to be identified.

The memory section M is divided into four levels 0, 1, 2, 3 each containing n columns holding a block of information B. The index R is likewise divided into four levels 0, 1, 2, 3 corresponding to respective ones of the four levels of the memory section M, each level being divided into p columns which each hold a block of information b which identifies a block of information B on the corresponding level of the memory section M.

The columns of the index R are initialised using addresses provided by one of the processors which come via the address lines either from the bus AD between the processor and its mask or from the main connecting bus BS.

To be more exact, if it is assumed that mask C, is shown in Fig. 4, the address lines 10 from bus AD convey address data from the processor P, associated with mask C, to the index section R of mask C,. In actual fact, a multiplexer 11, which is divided into two sections 1 1 a, 1 1 b each formed by at least one register, is interposed between the address lines 10 and the index section R. Section 1 a of the multiplexer 11 is intended for example to store the most significant bits of the address transmitted by the processor, whereas section 11 b of the multiplexer 1 1 records the least significant bits of the same address. Section 1 b of the multiplexer is used to identify a predetermined column containing a block of information b on the four levels 0, 1, 2, 3 of the index R.The most significant bits of the address contained in section 1 a of the multiplexer 11 are transmitted simultaneously to the inputs of four comparators 12. The other inputs of the comparators 12 receive respective ones of the blocks b respectively accommodated on the four levels 0, 1, 2, 3 of the index R, which blocks are identified by the least significant bits of the address. The outputs from the comparators 12 are transmitted to a multiplexer 13.

The multiplexer 11 is also connected to address lines 15 from bus BS, which lines are intended to transmit addresses to the mask which do not originate from the processor associated with this mask.

To each block of information b on the four levels of the index section R of a mask are added two items of data, namely two bits V and M which can assume either the 0 state or the 1 state. These two bits respectively enable the validity of the block b and the updated or non-updated status of the same block to be identified. The state of these two bits is the responsibility of a control unit 16 associated with the mask, the state of the bits being transmitted, for any block of information selected, to the multiplexer 13. At its output, multiplexer 13 is connected to a unit 17 for controlling the index section R of the mask.

A multiplexer 21 which is connected to both address lines 10 and address lines 15, enables a column on each level of the memory section M of the mask to be identified.

The contents of all the columns on levels 0, 1, 2, 3 of the memory section M can be transferred to a multiplexer 22 and from there can be transmitted either by a register 23 to the data lines 24 from bus DT to enable data to be transferred between the mask and its processor, or by registers 25 to the data lines 26 from the main bus BS to enable data to be transferred between the masks and the central memory.

At its input, the memory section M of the mask may receive, via a multiplexer 27, data coming either from the data lines 24 (from a processor) or from data lines 26 (from the central memory or a neighbouring mask).

A seniority memory 30 stores items of information which enable it to be determined which of the four blocks in the same four columns corresponding to respective ones of the four levels 0, 1, 2, 3 of the index is the oldest, so that space can be made in the mask by transferring the oldest block to the central memory. The seniority memory 30 has the same number of columns as the index section R of the mask, a column of this memory 30 being identified by an address (least significant digits) coming either from the address lines 15, or from the address lines 10 from bus AD via an interposed multiplexer 31.

From the outputs of the four levels 0, 1, 2, 3 of the index R of the mask, the four blocks in the same column on the four levels are transmitted to a multiplexer 32. The latter is connected at its output to a register 33 whose output is connected on the one hand to the address lines 15 from bus BS, in particular to enable the address of an item of data to be written in the central memory to be transferred, and on the other hand to a comparator 34 whose other input is connected to the address lines 15 from bus BS. This comparator makes it possible to discover in particular whether an item of data is in course of transfer, that is to say is stored in the above registers 25. Comparator 34 is connected at its output to a unit 35 for controlling the mask.

Still with reference to Fig. 4, let it be assumed that the processor P, wishes to write an item of data Y in associated mask C,.

The address of the item of data Y, which is supplied by processor P1, is transmitted to multiplexer 11 via the address lines 10. The most significant bits of this address are stored in a register in section 11 a of multiplexer 11, while the least significant bits are stored in a register in section 11 b of the multiplexer. The least significant bits enable a column to be identified on each level of the index R of the mask C, in which a block of information b is recorded.

The most significant bits are transmitted to the four comparators 12, the purpose of which is to compare these bits simultaneously with the items of information contained in the blocks b, which are likewise transmitted to the four comparators.

Let it be assumed that the four comparisons all produce a negative result, that is to say that none of the four blocks B in the memory section M of mask C, which are respectively associated with the four blocks b in the index R of mask C, contains the item of data Y.

Consequently, this item of data is not situated in the mask of the processor making the request.

Processor P, therefore issues a write instruction via the main bus BS and activates the address lines 15 to the neighbouring masks, which will respond in turn.

Let it now be assumed that one of the four comparisons produces a positive result, that is to say the item of data Y is already situated in the memory section M of mask C1. Under these conditions, the item of data Y is written in place of the associated block B in the memory section M of the mask. For this, the item of data Y is transmitted to mask C, via the data lines 24 and the multiplexer 27 before being directed to the selected block B on one of the four levels of the memory section M of the mask. The block B in the memory section M of mask C, has been identified by means of the multiplexer 21 connected to the address lines 1 0 (the least significant bits of the address of data item Y) and by the one of the comparators 12 which has responded positively, which enables the appropriate level 0, 1, 2 or 3 of the memory section M of mask C, to be identified.

In cases where the item of data Y to be written is situated in a neighbouring mask, the item of data Y is still written in the mask associated with the processor making the request, after it has first been checked that there is room. For this, it is necessary to consider the state of the V and M bits of the blocks b in the columns on each of the levels 0, 1, 2 and 3 of the index R which are identified by the least significant bits of the address of data item Y. If one of the V bits is transmitted by multiplexer 13 is in the binary 0 state, the associated block b is thus invalid and the data item Y can be written in the block B associated with this block b. If none of the V bits is in the 0 state, the four blocks are associated with respective ones of four items of updated information and it is necessary to make space in the mask to allow the data item Y to be written.

For this purpose the seniority memory 30 is interrogated, this memory being addressed by the least significant bits of the address of data item Y, which are transmitted by the address lines 10 via multiplexer 31. In a known fashion, the oldest block b on the four levels 0, 1, 2, 3 of the index is identified and then the information contained in the corresponding block B in the memory section M is transmitted to the central memory, via multiplexer 22, registers 25, and the data lines 26 from bus BS which connect the central memory to the various masks.

However, it is necessary to find the memory address of this item of data again before transmitting it. This memory address is present in register 33 and comes from section 11 b of multiplexer 11 in the case of the least significant bits and from multiplexer 32 in the case of the most significant bits. This address is then transmitted to the address lines 15 from the main bus, and after this the transfer to the central memory is able to take place.

When an item of data is transferred from the central memory to a mask under the control of a processor, the latter transmits the address via the address lines 10 from the main bus BS and the item of data to be written, coming from the central memory, is transmitted to the mask via data lines 26 to arrive at multiplexer 27 before being transferred to the column on level 0, 1, 2 or 3 of the memory section M of the mask. This procedure so applies when an item of data is transferred between two masks.

It may happen that an item of data re quested by a processor is in course of transfer and is present in registers 25. This is detected by means of comparator 34, which at all times receives the address data on the ad dress lines 15 from the main bus. When this address is equal to the address present in register 33, which corresponds to the item of data currently being processed, the processor making the request will fetch the item of data directly from registers 25.

When an item of data is to be written in a mask using the procedure described above and when this item of data is also to be transferred to the processor, this transfer is performed via the data lines 26 from the main bus BS, multiplexer 27, multiplexer 22, regis ter 23, and the data lines 24 from the main bus which run to the processor making the request.

Up to this point, what has been considered is an item of data or information correspond ing to a block, either a block b or a block B.

However, it is clear that any block may con tain a plurality of items of information, this depending upon the nature of the system envisaged. Thus, in the case of reading, the entire block selected on one of the levels of the memory section M of the mask is read and then only the relevant item of information from this block is processed, which is in particular the function of the multiplexer 22, which will first of all authorise the transmis sion of the requested part of the block.

A reading and writing scheme of this kind also enables the number of dialogues between the central memory and the masks to be reduced, which means that memory access conflicts are reduced. The invention is applica ble to any multiprocessing system of the above type, whatever the number of proces sors.

The invention is not of course in any way restricted to the embodiment described and illustrated, which is given merely by way of example. In particular, it covers all means which form technical equivalents of the means described, as well as combinations of these if 'he combinations are made within the scope of the invention and are employed in the context of the following claims.

Claims (15)

1. Method of ensuring the coherence of data or information in a data processing sys tem which operates in particular by multipro cessing, which data or information is recorded in a memory assembly formed by at least one central memory and at least two masks associ ated with respective ones of two processors belonging to the system, characterised in that it consists, when one of the processors be longing to the system alters or updates at least one of the recorded items of information in storing this updated item of information at a single location in the memory assembly, in invalidating the original, non-updated item of information in the masks in which it may also be present, and in keeping any updated item of information unique in the memory assembly of the system.

2. Method according to claim 1, characterised in that consists, when a processor wishes to write an item of information, in writing this item of information in the mask associated with the said processor.

3. Method according to claim 2, characterised in that it consists, when the item of information is an item of information updated from an item of information present in the mask or an original item of information, in replacing the said original information by the updated information.

4. Method according to claim 2 or 3, characterised in that it consists, when the said item of information is an item of information updated from an item of information present in masks neighbouring on the mask of the said processor making the request, in invalidating the said item of information present in the said other masks.

5. Method according to claim 2i characterised in that it consists, when so as to allow the said item of information to be written, the selected address in the mask of the said processor making the request corresponds to a memory location already containing updated information, in finding the item of information least recently used in the mask of the said requesting processor and in transferring this item of information to the central memory of the system.

6. Method according to claim 1, characterised in that it consists, when a processor belonging to the system requests the partial updating of an item of information present in a neighbouring mask which has already been altered, in updating the said information in the said other mask without transferring it to the mask of the processor making the request.

7. Method according to claim 1, characterised in that it consists, when a processor belonging to the system requests the partial updating either of an item of information present in a neighbouring mask which has not previously been updated or of an item of information not present in a mask neighbouring on the mask of the processor making the request, in updating the said item of information in the main memory of the system in which the said item of information is recorded.

8. Method according to claim 1, characterised in that it consists, when a processor requests the transfer to its associated mask of an updated item of information present in a neighbouring mask, in transferring the said updated item of information from the said other mask to the mask of the processor making the request, and in invalidating the said item of information in the said other mask.

9. Method according to claim 8, characterised in that it consists, when a processor requests the transfer to its associated mask of an updated item of information present in a neighbouring mask and when the address selected in the mask of the processor making the request is a memory location already containing an updated item of information, in finding in the mask of the processor making the request the least recently used item of information and in transferring it to the central memory of the system before performing the transfer proper.

10. Automatic data processing system which operates in particular by multiprocessing, of the kind comprising a memory addembly formed by at least one central memory, at least two masks associated with respective ones of two processors belonging to the system, at least one main connecting bus between the memory assembly and the processors, and in which each mask is for example divided into m levels containing n columns, each level being associated with an index having m levels and p columns, m being a multiple of p, a comparison circuit being associated with each level of the index, characterised in that associated with each column of the said index is a memory in which are recorded two items of data which relate to the items of information identified by the said column of the index and which respectively correspond to an item of data on the validity on the said item of information and an item of data on the modified or unmodified status of the said items of information.

11. System according to claim 10, characterised in that the above mentioned items of data correspond to respective ones of two binary bits whose state is O or 1.

12. System according to claim 10 or 11, characterised in that any transfer of information in the said memory assembly and between this assembly and the central memory takes place via the said single main bus.

13. A data processing system which operates in particular by multiprocessing, characterised in that coherence between items of information is ensured by the method defined in any of claims 1 to 9.

14. Method of ensuring the coherence of data substantially as hereinbefore described with reference to the accompanying drawings.

15. Data processing system substantially as hereinbefore described with reference to the accompanying drawings.