GB2025175A

GB2025175A - Digital generation of waveforms controlling inverters

Info

Publication number: GB2025175A
Application number: GB7922230A
Authority: GB
Original assignee: Siemens AG
Current assignee: Siemens AG
Priority date: 1978-07-06
Filing date: 1979-06-26
Publication date: 1980-01-16
Also published as: GB2025175B; BR7904237A; ATA465779A; BE877438A; FR2430691B1; US4290108A; JPS5532494A; SE7905636L; DE2829793A1; CA1124869A; FR2430691A1; IT7923898A0; AT369208B; IT1165121B

Description

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SPECIFICATION A control unit for a converter

5 The invention relates to a control unit for a converter with a circuit arrangement for generation of periodic control signal with fixed pulse pattern.

Together with the conception of the control 10 procedure for the converter, attention must be paid to making the technical realisation of such a device as simple as possible. With known control procedure, the control signal is produced by the comparison of voltages. This 15 necessitates the balancing of the components used such as the amplifier, reference voltage generator and comparator as well as providing drift compensation.

Known control procedures for converters 20 are usually phase angle controls and pulse width controls. With a pulse width control, the regulation speed is large in comparison with a phase angle control and the harmonic content greatly reduced. The pulse frequency can be 25 selected to be sufficiently high that the harmonic content of the current remains small even with a small inductance in the load circuit. The harmonic spectrum can be influenced with regard to a small filter input. In 30 this way, the weight and volume of the current converter are reduced and its degree of efficiency increased. The higher the pulse frequency selected, the more accurate the required nature of the output voltage. An upper 35 limit to the pulse frequency is given by the operating time of the converter valves and its operating deficit.

Known controls for converters operate as phase-angle controls with a constant pulse 40 frequency and variable switch-on time or as phase-angle control with variable pulse frequency and either a constant switch-on time or constant cut-out time (Heumman/Stumpe, "Thyristors", 1974, Pages 167, 168) or 45 thirdly according to procedure of pulse width modulation (BBC News, 1966 Pages 44 to 52).

With pulse width modulation, the points of intersection of a sinusoidal voltage with a 50 triangular voltage give the switch-over points of the control voltage as a pulse width modulated voltage with two voltage levels. The ratio of the amplitude of the sinusoidal voltage to the amplitude of the triangular voltage deter-55 mines the number of switch-over points.

By a further known process for the production of a pulse width modulated control voltage for a converter, a sinusoidal voltage is compared with a triangular voltage which is 60 composed of a main triangular voltage and a secondary triangular voltage. (DE-OS 1 9 45 960).

By a further known process for the production of a control signal for a converter, a 65 sinusoidal signal with constant amplitude is compared with a number of DC voltages symmetrical to the zero line (DE-PS 21 12 186, US-PS 38 20 003). For the control of the amplitude of the output voltage of the conver-70 ter the DC voltages are changed. This procedure is particularly suitable for three-phase systems.

With the above procedure for the production of control signals for the converter, in 75 particular with the foregoing pulse control procedure, special circuits are necessary. In all cases note must be taken of the production feasibility of the control procedures. The wave shapes, frequencies and amplitudes of the 80 voltages to be compared with each other,

must be exactly balanced. The built-up unit should not show any drift.

The function underlying the invention is to provide a control unit for converter, which 85 universally produces the control signals for different converters and uses and by which the pulse pattern of the control signals can be determined without requiring the use of reference voltage generators and comparators. 90 This problem is solved by the invention through the following characteristics:

a) numbers are stored in a memory, which describe the position of the switching edges of the control signal in one period subdivided

95 into a number of increments or part periods of the input or output AC voltage of the converter;

b) an adressing input of the memory is connected to an adressing unit, which produces

100 adresses co-ordinated with the pulse pattern of the control signal and the switching edges within the pulse pattern;

c) the digital output of the memory is connected with a first comparator input of a

105 digital comparator, having a second comparator input connected with a counter which counts the impulses of a timing oscillator, whereby each timed impulse is co-ordinated to the accuracy of one increment;

1 10 d) with each correlation of the number selected from the memory with a number produced from the counter, the output signal of the comparator initiates a pluse stage whose output signal provides control signal and 115 switches and addressing unit over to the provision of the next address.

With such a control unit, a period or part period of the control signal is divided up into the largest possible number of increments. 1 20 The temporal result of the switching edges of the control signal is stored in digital form as a number in a memory, for example in a permanent memory. The timely recall of the number describing the switching edges for a definite 125 pulse pattern is achieved through comparison of the numbers of the counter, operating with constant or variable frequency, with the selected numbers from the memory. The frequency of the counter stays mostly in a fixed 1 30 relation to the input or output voltage of the

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converter and amounts to, for example, a submultiple of the converter frequency. With a sufficiently high counter frequency, this is however not absolutely necessary. The num-5 bers are entered in the memory in storage sites, which are selected by the addressing unit. While the counter counts, the number selected from the memory is delayed until correlation is achieved with a number of the 10 counter. With each correlation of a number and a counter number the addressing unit addresses the storage site of the next switching edge of the relevant pulse pattern. The selected number from this storage site is de-15 layed again until renewed correlation with a counter number takes place.

With each correlation of a number and a counter number the impulse stage switches from '0' to '1' or from '1' to '0'. The ouput 20 signal of the impulse stage is the required pulse width modulated control signal.

Such a control unit enables the production of control signals for converters, which can be given completely independently of the use of 25 reference voltage generators and comparators. The task of the control signal can, for instance, be effected with regard to a required harmonic spectrum of the output voltage by using inverter control equipment or with re-30 gard to a required reaction on the input voltage by using rectifier control equipment. A control unit according to the invention can be used in a circuit technically invariable form for different converter types and converter 35 circuits. If need be, the memory must merely be programmed with the numbers for the switching edges of the pulse pattern of the required control signal. In normal usage one would insert beforehand the programmed per-40 manent memory, for instance a PROM in the control unit. It is however also possible to design the memory as a write-read-memory and to programme through a calculator,

which, during converter operation, determines 45 the actual most favourable pulse pattern from the measured operating conditions.

It is, in principle, possible to store the switching edges of the control signal for a whole period. In this case the highest possible 50 counting rate of the counter corresponds to the combined number of increments of a period.

For space economy, it is advantageous to choose the highest possible counting rate of 55 the counter in such a way that is corresponds to a part period of the control signal, preferably a quarter period. A first run of the counter provides the switching edges of the pulse pattern for the first quarter period of the 60 control signal. The second quarter period of the control signal is reached with the reverse counting counter through call in of the same switching edges. In the third quarter period of the control signal, the counter runs forward 65 again and in the fourth quarter period.

backwards. If a control signal with two active levels is required, then the output signal of the pulse stage can be inverted in the second half period of the control signal. 70 The wave shape and the amplitude of output voltage or the reaction on the output voltage of a converter controlled thus, will be determined through the pulse pattern of the control signal, also through the variation of 75 the switching edge with time. If an inverter is supplied as a converter, then its output voltage can be sinusoidal, triangular or trapezoidal. On the whole, one will actually prescribe a definite wave shape for a given use. In 80 general, with the use of inverters the ouput voltage of the inverter should be variable with regard to its amplitude, or an amplitude constant with regard to its ouput voltage even with alterations of the input DC voltage. With 85 the use of rectifiers, a constant output DC voltage with variable AC input voltage or a variable DC output voltage is required. In addition to this, a number of pulse patterns can be stored in the memory, by which the 90 switching edges of a control signal are selected, so that the output voltage of the converter is adjustable in stages. For example, by using 128 pulse patterns, the amplitude of the output voltage of the converter can be 95 altered incrementally in 128 stages between 0% and 100%.

With a unit according to the invention, it is however also possible to change the wave shape of the ouput voltage of an inverter 100 depending on its modulation. For example, by using converter units, pulse patterns can be selected in such a way that the converter produces a trapezoidal output voltage in a first modulation range, a sinusoidal output voltage 105 in a second modulation range and a triangular AC voltage in a third modulation range.

The actual largest possible number of stored pulse patterns and the number of switching edges per pulse patter is determined by the 110 storage capacity of the memory used. For example with a IK X 8 bit permanent memory, in all 64 pulse patterns of control signals are stored, which in each quarter period, can exhibit between 8 and 15 switching edges. 115 With a memory with an equivalent storage capacity, 128 pulse patterns of control patterns can be stored which actually contain between 4 and 7 switching edges per quarter period. If, in the same storage capacity, less 120 than 4 switching edges per quarter period are necessary, then even 256 pulse patterns can be recorded. The number of pulse patterns and the number of switching edges within each pulse pattern are thus established, while 125 considering the storage of the permanent memory, whereby one is variable with regard to the pulse frequency and number width. The number of pulse patterns determines the control possibilities of the output voltage of the 130 converter. The number of the changeover

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edges within a pulse pattern determines the harmonic content of the output voltage of the inverter and with it also the requisite filter input.

5 The accuracy of the temporal position of the switching edges of the control signal is determined by the number of increments into which a period or part period of the control signal is subdivided. The number of incre-10 ments determines, on the other hand, the number width of the numbers stored in the memory. By using 8 bits wide numbers a quarter period can be subdivided into 256 increments. The switching edges can therefore 15 be accurately established on the 256th part of a quarter period of the control signal. This time increment corresponds to an angle of 0.351° .

With a unit of the invention, the interfer-20 ence resistance is improved by using digital technology. Offset compensation, drift compensation and other adustments are not applicable. A particular advantage is the flexibility with the production of control signals for the 25 triggering of converters.

The pulse patterns are not fixed through a circuit assembly, rather the required frequency spectrum of the output voltage or the reaction on the input voltage of the converter can be 30 established, from this the required pulse pattern determined and the switching edges of same determined pulse pattern stored in the memory.

the number of the switching edges, their 35 temporal position and the number of the pulse patterns can be determined by considering the required frequency spectrum, the filter assembly and other parameters.

In particular, the invention also renders pos-40 sible the presentation of pulse patterns which allows operation with unconventional filters. One can also submit pulse patterns, which would not be realizable by analogue means or would only be realisable with a large circuit 45 Furthermore it is possible to let the pulse pattern calculate continuously through a micro-computer.

A particularly simple and therefore favoured addressing form is achieved in this way as a 50 result of a further development of the invention, so that the addresses developed from the addressing unit are actually assembled from a first and second sub address, whereby the first sub address is developed from a trigger 55 counter with correlation of number and counter number and the second sub address developed from a shift register which transmits cyclically a signal determining the modulation of the converter. The cyclic transmission of 60 the signal determining the converter is achieved, for example, at the beginning of each quarter period.

The signal determining the modulation of the converter can be supplied directly to the 65 shift register by a setting up facility or a digital control facility. By using analogue setting up facilities, for example, by preset potentiometers, or analogue control facilities, the input of the shift register can be connected 70 via an analogue-digital-converter with an analogue setting up facility or a control facility.

Another alternative of the address creation is that the addressing unit be produced through a microcomputer which determines 75 the address from digitally given regulator signals. This feature is suited in particular to the extensive controls of converter units.

A unit of the invention can be set up to control converters with fixed, constantly vari-80 able or incrementally variable frequency. For the production of a periodic control signal with variable frequency, the counter can by timed with variable frequency. The variable frequency is, for example, produced from a 85 voltage-frequency-converter. For a periodic control system with a frequency variable by degrees, a continous timing oscillator with constant frequency can be used, whereby a controllable frequency divider is connected in 90 series to the counter.

For the particularly high level control of a converter, the counter can be synchronised by an external synchronising signal.

With parallel operation of several conver-95 ters, the synchronising signal of a common synchronising oscillator can be used.

Specific examples of the invention will be described in detail with reference to the drawing which show as follows:—

100 Figure 1, a basic diagram of a control unit for the production of a pulse width modulated control signal for use with an inverter.

Figure 2, a diagram with a pulse width modulated control signal and the accompany-105 ing output voltage of an inverter.

Figure 3, the programming and addressing of a permanent memory.

Figure 4, a block diagram of a control unit for an inverter.

110 Figure 5, a controlled converter of a control unit according to Fig. 4.

Figure 6, a block diagram of control unit for the production of a 3 phase pulse width modulated control signal for a 3 phase inver-115 ter

Figure 7, a block diagram of a further type of control unit for the development of a 3 phase pulse width modulated control signal for a 3 phase inverter.

1 20 Figure 8, a further type of control unit for the production of 3 phase pulse width modulated control signal for 3 phase inverter.

Figure 9, a basic diagram of a 3 phase bridge inverter.

125 Figure 10, a diagram of the current duration of a rectifier of the bridge inverter of Fig. 10.

Figure 11, a sum pulse pattern without taking into account the commutating proc-130 esses for the triggering of the bridge inverter

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seen in Fig. 9, with a simple control signal, which only shows one pulse in each half period.

Figure 12, a sum pulse pattern taking into 5 account the commutating processes for the triggering of the bridge inverter seen in Fig. 9, with a simple control signal, which only show one pulse in each half period.

Figure 13, a control unit for the establish-10 ment of a 3 phase pulse width modulated signal by using sum patterns.

Fig. 1 shows the basic assembly of a control unit for the production of a periodic preferably pulse width modulated control sig-15 nal Us. The circuit contains a memory 1, for example a PROM, as a permanent memory, which has a 10-bit wide address input 2 and an 8-bit wide numeral output 3. In memory 1 the switching edges of the control signal Us 20 are stored in the form of numbers whose production method is explained by Fig. 2. The timely recall of the switching edges is achieved through a corresponding address which is described in Fig. 3. 25 The addressing input 2 of the memory 1 is connected with an addressing unit 10, which gives out the addresses of the switching edges of the desired control signal Us. If the modulation of the converter has to be vari-30 able, then the circuit of the invention must produce control signals with different pulse patterns. This means that the addressing unit 10 is controlled ndt only with regard to a pulse pattern co-ordinated to a definite modu-35 lation of the converter from a number of pulse patterns, but also with regard to the sequence of the switching edges within this pulse pattern. The pulse pattern co-ordinated to a fixed modulation of the converter is preselected via 40 a control voltage on pulse pattern-control input 11, which for instance, is connected with a control facility 13. This temporal sequence of the switching edges within a pulse pattern is determined through control commands on a 45 switching edges—control input 12.

The output 3 of the memory 1 is connected with the first comparator input A of a comparator 4, whose second comparator input B is connected with the 8-bit wide output of the 50 counter 5. The counter 5 counts the impulses of a timing oscillator 6. When only a modification to the amplitude of the output voltage converter is necessary, the timing oscillator 6 operates with constant pulse frequency. Addi-55 tionally, when the frequency of the output voltage of the converter has to be influenced, then a timing oscillator with variable pulse frequency is used , for example a voltage-frequency-converter. With the correlation of 60 the number on the comparator input A with the counter number on the comparator input B, the comparator 4,on its output side, produces a signal which is transformed by an Impulse stage 7 to a control impulse for a flip-65 flop 8. The flip-flop 8 switches with each control impulse to its dynamic input . On output 9 of the flip-flop the control signal Us appears. The control impulse, established from the impulse stage 7 with each correlation of numbers and counter number (A = B), controls the addressing unit 10 through the switching edges-control input, in such a way, that this switches the address of the next switching edge inside the pulse pattern, fixed through the control voltage on the pulse pattern control input 11, to the addressing input 2 of the memory.

The control unit will now be described by way of particular examples. As converters, inverters are used, which transform a DC input voltage to a sinusoidal AC output voltage with a constant frequency.

Fig. 2 shows, over a quarter period, the shape of the sinusoidal AC output voltage Uw of an inverter and the shape of the accompanying pulse width modulated control signal Us. The quarter period is sub-divided into 256 increments. The numbers of the switching edges of the control voltage Us are recorded on the time axis t. The numbers co-ordinated to the switching edges are stored in memory 1 and can be called in through accompanying addresses. With a different modulation of the inverter or another wave shape of its output voltage, a control signal with another pulse pattern is necessary. The switching edges of this other pulse pattern are likewise stored in the memory and can be recalled through other addresses. It is advisable to assemble each address from two sub addresses. One sub address shows the desired pulse pattern.

The other sub address shows the switching edges within the relevant pulse pattern. By assuming that, with the example described, the pulse pattern should not have more than 8 switching edges per quarter period and that the output voltage of the inverter should be variable in 128 stages, 128 pulse patterns are necessary each with 8 switching edges, which are stored in memory 1. In addition, 1024 numbers are necessary, which provide 1024 storage sites with 8-bit width and which are addressable over 1024 addresses.

Fig. 3 shows in table form the addresses and the accompanying numbers as storage capacity for 3 shift pulse patterns. The addresses and numbers are given in binary form and, for easier readability, in decimal form as well. The upper pulse pattern is co-ordinated, for instance, to the minimum output voltage of the inverter. The middle pulse pattern is coordinated to the output voltage of the inverter shown in Fig. 2. The lower pulse pattern is, for example, co-ordinated to the maximum output voltage of the inverter.

The first slot shows the addresses sub divided into two sub addresses, which are produced from the addressing device and with which the address lines AO to A9 of the addressing input 2 of memory 1 are occupied.

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The address line AO to A2 are occupied by a 3-bit wide first sub address, which runs through the binary numbers 000 to 111 (decimal 0—7) in each pulse pattern. The 5 first sub address shows the switching edges within a pulse pattern. The address lines A3 to A9 are occupied by a second sub address, which shows the relevant pulse pattern.

To the right, next to the addresses, the 10 accompanying storage capacities are given, which actually name the increment at which a switching edge should occur in the control signal. As each quarter period of the control signal is sub divided into 256 increments, 15 each increment corresponds to a binary number between 0000 0000 and 1111 1111 (decimal 0-255). With the programming of the memory, the time interval fixed as an increment is recorded as a binary number, on 20 which a switching edge should occur in the control signal. The numbers are stored in a rising sequence. First the number is stored, with which the control signal from the level for the logic state '0' changes to the level for 25 the logic state '1' or from level '1' to the level '0'. With the second number the control signal turns back to its original state.

Fig. 4 shows a block diagram of a control circuit for triggering of the inverter seen in 30 Fig. 5 according to the examples described in Figs. 1 & 2 of a pulse width modulated control signal. Similar or similar acting components or assemblies are provided with the same symbols as in the basic diagram of Fig. 35 1. A 1024 X 8 bit PROM is provided as memory 1, as permanent memory. The 8-bit number occurring with corresponding address on its output is compared by comparator 4 with the 8-bit output of the counter 5 timed 40 with a constant pulse frequency. With each correlation the permanent memory 1 is further addressed through the pulse stage 7 and the addressing unit 10 and the flip-flop 8 is triggered. The addressing of the permanent 45 memory 1 is binary through its 10-bit addressing input 2 with the address lines AO to A9. The total circuit 35 is controlled through a central control counter 18, which is designed as a 12-bit counter with outputs QO to 50 Q11. The central control counter 18 is timed by an oscillator 17 with a constant frequency. The counter output Q1 times the counter 5, whose counter numbers are compared with the numbers selected from the memory 1. 55 The connection lines of the further outputs of the central control counter 18 with the corresponding components are not plotted, in order to maintain the clarity of the diagram. Instead the markings of the counter outputs of the 60 control counter 18 on the inputs of the relevant components are put in brackets. Likewise, the circuits of a time raster are not represented as it is a standard one with digital circuits.

65 The addressing unit 10 contains a further counter 14, a shift register 15 and an analo-gue-digital-converter 16 in the circuit shown. The analogue input of the analogue-digital-converter 16 is the pulse pattern control input 70 11 which is connected with the control equipment 13 of the inverter which, for example, is designed for voltage regulation.

The analogue-digital-converter 16 converts the regulator voltage occuring on the pulse 75 pattern control input 11 to digital form, which the pulse patterns, co-ordinated to the actual regulator voltage, identify. The corresponding digital forms are passed via the shift register 15 which through a release impulse (output 80 Q10) given by the central control counter 18, gives the pulse pattern symbol on the address lines A3 to A9 at the beginning of each quarter period. This corresponds to the formation of a sub address determining the pulse 85 pattern through the regulator voltage.

The address lines AO to A2 are connected with the counter 14, whose count input from the pulse generator 7 is initiated with each correlation between the counter number of the 90 counter and the number selected from the permanent memory 1. The counter 14 in the addressing unit 10 produces the further sub addresses, which the switching edges show in the pulse pattern.

95 With each correlation of counter number and number, the flip-flop 8 is triggered from the pulse generator 7, whose ouputs are connected with output logic 19. The output logic 19 is furthermore connected with the output 100 Q11 of the central control counter 18, which is occupied by a rectangular signal, which has the same period duration as the pulse width modulated control signal. The output logic 19 changes the pulse width modulated control 105 signal appearing on the outputs 8a and 8b of the flip-flop 8 to a control signal with two active levels and so occupies the control lines 28 and 29 for a direct triggering of the valve of the inverter.

110 The inputs of the NAND gate in the output logic 19 are taken up by the output supplying the inverse control signal 8 b of the flip-flop 8 and the rectangular signal of the output Q11 of the central control counter 18. The non-115 inverted input of the next NAND gate 21 is connected with the output 8 a of the flip-flop 8 supplying the control signal and the inverted input of the NAND gate 21 is connected with the output Q11. The outputs of the NAND 120 gates 20 and 21 are connected with the inputs of a further NAND gate 22. The output of NAND gate 22 is connected through an inverting stage with a first amplifier stage 26, which amplifies the control signals on a con-125 trol line 28. The output of further NAND gate 22 is connected through two series connected inverting stages 24 and 25 with a second amplifier stage 27, which amplifies the control signals on a control line 29.

1 30 The output Q10 of the central control coun-

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ter 18 has a rectangular signal with the half period duration of pulse width modulated control signal. The rectangular signal on output Q10 is thence used for the controlling of the 5 method of operation (forwards/backwards) of the counters 5 and 14. From the central control counter 18 still more rectangular impulses are discharged, which are used as inhibiting pulses start pulses and interlocking 10 pulses. The production and use of these impulses, which needs to be less for the operation of the control unit then for the functioning of an established circuit, is not described in detail and is described in the following only 1 5 in brief.

With each second counting cycle, i.e. after a forwards counting phase and a backwards counting phase, the counters 5 and 14 are set back into the '0' state. In this way an error 20 resulting from interference is ineffective at the most for a half period. At the same time the flip-flop 8 is also set to a defined output state. After each quarter period further inhibiting pulses are produced which the counters 4 and 25 14 interlock by switch-over of one pulse pattern to another pulse pattern. The flip-flop 8 is likewise interlocked to prevent a faulty response of the flip-flop during switch-over between two pulse patterns. Furthermore, the 30 central control counter 18 controls the start of the analogue-digital-converter 16. Each inhibiting impulse at the end of a quarter period of the pulse width modulated control signal releases to the shift register, for the following 35 quarter period, the input of the regulator voltage occuring on the pulse pattern control input 11 of the analogue-digital-converter 16. Immediately thereafter, the analogue-digital-converter 16 is started for a new conversion, 40 which should not last longer than a quarter period. In this way at the beginning of the next quarter period there is available a new sub address, if necessary characterised by a different pulse pattern.

45 When using circuit 35, in connection with a regulation, a lag time occurs, which actually is determined by the time which the analogue-digital-converter 16 needs to convert an analogue value occuring on the pulse pattern 50 control input 11 to a binary signal. One can take action here—as described—so that at the beginning of each quarter period of the control signal, the regulated voltage is scanned and converted to a digital value. At 55 the beginning of the next following quarter period the permanent memory 1 is addressed corresponding to the regulator voltage scanned in the preceding quarter period.

• Thereby between a change of regulated volt-60 age and the corresponding change of the trigger impulse, there develops for the inverter a lag time of a maximum of a half period of the pulse width modulated control signal. This is sufficient for numerous applications. For 65 rapid regulation a fast analogue-digital-converter can be used, which converts to a digital form the analogue value supplied to pulse pattern control input 11 during the inhibiting time of the counter between two quarter periods. The regulator output voltage scanned at the end of a quarter period is then already available at the beginning of the next quarter period as a digital value.

Circuit 35 shown in Fig. 4 can be modified for instance in such a way that a counter with 4 outputs is used (counter 14) which is switched onto 4 address lines. Then six address lines are still available for the shift register. This way the number of possible pulse patterns would be reduced to 64, but in return the number of switching edges each quarter period of the pulse width modulated control signal would be increased to 15.

Fig. 5 shows in principle the control of a bridge inverter with the circuit 35 shown in Fig. 4 and coordinated output logic 19. The pulse pattern control input 11 of control circuit 35 is connected with a control 13. The control lines 28 and 29 of the output logic are taken up by the trigger impulses for the controlled semi-conductor rectifiers of the inverter. The inverter is designed as a bridge inverter and contains, as rectifiers, the electronic switches 31-34 schematically represented. The outputs of the inverter are connected through a low-pass filter 37 with a user 38. Other filter circuits are also feasible, in particular unconventional filters. The output voltage of the inverter is detected behind filter 37 by a voltage measuring converter and supplied to the regulator input of the controller 1 3. The control input of controller 13 is connected to reference setter 40 shown as a potentiometer. The setting of a potentiometer can also be designed as a higher control or regulating facility. The rectifiers 31 and 34 of the inverter are in fact triggered simultaneously from the control line 28 and the rectifiers 32 and 33 are simultaneously triggered from line 29.

The modulation of the inverter can be effected through the output voltage of controller 13 with the aid of one of the 128 stored pulse patterns. With the control action the lag time already mentioned should be noted which lies between the instant of scanning the regulated output voltage and its input to the analogue-digital-converter in circuit 35 and the instant at which a new pulse pattern can be called in by virtue of the converted analogue value. It is stressed that the switching edges can not be continually changed as only a limited number of pulse patterns can be stored. Thus a change in the output voltage of controller 13 can only switch from one pulse pattern to another. Measures are necessary to avoid instability according to the regulator circuit.

The control unit is not only suitable for the establishment of control signals, in particular

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pulse width modulated control signals for a single phase converter, but also the production of control signals for poly-phase converters, in particular 3-phase converters. For the 5 production of poly-phase signals there are several alternatives from which one can choose the most favourable with regard to the relevant usage. In the following some of these possibilities are described which are applied in 10 the most frequent usage of a 3-phase pulse width modulated control signal.

The first possibility for the production of a 3-phase pulse width modulated control signal is to produce a single phase control signal in 15 the manner already described and to modify the first phase control signal by delaying it to give control signals for the further phases.

Fig. 6 shows schematically a block diagram of the first possibility for the production of 3-20 phase pulse width modulated control with the aid of a control unit. The single phase circuit 35 can have the same make up as shown in Figs. 1 and 4. Circuit 35 produces a pulse width modulated control signal VSR as a con-25 trol signal for the phase R of a converter.

The pulse width modulated control signal Vss for the phase S of the converter is delayed by delaying the control signal VSR for that number of time periods of counter 5 which 30 corresponds to a shift of 120°. The control signal Vss therefore represents a repetition of the control signal VSR in a temporal interval of 120°. For the development of the control signal Vss for the phase S of the converter, 35 the control signal VSR is supplied for the phase R of a shift register arrangement 41 which consists of the series connection of a 64-bit register 42, of a 64-bit shift register 43 and of a 256-bit shift register 44. The clock 40 inputs of the shift registers 42, 43 and 44 are connected with the clock input of counter 5 in circuit 35. The input of the first shift register 42 is taken by the control signal VSR for phase R of the converter.

45 The control signal VST for the phase T of the converter represents a repetition of the control signal VSR of the R phase in a temporal interval of 240°. It is achieved by delaying the control signal VSR for that number of time 50 periods of counter 5 corresponding to a shift of 240°. In addition to this the control signal VSR is supplied in analogue form to a further shift register 47 which consists of the series connection of a 64-bit shift register 48, a 55 128-bit shift registers 49 and a 512-bit shift register 50. The clock inputs of shift registers 48,49 and 50 are again connected with the clock input of counter 5 in circuit 35.

If the delays of the pulse width modulated 60 control signal VSR are fixed in the shift registers 42, 43, 44 or 48, 49, 50, then a constant delay of the control signal Vss by 1 20° or of the control signal VST by 240° can be achieved. For many applications it is how-65 ever desirable to change the phase shift within a limited range between the single control signals. In addition, with shift register 42 and shift register 48, through an external 6-bit address, it can be established how many 70 clock pulses the control signal VSR should be delayed from shift registers 42 or 48. The 6-bit addresses are established by analogue-digital-converter 45 or 51, whose analogue inputs are connected with phase regulators 46 75 or 52. In this way the phase shift between the control signal VSR for the R phase and control signal Vss for the S phase can be set in stages of 0.35° between the values 112.9° and 135.5° . The shift between the control signal 80 VSR for the R phase and VST for the phase T can in any case be set in stages between 225.9° and 248.5°.

With the arrangement shown in Fig. 6a{ period of the control signal can no longer be 85 divided into 256 increments as, with such a division, the desired phase delays of 1 20° or 240° would not correspond to a whole number of periods. One can, however, set counter 5 to zero in circuit 35 just after a counter 90 position of 254. Then 340 clock pulses corresponds to a delay of 120° and 680 clock pulses to a delay of 240° .

The circuit represented by Fig. 6 has a small circuit outlay each of the two delay units 95 consists solely of a shift register with, if necessary, adjustable delay and two shift registers with fixed delay. Of course only the pulse pattern of the control signal VSR for the phase R of the converter is determined depen-100 dent on the output voltage of controller 13. The control signals Vss and VST for the S and T phase of the converter can not be independent of phase R. A change in the output voltage of controller 1 3 is only effective with 105 a delay of 120° in addition to the lag time already described or at phase T with a delay of 240° in addition to the lag time.

A further possibility for the production of a 3-phase pulse width modulated control with 110 the control unit is to provide 3 such circuits and to procede with a fixed phase delay.

Fig. 7 shows a circuit for the production of a 3-phase control signal VSR, Vss and VST with 3 single phase circuits 35R, 35S and 35T 115 whereby the phase angle is fixed between the control signals for the phases R, S and T. The first circuit 35R whose construstion is more fully explained in Fig. 4, produces the control signal VSR for the phase R of the converter. 120 The additional circuits 35S and 35T, which are similar to 35R, produce control signals Vss and VST for the phases S and T of the converter. Circuits 35S and 35T are triggered by circuit 35 by decoders 53 and 54 to 120° 125 and 240° . The central control counters 18S and 18T in circuits 35S and 35T are started by trigger impulses from decoder 53 or 54. These decoders always produce a start impulse, if a number of counter 5R agrees with a 130 given codeword, which corresponds to the

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assigned phase shift. It is also possible to trigger the decoder with numbers from the central control counter 18R. The oscillator 17 times the three circuit arrangements 35R 35S 5 and 25T collectively. Each of the three circuits has its own memory 1R, 1S and 1T. To each of the circuits an individual controller 13R, 13S and 13T is connected in series. In this way each phase of the converter can be 10 regulated separately by respective pulse patterns.

The alternative represented in Fig. 7 for the production of a 3-phase pulse width modulated control signal with single phase regulation 15 can also be developed with an adjustable phase shift between the phases R, S and T. Fig. 8 shows such a circuit whose assembly corresponds in principle to the circuit of Fig. 7. Settings of the decoder are, however, sup-20 plied phase angle controls 55 and 57 which make possible a susceptible phase shift dependent on the output voltages of the phase regulators 56 and 58, between the phases R and S or between R and T of the converter. 25 The phase angle controls 55 and 57 produce start signals for the central control counters 18S and 18T in circuis 35S and 35T. The assembly of phase angle controls is described in detail with phase angle control 55. The 30 phase angle control has a comparator 59, a shift register 60 and an analogue-digital-converter 61 in the circuit shown. One comparator input of comparator 59 is connected in circuit 35 with one counter number output of 35 counter 5R. The second comparator input of comparator 59 is connected with the output of shift register 60. The input of shift register 60 is connected to the analogue-digital-con-verter 61 whose analogue input is supplied by 40 the output voltage of the phase regulator 56.

The analogue-digital-converter 61 changes the regulator output voltage to a digital form which is given at the beginning of each control signal period from shift register 60 to the 45 second comparator input of the comparator. This number gives the phase shift determined by the regulator 56 between the phases R and S of the converter. The correlation of this number with the counter number 50 from counter 5R starts the central control counter 18S in circuit 35S. The control signal Vss thus begins opposite the control signal VSR with a delay corresponding to a number of clock pulses from timing oscillator 17, deter-55 mined through the output voltage of regulator 56. The phase angle control 57 for phase T works in the same way.

A further way to produce a poly-phase pulse width modulated control signal is to combine 60 the pulse patterns of the individual phases with a sum pattern and to store the switching edges of the sum pattern in a permanent memory. With the positioning of the switching edges of the sum pattern each switching edge 65 is assigned to that rectifier of the converter which should be triggered at the corresponding moment by means of a rectifier selection control.

Fig. 9 shows schematically the assembly of a 3-phase bridge inverter with start and clear rectifiers n1 to n6 as well as associated reverse current diodes.

Fig. 10 shows the current carrying periods of rectifiers n1 to nB of the bridge inverter of Fig. 9 with a modulation having only one start per period.

Fig. 11 shows the switching edges of a sum pattern as a sum of the pulse patterns for the individual phases of the inverter . One recognises that with each change in the current flow of one of the rectifiers n1 to n6 of the inverter a switching edge appears in the sum pattern. With each switching edge of the sum pattern a rectifier in the inverter is triggered and a further rectifier is cleared. The required commutating pause can be produced through a suitable delay circuit. The sum pattern shows three times the switching edges as a comparable single phase pattern. It is also no longer possible to divide a period of the control signal into four periods and to determine the switching edges of each period through forward counting and backward counting of counter 5. Rather the pulse pattern must actually be stored for a whole period. From this it follows that with the production of the switching edge of a sum pattern, represented in Fig. 12, then 12 times the memory capacity is required compared to a single phase control signal.

Fig. 12 shows the switching edges of a sum pattern with regard to the commutating processes. With each individual switching edge only a specific rectifier is actually triggered. For example with the switching edge SF1, a clear impulse is given for rectifier n5 and with the switching edge SF2 a start pulse is given for the following rectifier n6. For the production of the alternative shown in Fig. 12, for the storing of the pulses for the main rectifiers as well as for the clear rectifiers of an inverter, double the memory capacity is required again in comparison to the alternative shown in Fig. 11.

Fig. 1 3 shows schematically the realisation of the memory capacity described in Fig. 11, of the switching edges of a sum pattern without taking into account any commutating processes. The circuit 35 corresponds again to the preceding examples in which, however, a recorder with a correspondingly larger storage capacity is provided. Furthermore, a rectifier selection control is provided which includes a second memory 62, which is addressed from the addressing unit 10 parallel to the permanent memory 1. NAND gates 63-68 are connected on the load side of the rectifier selection memory 62, whose inputs are actually connected with the output of the impulse stage 7 and with one of the output

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lines of the second rectifier selection memory 62. The outputs of the NAND gates 63-68 are connected with the dynamic inputs of the flip-flop stages 69 to 74. On the outputs of 5 the flip-flop stages there are pulse width modulated control signals for the controlling of the main rectifiers and clear rectifiers of the inverter.

Numbers are stored in the rectifier selection 10 memory 62 which actually contain n5 sites logic 0 and in a sixth site logic 1, for instance 010000. As soon as the addressing unit 10 gives the address assigned to a specific switching edge a number programmed for this 15 switching edge appears on the outputs of the rectifier selection memory 62, for instance 010000. The logic 1 in this numeral stands on an input of the NAND gate 67. Now as soon as there is in circuit 35 a correlation 20 between the counter number of counter 5 and the number selected from memory 1, the impulse stage 7 gives an impulse not only on the addressing unit 10 but also on the next input of the NAND gate 67. The NAND gate 25 67 is fully controlled and initiates the flip-flop stage 73. The corresponding rectifier is turned on.

Claims

30 1. Control unit for a converter with a circuit for the production of a periodic control signal with given pulse pattern, characterised by the following features:

a) in a memory numbers are stored which 35 show the position of the switching edges of the control signal in a period sub-divided into a number of increments or sub-periods of the input or output AC voltage of the converter;

b) an addressing input of the memory is 40 connected with an addressing unit, which produces addresses coordinated to the pulse pattern of the control signal and the switching edges within the pulse pattern;

c) the digital output of the memory is con-45 nected with a first comparator input of a digital comparator having a second comparator input connected with a counter which counts the pulses of a clock oscillator thus giving each timed pulse the significance of 50 one increment; and d) with each correlation of the number selected from the memory with a number produced from counter the output signal of the comparator initiates an impulse state whose

55 output signal provides the control signal and switches the addressing unit over to the provision of the next address.
2. Control unit according to claim 1, characterised by the fact that the addresses pro-60 duced by the addressing unit are actually made up by a first and second sub-address, whereby the first sub-address is established from a counter switched by each correlation of number and counter-number, and the second 65 sub-address is given by a shift register which gives cyclic signals determining the modulation of the converter.
3. Control unit according to claim 2, characterised by the fact that the input of the shift

70 register is connected with an analogue adjusting device or a control facility an analogue-digital converter.
4. Control unit according to claim 1, characterised by the fact that the addressing unit

75 is established through a micro-computer which determines the address from digital regulator signals.
5. Control unit according to claim 1, for a periodic control signal with variable frequency

80 characterised by the fact that the counter is timed with variable frequency.
6. Control unit according to claim 1, characterised by the fact that a controllable frequency divider is connected in series to the

85 counter.
7. Control unit according to claim 1, characterised by the fact that the counter is synchronised by an external synchronising signal.
8. Control unit according to claim 1 for a

90 single phase control characterised by the fact that the switching edges are stored in the memory for a £ period of the control signal and that the counter reverses its counting direction at the end of each^period of the

95 control signal.
9. Control unit according to claim 1, establishing a poly-phase control signal, characterised by the fact that the poly-phase control signal is obtained from a single phase control

100 signal through delay circuits which actually delay the single phase control signal for a number of timing cycles of the timing oscillator.
10. Control unit according to claim 1, for 105 creation of poly-phase control signals characterised by the fact that for each phase a circuit is provided for the production of a single phase control signal and that the circuits assigned to the individual phases are con-

110 nected to one another through decoders or phase angle controls.
11. Control unit according to claim 1, for the production of a poly-phase control signal, characterised by the fact that the pulse pat-

115 terns of the individual phases are combined with a sum pattern whose switching edges are stored in memory and that a rectifier selection control is provided, addressable by the addressing unit together with the memory, 1 20 which contains a further memory and logic switching elements which is actually connected with the impulse stage (7) and an output line of the memory.

1 2. Control unit for a converter, substan-125 tially in accordance with any example herein described with reference to the accompanying drawings.

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Printed for Her Majesty's Stationery Office by Burgess 8- Son (Abingdon) Ltd.—1980.

Published at The Patent Office, 25 Southampton Buildings,

London, WC2A 1AY, from which copies may be obtained.