GB202205174D0 - Systems and methods for assembling and developing an soc efficiently using templates and designer input data - Google Patents

Systems and methods for assembling and developing an soc efficiently using templates and designer input data

Info

Publication number
GB202205174D0
GB202205174D0 GBGB2205174.2A GB202205174A GB202205174D0 GB 202205174 D0 GB202205174 D0 GB 202205174D0 GB 202205174 A GB202205174 A GB 202205174A GB 202205174 D0 GB202205174 D0 GB 202205174D0
Authority
GB
United Kingdom
Prior art keywords
templates
soc
developing
assembling
efficiently
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
GBGB2205174.2A
Other versions
GB2603402A (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Efabless Corp
Original Assignee
Efabless Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US16/689,031 external-priority patent/US11270053B2/en
Application filed by Efabless Corp filed Critical Efabless Corp
Publication of GB202205174D0 publication Critical patent/GB202205174D0/en
Publication of GB2603402A publication Critical patent/GB2603402A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/337—Design optimisation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2111/00—Details relating to CAD techniques
    • G06F2111/16—Customisation or personalisation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2115/00—Details relating to the type of the circuit
    • G06F2115/08—Intellectual property [IP] blocks or IP cores
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/20—Design reuse, reusability analysis or reusability optimisation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Stored Programmes (AREA)
GB2205174.2A 2019-11-19 2020-10-26 Systems and methods for assembling and developing an soc efficiently using templates and designer input data Pending GB2603402A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US16/689,031 US11270053B2 (en) 2016-07-08 2019-11-19 Systems and methods for assembling and developing an SoC efficiently using templates and designer input data
PCT/US2020/057410 WO2021101669A1 (en) 2019-11-19 2020-10-26 Systems and methods for assembling and developing an soc efficiently using templates and designer input data

Publications (2)

Publication Number Publication Date
GB202205174D0 true GB202205174D0 (en) 2022-05-25
GB2603402A GB2603402A (en) 2022-08-03

Family

ID=75980896

Family Applications (1)

Application Number Title Priority Date Filing Date
GB2205174.2A Pending GB2603402A (en) 2019-11-19 2020-10-26 Systems and methods for assembling and developing an soc efficiently using templates and designer input data

Country Status (2)

Country Link
GB (1) GB2603402A (en)
WO (1) WO2021101669A1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023196124A1 (en) * 2022-04-08 2023-10-12 Microchip Technology Incorporated System-level design tool for selecting and confirming compatability of electrical components
CN115345106B (en) * 2022-07-14 2023-10-17 贝叶斯电子科技(绍兴)有限公司 Verilog-A model construction method, system and equipment for electronic device

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003091914A1 (en) * 2002-04-25 2003-11-06 Arc International Apparatus and method for managing integrated circuit designs
US6941527B2 (en) * 2003-04-28 2005-09-06 International Business Machines Corporation Method, system and program product for reducing a size of a configuration database utilized to configure a hardware digital system
US8726200B2 (en) * 2011-11-23 2014-05-13 Taiwan Semiconductor Manufacturing Co., Ltd. Recognition of template patterns with mask information

Also Published As

Publication number Publication date
WO2021101669A1 (en) 2021-05-27
GB2603402A (en) 2022-08-03

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