GB2016752A - Data Processing Apparatus - Google Patents

Data Processing Apparatus

Info

Publication number
GB2016752A
GB2016752A GB7904816A GB7904816A GB2016752A GB 2016752 A GB2016752 A GB 2016752A GB 7904816 A GB7904816 A GB 7904816A GB 7904816 A GB7904816 A GB 7904816A GB 2016752 A GB2016752 A GB 2016752A
Authority
GB
United Kingdom
Prior art keywords
operand
pairs
register
string
cache
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB7904816A
Other versions
GB2016752B (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US05/887,095 external-priority patent/US4189772A/en
Priority claimed from US05/887,097 external-priority patent/US4189770A/en
Priority claimed from US05/887,091 external-priority patent/US4189768A/en
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of GB2016752A publication Critical patent/GB2016752A/en
Application granted granted Critical
Publication of GB2016752B publication Critical patent/GB2016752B/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/04—Addressing variable-length words or parts of words
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0855—Overlapped cache accessing, e.g. pipeline
    • G06F12/0859—Overlapped cache accessing, e.g. pipeline with reload from main memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0877—Cache access modes
    • G06F12/0886—Variable-length word access
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30018—Bit or string instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30043—LOAD or STORE instructions; Clear instruction
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G06F9/345—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes of multiple operands or results
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3816—Instruction alignment, e.g. cache line crossing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/383—Operand prefetching

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Advance Control (AREA)

Abstract

Improved processor performance when dealing with variable field length operands is achieved by incorporating a fetching mechanism A9 which can operate in an overlapped mode with the instruction execution unit EF. Further improvement is provided by aligning operands within the fetching mechanism A13 and also, when a cache is incorporated, by incorporating a cache by-pass data transfer path by which, in the case of a cache miss, simultaneous transfer of requested items can proceed to both the cache and the operand fetch mechanism starting with the specific item sought. The operand fetch mechanism includes a plurality of operand-address pairs of registers, and a wrap-around shifter. When an instruction specifying a variable length field operand is decoded a set of empty register pairs, corresponding in number to the operand length, is formed into a string by means of pointers and the starting address of the operand is inserted into the address register of the first register pair of the string. Progressively incremented addresses are entered into the remaining register pairs, the amount of the increment being the unit of transfer. A separate mechanism A9 responds to the address to fetch the corresponding operand segments entering the same into the corresponding other registers of the pairs. A further mechanism responds to the execution unit to transfer the operand segments in string order from the register pairs to the execution unit. Where source and destination operands are specified two strings are established and where alignment is required transfer into the register pairs from storage is by way of a "by byte" wrap around shifter so that the register pairs of the string (save for the last perhaps) are packed and contain only operand segments. <IMAGE>
GB7904816A 1978-03-16 1979-02-12 Data processing apparatus Expired GB2016752B (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US05/887,095 US4189772A (en) 1978-03-16 1978-03-16 Operand alignment controls for VFL instructions
US05/887,097 US4189770A (en) 1978-03-16 1978-03-16 Cache bypass control for operand fetches
US05/887,091 US4189768A (en) 1978-03-16 1978-03-16 Operand fetch control improvement

Publications (2)

Publication Number Publication Date
GB2016752A true GB2016752A (en) 1979-09-26
GB2016752B GB2016752B (en) 1982-03-10

Family

ID=27420522

Family Applications (1)

Application Number Title Priority Date Filing Date
GB7904816A Expired GB2016752B (en) 1978-03-16 1979-02-12 Data processing apparatus

Country Status (4)

Country Link
DE (1) DE2909987A1 (en)
FR (1) FR2423822A1 (en)
GB (1) GB2016752B (en)
IT (1) IT1164980B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0075891A2 (en) * 1981-09-30 1983-04-06 Siemens Aktiengesellschaft Control circuit for operand processing
EP0144268A2 (en) * 1983-11-30 1985-06-12 Fujitsu Limited Method for controlling buffer memory in data processing apparatus

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3800292A (en) * 1972-10-05 1974-03-26 Honeywell Inf Systems Variable masking for segmented memory
US3858183A (en) * 1972-10-30 1974-12-31 Amdahl Corp Data processing system and method therefor
US3806888A (en) * 1972-12-04 1974-04-23 Ibm Hierarchial memory system

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0075891A2 (en) * 1981-09-30 1983-04-06 Siemens Aktiengesellschaft Control circuit for operand processing
EP0075891A3 (en) * 1981-09-30 1986-07-16 Siemens Aktiengesellschaft Control circuit for operand processing
EP0144268A2 (en) * 1983-11-30 1985-06-12 Fujitsu Limited Method for controlling buffer memory in data processing apparatus
EP0144268A3 (en) * 1983-11-30 1987-10-14 Fujitsu Limited Method for controlling buffer memory in data processing apparatus
US4779193A (en) * 1983-11-30 1988-10-18 Fujitsu Limited Data processing apparatus for writing calculation result into buffer memory after the writing of the beginning word of the read data
US4924425A (en) * 1983-11-30 1990-05-08 Fujitsu Limited Method for immediately writing an operand to a selected word location within a block of a buffer memory

Also Published As

Publication number Publication date
FR2423822A1 (en) 1979-11-16
FR2423822B1 (en) 1983-08-05
GB2016752B (en) 1982-03-10
DE2909987A1 (en) 1979-09-20
IT7920140A0 (en) 1979-02-13
IT1164980B (en) 1987-04-22

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Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee