GB2011764A - Synchronizing circuit for a digital arrangement - Google Patents

Synchronizing circuit for a digital arrangement

Info

Publication number
GB2011764A
GB2011764A GB7849420A GB7849420A GB2011764A GB 2011764 A GB2011764 A GB 2011764A GB 7849420 A GB7849420 A GB 7849420A GB 7849420 A GB7849420 A GB 7849420A GB 2011764 A GB2011764 A GB 2011764A
Authority
GB
United Kingdom
Prior art keywords
store
cycle
coefficients
clock signal
counter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB7849420A
Other versions
GB2011764B (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Telecommunications Radioelectriques et Telephoniques SA TRT
Original Assignee
Telecommunications Radioelectriques et Telephoniques SA TRT
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Telecommunications Radioelectriques et Telephoniques SA TRT filed Critical Telecommunications Radioelectriques et Telephoniques SA TRT
Priority to GB7849420A priority Critical patent/GB2011764B/en
Publication of GB2011764A publication Critical patent/GB2011764A/en
Application granted granted Critical
Publication of GB2011764B publication Critical patent/GB2011764B/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L25/03012—Arrangements for removing intersymbol interference operating in the time domain
    • H04L25/03114—Arrangements for removing intersymbol interference operating in the time domain non-adaptive, i.e. not adjustable, manually adjustable, or adjustable only during the reception of special signals
    • H04L25/03133—Arrangements for removing intersymbol interference operating in the time domain non-adaptive, i.e. not adjustable, manually adjustable, or adjustable only during the reception of special signals with a non-recursive structure
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronizing For Television (AREA)

Abstract

Arrangement for synchronizing digital operating cycles with an external clock signal. The arrangement comprises a calculating unit 5, and a circulating store 6 which produces a sequence of multi-bit coefficients in a predetermined order in each cycle. The store 6 comprises switching means for circulating the coefficients in the store either all coefficients being circulated in series, or each individual coefficient being internally circulated in a particular sub- port of the store 6 in series. A counter 21 produces a coefficient clock signal HM, and a counter 22 forms operating cycles synchronous with the word clock signal HM and starts each operating cycle at each characteristic transition of an external clock signal HE appearing after the end of each cycle. The signal HE is reproduced from incoming data by a clock recovery circuit 2. The switching means in the store 6 are controlled by the counter 22 so that the sequence of coefficients circulate in series once in each cycle, the individual coefficients circulating internally for the remaining period of time in the cycle. <IMAGE>
GB7849420A 1978-12-21 1978-12-21 Synchroniuing circuit for a digital arrangement Expired GB2011764B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB7849420A GB2011764B (en) 1978-12-21 1978-12-21 Synchroniuing circuit for a digital arrangement

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB7849420A GB2011764B (en) 1978-12-21 1978-12-21 Synchroniuing circuit for a digital arrangement

Publications (2)

Publication Number Publication Date
GB2011764A true GB2011764A (en) 1979-07-11
GB2011764B GB2011764B (en) 1982-03-10

Family

ID=10501855

Family Applications (1)

Application Number Title Priority Date Filing Date
GB7849420A Expired GB2011764B (en) 1978-12-21 1978-12-21 Synchroniuing circuit for a digital arrangement

Country Status (1)

Country Link
GB (1) GB2011764B (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6721372B1 (en) 2000-03-17 2004-04-13 Lucent Technologies Inc. Intelligent software controlled correction of frequency tracking for a local oscillator of a receiver of a wireless device
US7227918B2 (en) 2000-03-14 2007-06-05 Altera Corporation Clock data recovery circuitry associated with programmable logic device circuitry
US7333570B2 (en) 2000-03-14 2008-02-19 Altera Corporation Clock data recovery circuitry associated with programmable logic device circuitry

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7227918B2 (en) 2000-03-14 2007-06-05 Altera Corporation Clock data recovery circuitry associated with programmable logic device circuitry
US7333570B2 (en) 2000-03-14 2008-02-19 Altera Corporation Clock data recovery circuitry associated with programmable logic device circuitry
US7684532B2 (en) 2000-03-14 2010-03-23 Altera Corporation Clock data recovery circuitry associated with programmable logic device circuitry
US6721372B1 (en) 2000-03-17 2004-04-13 Lucent Technologies Inc. Intelligent software controlled correction of frequency tracking for a local oscillator of a receiver of a wireless device

Also Published As

Publication number Publication date
GB2011764B (en) 1982-03-10

Similar Documents

Publication Publication Date Title
JPS5661873A (en) Digital video signal processor
AU517189B2 (en) Television picture special effect system using digital memory techniques
JPS54118723A (en) Phase converter
GB2073971B (en) Circuit interrupter with digital trip unit and optically-coupled data input/output system
JPS57123578A (en) Error correcting circuit for drive data
EP0450445A3 (en) Digital television signal processing circuit with orthogonal output clock
JPS5676691A (en) Television receiver with plurality of screen display
GB2011764A (en) Synchronizing circuit for a digital arrangement
JPS5773578A (en) Television receiver
JPS5718169A (en) Synchronizing circuit of video control data
JPS5528699A (en) Video signal gamma correcting circuit
US3059851A (en) Dividing apparatus for digital computers
FI894154A (en) SKENBART LINJELAOST SKRIVKLOCKA FOER BILD-I-BILD-VIDEOTILLAEMPNINGAR.
JPS5637778A (en) Producing circuit of inserted screen signal
JPS5438732A (en) Input/output order accepting system
JPS54153518A (en) Corrector for time axis error
KR960012495B1 (en) Macro block address memory for hdtv
JPS57163292A (en) Picture memory output reference display circuit
JPS5646372A (en) Picture converter
JPS561660A (en) Reading method
GB2027314B (en) Video recording time-error correction circuit
JPS53132227A (en) Output unit for video data
JPS5469337A (en) Shading correction system
JPS5492118A (en) Static picture file device
JPS5510255A (en) Variable divider-multiplier circuit using n-channel filter

Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee