GB2011727A - Improvements in or relating to packaging arrangements - Google Patents

Improvements in or relating to packaging arrangements

Info

Publication number
GB2011727A
GB2011727A GB7846698A GB7846698A GB2011727A GB 2011727 A GB2011727 A GB 2011727A GB 7846698 A GB7846698 A GB 7846698A GB 7846698 A GB7846698 A GB 7846698A GB 2011727 A GB2011727 A GB 2011727A
Authority
GB
United Kingdom
Prior art keywords
base part
chip
relating
moulded
ceramic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB7846698A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Plessey Co Ltd
Original Assignee
Plessey Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Plessey Co Ltd filed Critical Plessey Co Ltd
Priority to GB7846698A priority Critical patent/GB2011727A/en
Publication of GB2011727A publication Critical patent/GB2011727A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/055—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads having a passage through the base
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

A chip carrier packaging arrangement for use e.g. with a magnetic domain device or semiconductor integrated circuit is of a two-part construction and comprises a base part (1) and a lid (4), the base part being moulded of e.g. glass or ceramic and having a cavity (2) containing a chip (3), and a number of electrically conducting preferably non-magnetic pins (6) extending through the base part into the cavity, to which the chip may be electrically connected by interconnecting wires. The lid (4) may also be moulded of glass or ceramic and preferably sealed to the top surface of base part (1). <IMAGE>
GB7846698A 1977-12-29 1978-11-30 Improvements in or relating to packaging arrangements Withdrawn GB2011727A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB7846698A GB2011727A (en) 1977-12-29 1978-11-30 Improvements in or relating to packaging arrangements

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB5408377 1977-12-29
GB7846698A GB2011727A (en) 1977-12-29 1978-11-30 Improvements in or relating to packaging arrangements

Publications (1)

Publication Number Publication Date
GB2011727A true GB2011727A (en) 1979-07-11

Family

ID=26267403

Family Applications (1)

Application Number Title Priority Date Filing Date
GB7846698A Withdrawn GB2011727A (en) 1977-12-29 1978-11-30 Improvements in or relating to packaging arrangements

Country Status (1)

Country Link
GB (1) GB2011727A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0223234A2 (en) * 1985-11-20 1987-05-27 AMP-AKZO CORPORATION (a Delaware corp.) Interconnection package suitable for electronic devices and methods for producing same
WO2003073502A1 (en) * 2002-02-26 2003-09-04 Silicon Bandwidth, Inc. Micro grid array package for a semiconducteur die

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0223234A2 (en) * 1985-11-20 1987-05-27 AMP-AKZO CORPORATION (a Delaware corp.) Interconnection package suitable for electronic devices and methods for producing same
EP0223234A3 (en) * 1985-11-20 1989-05-10 AMP-AKZO CORPORATION (a Delaware corp.) Interconnection package suitable for electronic devices and methods for producing same
WO2003073502A1 (en) * 2002-02-26 2003-09-04 Silicon Bandwidth, Inc. Micro grid array package for a semiconducteur die
US6734546B2 (en) 2002-02-26 2004-05-11 Silicon Bandwidth, Inc. Micro grid array semiconductor die package

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Legal Events

Date Code Title Description
WAP Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1)