GB201111740D0 - Method of semiconductor element applicaiton - Google Patents

Method of semiconductor element applicaiton

Info

Publication number
GB201111740D0
GB201111740D0 GBGB1111740.5A GB201111740A GB201111740D0 GB 201111740 D0 GB201111740 D0 GB 201111740D0 GB 201111740 A GB201111740 A GB 201111740A GB 201111740 D0 GB201111740 D0 GB 201111740D0
Authority
GB
United Kingdom
Prior art keywords
element positions
substrate
planarization layer
conductive pads
semiconductor elements
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GBGB1111740.5A
Other versions
GB2498699B (en
GB2498699A (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Cambridge Display Technology Ltd
Original Assignee
Cambridge Display Technology Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cambridge Display Technology Ltd filed Critical Cambridge Display Technology Ltd
Priority to GB1111740.5A priority Critical patent/GB2498699B/en
Publication of GB201111740D0 publication Critical patent/GB201111740D0/en
Publication of GB2498699A publication Critical patent/GB2498699A/en
Application granted granted Critical
Publication of GB2498699B publication Critical patent/GB2498699B/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/129—Chiplets
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/60—Forming conductive regions or layers, e.g. electrodes
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/549—Organic PV cells

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Electromagnetism (AREA)
  • Electroluminescent Light Sources (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

During manufacture of a backplane for example for a colour pixel OLED display, a plurality of semiconducting elements in the form of chiplets are deposited on a substrate using a method comprising defining a plurality of element positions on a substrate; applying semiconductor elements 10 to the substrate; forming a first planarization layer (Fig. 4B: 405) over the applied semiconductor elements wherein the upper surface at element positions where a semiconductor element is present has a height of at least H1 above the substrate, which is greater than a maximum height H2 of the upper surface in the defined element positions where a semiconductor element is not present; depositing a plurality of conductive pads (Fig. 4C: 407) on the upper surface of the first planarization layer at the plurality of defined element positions; removing conductive pads such that only conductive pads deposited on the upper surface at element positions having the upper surface height of at least H1 are removed; forming through-vias (Fig. 4G: 11) in the first planarization layer at the plurality of defined element positions; and depositing a conductive material 413 in the through vias and over the first planarization layer to the applied semiconductor elements to remaining conductive pads and/or other applied semiconductor elements.
GB1111740.5A 2011-07-08 2011-07-08 Method of semiconductor element application Expired - Fee Related GB2498699B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB1111740.5A GB2498699B (en) 2011-07-08 2011-07-08 Method of semiconductor element application

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB1111740.5A GB2498699B (en) 2011-07-08 2011-07-08 Method of semiconductor element application

Publications (3)

Publication Number Publication Date
GB201111740D0 true GB201111740D0 (en) 2011-08-24
GB2498699A GB2498699A (en) 2013-07-31
GB2498699B GB2498699B (en) 2014-08-13

Family

ID=44544460

Family Applications (1)

Application Number Title Priority Date Filing Date
GB1111740.5A Expired - Fee Related GB2498699B (en) 2011-07-08 2011-07-08 Method of semiconductor element application

Country Status (1)

Country Link
GB (1) GB2498699B (en)

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11233784A (en) * 1998-02-17 1999-08-27 Matsushita Electron Corp Manufacture of thin film transistor
GB0819448D0 (en) * 2008-10-23 2008-12-03 Cambridge Display Tech Ltd Connected display pixel drive chiplets

Also Published As

Publication number Publication date
GB2498699B (en) 2014-08-13
GB2498699A (en) 2013-07-31

Similar Documents

Publication Publication Date Title
EP2701188A3 (en) A method of singulating semiconductor die from a semiconductor wafer
IN2014CN03081A (en)
WO2010059857A3 (en) Bottom up plating by organic surface passivation and differential plating retardation
WO2016209668A3 (en) Structures and methods for reliable packages
MX354168B (en) Method for manufacturing of printed product micro features and arrangement for continuous production of such a product.
WO2014168665A3 (en) Methods for making a superconducting device with at least one enclosure
WO2010059790A3 (en) Integration sequences with top profile modification
SG169269A1 (en) Semiconductor device and method of forming dam material around periphery of die to reduce warpage
CN105138163B (en) A kind of organic electroluminescent touch-control display panel, its preparation method and display device
WO2014105233A3 (en) Processes for multi-layer devices utilizing layer transfer
WO2014163728A3 (en) Superconducting device with at least one enclosure
WO2011149616A3 (en) Planarizing etch hardmask to increase pattern density and aspect ratio
EP2194574A3 (en) Method for producing interconnect structures for integrated circuits
TW201130099A (en) Semiconductor component and fabrication method thereof
SG171522A1 (en) Semiconductor device and method of forming compliant stress relief buffer around large array wlcsp
WO2012134175A3 (en) Conductive substrate and touchscreen having same
EP2731139A3 (en) Light-emitting display backplane, display device and manufacturing method of pixel define layer
WO2015187210A3 (en) Spacer enabled active isolation for an integrated circuit device
JP2013520844A5 (en)
WO2012061091A3 (en) Encapsulated die, microelectronic package containing same, and method of manufacturing said microelectronic package
TW200744218A (en) Semiconductor device and method of manufacturing the same
EP2403019A3 (en) Light emitting device
CN110518150A (en) Display base plate and its manufacturing method, display device
CN106384789A (en) OLED packaging structure and OLED packaging method
WO2010110987A3 (en) Methods of forming patterns on substrates

Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee

Effective date: 20160708