GB201017741D0 - Data processing units - Google Patents
Data processing unitsInfo
- Publication number
- GB201017741D0 GB201017741D0 GBGB1017741.8A GB201017741A GB201017741D0 GB 201017741 D0 GB201017741 D0 GB 201017741D0 GB 201017741 A GB201017741 A GB 201017741A GB 201017741 D0 GB201017741 D0 GB 201017741D0
- Authority
- GB
- United Kingdom
- Prior art keywords
- data processing
- processing units
- units
- data
- processing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
- G06F15/7814—Specially adapted for real time processing, e.g. comprising hardware timers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
- G06F15/8053—Vector processors
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/3017—Runtime instruction translation, e.g. macros
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
- G06F9/3887—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by a single instruction for multiple data lanes [SIMD]
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- General Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computing Systems (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Advance Control (AREA)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB1017741.8A GB2484900A (en) | 2010-10-21 | 2010-10-21 | Data processing unit with scalar processor, vector processor array, parity and FFT accelerator units |
PCT/GB2011/052042 WO2012052774A2 (en) | 2010-10-21 | 2011-10-20 | Data processing units |
US13/880,473 US9285793B2 (en) | 2010-10-21 | 2011-10-20 | Data processing unit including a scalar processing unit and a heterogeneous processor unit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB1017741.8A GB2484900A (en) | 2010-10-21 | 2010-10-21 | Data processing unit with scalar processor, vector processor array, parity and FFT accelerator units |
Publications (2)
Publication Number | Publication Date |
---|---|
GB201017741D0 true GB201017741D0 (en) | 2010-12-01 |
GB2484900A GB2484900A (en) | 2012-05-02 |
Family
ID=43334129
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB1017741.8A Withdrawn GB2484900A (en) | 2010-10-21 | 2010-10-21 | Data processing unit with scalar processor, vector processor array, parity and FFT accelerator units |
Country Status (1)
Country | Link |
---|---|
GB (1) | GB2484900A (en) |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5197130A (en) * | 1989-12-29 | 1993-03-23 | Supercomputer Systems Limited Partnership | Cluster architecture for a highly parallel scalar/vector multiprocessor system |
US8090928B2 (en) * | 2002-06-28 | 2012-01-03 | Intellectual Ventures I Llc | Methods and apparatus for processing scalar and vector instructions |
US7412588B2 (en) * | 2003-07-25 | 2008-08-12 | International Business Machines Corporation | Network processor system on chip with bridge coupling protocol converting multiprocessor macro core local bus to peripheral interfaces coupled system bus |
US20070198815A1 (en) * | 2005-08-11 | 2007-08-23 | Coresonic Ab | Programmable digital signal processor having a clustered SIMD microarchitecture including a complex short multiplier and an independent vector load unit |
-
2010
- 2010-10-21 GB GB1017741.8A patent/GB2484900A/en not_active Withdrawn
Also Published As
Publication number | Publication date |
---|---|
GB2484900A (en) | 2012-05-02 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |