GB1605048A - Impulse detection arrangements - Google Patents

Impulse detection arrangements Download PDF

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Publication number
GB1605048A
GB1605048A GB5304977A GB5304977A GB1605048A GB 1605048 A GB1605048 A GB 1605048A GB 5304977 A GB5304977 A GB 5304977A GB 5304977 A GB5304977 A GB 5304977A GB 1605048 A GB1605048 A GB 1605048A
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United Kingdom
Prior art keywords
waveform
output
pulse
arrangement
substantially rectangular
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB5304977A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BAE Systems Electronics Ltd
Original Assignee
Marconi Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Marconi Co Ltd filed Critical Marconi Co Ltd
Priority to GB5304977A priority Critical patent/GB1605048A/en
Publication of GB1605048A publication Critical patent/GB1605048A/en
Expired legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/125—Discriminating pulses
    • H03K5/1252—Suppression or limitation of noise or interference
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/08—Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding
    • H03K5/082—Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding with an adaptive threshold
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/153—Arrangements in which a pulse is delivered at the instant when a predetermined characteristic of an input signal is present or at a fixed time interval after this instant

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Manipulation Of Pulses (AREA)

Description

(54) IMPROVEMENTS IN OR RELATING TO IMPULSE DETECTION ARRANGEMENTS (71) We, THE MARCONI COM PANY LIMITED, a British Company, of Marconi House, New Street, Chelmsford, Essex CMi 1PL, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: This invention relates to impulse detection arrangements and in particular to such arrangements for detecting pulses in a signal such as might be produced from an infra-red detector.
The invention seeks to provide improved such detection arrangements.
According to this invention an impulse detection arrangement comprises means for applying an input waveform containing an impulse to be detected in parallel to a low pass filter arrangement and an equalising delay arrangement, the latter having a delay corresponding to that provided by the former, whereby to provide two waveforms, that from said equalising delay arrangement corresponding to said input waveform and that from said low pass filter arrangement corresponding to said input waveform but with said impulse attenuated, means for adding to the waveform at the output of said low pass filter arrangement a threshold level, means for comparing the waveform produced by said last mentioned addition with the output waveform of said equalising delay arrangement to produce a substantially rectangular pulse, and means responsive to said substantially rectangular pulse for indicating the presence of an impulse in said input waveform.
Preferably said impulse attenuated by said low pass filter arrangement is attenuated to an extent such that said impulse is effectively removed.
Preferably said means responsive to said substantially rectangular pulse comprises a monostable circuit arranged to be triggered by said substantially rectangular pulse and means for comparing the output pulse of said monostable circuit with said substantially rectangular pulses to produce an impulse presence indicating pulse when the output pulse of said monostable circuit is of a duration greater than that of said substantially rectangular pulses.
Preferably said last mentioned means for comparing comprises a logic gate to which said substantially rectangular pulse and the output pulse of said monostable circuit are applied.
Means may be provided for controlling the pulse width or duration of the output pulse of said monostable circuit in a manner dependent upon the length or duration of the impulse in said input waveform.
Preferably said last mentioned means comprises means for subtracting the waveform at the output of said low pass filter arrangement from the waveform at the output of said equalising delay arrangement to produce a resultant waveform, means for holding the peak value of said resultant waveform and means for utilising said held peak value of said resultant waveform to control the output pulse width of said monostable circuit.
Preferably said means for holding said peak value comprises a peak level holding circuit which is arranged to be primed to register said peak value by said substantially rectangular pulse, means being provided for re-setting said peak level holding circuit as required.
Where it is desired to determine relatively precisely the instant of detection, preferably means are provided for subtracting the waveform at the output of said low pass filter arrangement from the waveform at the output of said equalising delay arrangement to produce a resultant waveform, means are provided for differentiating said resultant waveform and means are provided responsive to the zero crossings of said differentiated waveform for producing a series of substantially rectangular pulses synchronised to said zero crossings, said series of substantially rectangular pulses being applied to a gate circuit controlled by said first mentioned substantially rectangular pulses to provide an output timing pulse related to the required instant of detection.
Preferably said means responsive to said zero crossings comprises a comparator circuit, one input of which is comprised of said differentiated waveform and the other input of which is connected to common potential.
The invention is illustrated in and further described with reference to the drawings accompanying the provisional specification in which, Figure 1 is one example of an impulse detection arrangement in accordance with the present invention and Figure 2 shows a number of explanatory waveforms.
Referring to Figure 1, the arrangement, in this example is provided to detect positive going impulses in a signal such as might be produced from an infra-red detector. The signal is applied, after pre-amplification and noise bandwidth limiting to an input terminal 1. At this point the waveform is as illustrated at H in Figure 2, where a positive going impulse is shown at H'.
Input terminal 1 is connected to pass the waveform H, in parallel, through a low pass filter network and an equalising delay network 3, the latter providing a delay equivalent to the delay of the low pass filter 2.
Since both networks 2 and 3 are third order, each may consist, in practice, of an operational amplifier, a transistor, 3 capacitors and several resistors.
The output of low pass filter 2 is the waveform I of Figure 2, whilst the output of the equalising delay network 3 is the waveform J of Figure 2, with the positive going impulse still present and here shown at J'.
The outputs of the networks 2 and 3 are applied to a subtractor circuit 4 which subtracts the waveforms I and J of Figure 2 to provide at the output of subtractor circuit 4 the waveform shown at M in Figure 2.
The output of low pass filter network 2, the waveform I, is added in an adding circuit 5 to a threshold level, tin Figure 2, to provide at its output the waveform K of Figure 1.
The output of adding circuit 5, the waveform K, is applied to a comparator or threshold detector 6, a second input for which is provided by the output of the equalising delay network 3, i.e. the waveform J. The output of comparator 6 is thus the waveform L of Figure 2.
The output of comparator 6, the waveform L is applied to trigger, with the leading edge of the pulse L' in waveform L, a monostable circuit 7. Monostable circuit 7 provides an output as shown at Q in Figure 2 and this output is applied with the output from the comparator 6 (i.e. the waveform L) to a logic gate 8 so that the pulse provided by the monostable 7 is compared in width with the pulse L' provided in the output waveform L of the comparator 6. If the pulse L' is of a width greater than that of the pulse of the monostable 7 no output will be obtained from the logic gate 8, but if the pulse L' is narrower than the pulse of the monostable circuit 7, an output will appear as shown at R in Figure 2.
From large point sources infra-red targets can result in waveforms (L) at the output of the comparator 6, which have pulses (L') of several resolution widths and these would not normally result in an output pulse at the output of logic gate 8. In order to accommodate such very large point source targets, the output waveforms I and J of the low pass filter network 2 and the equalising target network 3 are applied to a subtractor circuit 4 which produces at its output the difference as shown at M in Figure 2. The output waveform M of subtractor circuit 4 is applied to a peak level holding circuit 9, which holds the peak level of the waveform M, if a threshold level has been exceeded.The output of the peak level holding circuit 9 is applied to the monostable circuit 7 to control the width of the pulse produced by this monostable circuit in accordance with a control law such that for target sources of interest the output pulse of the monostable 7 exceeds the width of the pulse L' in the waveform L at the output of the comparator circuit 6, thus ensuring an output pulse from logic gate 8. In practice, the control law will be an approximate square root log law. The output level holding circuit 9 is re-set as required by a pulse applied to "re-set to zero" input 10. Peak level holding circuit 9 is primed to hold the peak level of the waveform M by a pulse upon "start" input 11. As shown input 11 is connected to the output of comparator 6 so that peak level holding circuit 9 is primed by the leading edge of the pulse L' in the waveform L at the output of comparator circuit 6.
In order to determine the precise instant of detection the output waveform M of the subtractor circuit 4 is applied to a differentiating circuit 12, which, from the waveform M produces the waveform shown at N in Figure 2.
The output of differentiating circuit 12, the waveform N, is applied to a comparator circuit 13 having a second input at common potential in order to record the zero crossings of the waveform N as shown by the waveform as in Figure 2. The waveform 0 appearing at the output of the comparator circuit 13 is applied to a gate 14, which is arranged to be opened (i.e. rendered conductive) by the leading edge of pulse L' appearing in the waveform L at the output of the comparator circuit 6. This produces at the output of the gate 14, the waveform P of Figure 2, the leading edge of the pulse P' therein indicating the instant of detection.
Thus at output terminal 15 connected to the output of logic gate 8 will appear a pulse denoting the presence of an impulse signal, whilst at output terminal 16 connected to the output of gate 14 will appear a pulse, the leading edge of which represents the detection instant. A further output terminal 17 is connected to the output of subtracting circuit 4 in order to provide a high frequency analogue output (the waveform M) where this is required.
WHAT WE CLAIM IS: 1. An impulse detection arrangement comprising means for applying an input waveform containing an impulse to be detected in paralel to a low pass filter arrangement and an equalising delay arrangement, the latter having a delay corresponding to that provided by the former, whereby to provide two waveforms, that from said equalising delay arrangements corresponding to said input waveform and that from said low pass filter arrangement corresponding to said input waveform but with said impulse attenuated, means for adding to the waveform at the output of said low pass filter arrangement a threshold level, means for comparing the waveform produced by said last mentioned addition with the output waveform of said equalising delay arrangement to produce a substantially rectangular pulse, and means responsive to said substantially rectangular pulse for indicating the presence of an impulse in said input waveform.
2. An arrangement as claimed ih claim 1 and such that said impulse attenuated by said low pass filter arrangement is attenuated to an extent such that said impulse is effectively removed.
3. An arrangement as claimed in any of the above claims and wherein said means responsive to said substantially rectangular pulse comprises a monostable circuit arranged to be triggered by said substantially rectangular pulse and means for comparing the output pulse of said monostable circuit with said substantially rectangular pulses to produce an impulse presence indicating pulse when the output pulse of said monostable circuit is of a duration greater than that of said substantially rectangular pulses.
4. An arrangement as claimed in claim 3 and wherein said last mentioned means for comparing comprises a logic gate to which said substantially rectangular pulse and the output pulse of said monostable circuit are applied.
5. An arrangement as claimed in claim 3 or 4 and wherein means are provided for controlling the pulse width or duration of the output pulse of said monostable circuit in a manner dependent upon the length or duration of the impulse in said input waveform.
6. An arrangement as claimed in claim 5 and wherein said last mentioned means comprises means for subtracting the waveform at the output of said low pass filter arrangement from the waveform at the output of said equalising delay arrangement to produce a resultant waveform, means for holding the peak value of said resultant waveform and means for utilising said held peak value of said resultant waveform to control the output pulse width of said monostable circuit.
7. An arrangement as claimed in claim 6 and wherein said means for holding said peak value comprises a peak level holding circuit which is arranged to be primed to register said peak value by said substantially rectangular pulse, means being provided for re-setting said peak level holding circuit as required.
8. An arrangement as claimed in any of the above claims wherein means are provided for subtracting the waveform at the output of said low pass filter arrangement from the waveform at the output of said equalising delay arrangement to produce a resultant waveform, means are provided for differentiating said resultant waveform and means are provided responsive zero crossings of said differentiated waveform for producing a series of substantially rectangular pulses synchronised to said zero crossings, said series of substantially rectangular pulses being applied to a gate circuit controlled by said first mentioned substantially rectangular pulses to provide an output timing pulse related to the required instant of detection.
9. An arrangement as claimed in claim 8 and wherein said means responsive to said zero crossings comprises a comparator circuit, one input of which is comprised of said differentiated waveform and the other input of which is connected to common potential.
**WARNING** end of DESC field may overlap start of CLMS **.

Claims (10)

**WARNING** start of CLMS field may overlap end of DESC **. waveform as in Figure 2. The waveform 0 appearing at the output of the comparator circuit 13 is applied to a gate 14, which is arranged to be opened (i.e. rendered conductive) by the leading edge of pulse L' appearing in the waveform L at the output of the comparator circuit 6. This produces at the output of the gate 14, the waveform P of Figure 2, the leading edge of the pulse P' therein indicating the instant of detection. Thus at output terminal 15 connected to the output of logic gate 8 will appear a pulse denoting the presence of an impulse signal, whilst at output terminal 16 connected to the output of gate 14 will appear a pulse, the leading edge of which represents the detection instant. A further output terminal 17 is connected to the output of subtracting circuit 4 in order to provide a high frequency analogue output (the waveform M) where this is required. WHAT WE CLAIM IS:
1. An impulse detection arrangement comprising means for applying an input waveform containing an impulse to be detected in paralel to a low pass filter arrangement and an equalising delay arrangement, the latter having a delay corresponding to that provided by the former, whereby to provide two waveforms, that from said equalising delay arrangements corresponding to said input waveform and that from said low pass filter arrangement corresponding to said input waveform but with said impulse attenuated, means for adding to the waveform at the output of said low pass filter arrangement a threshold level, means for comparing the waveform produced by said last mentioned addition with the output waveform of said equalising delay arrangement to produce a substantially rectangular pulse, and means responsive to said substantially rectangular pulse for indicating the presence of an impulse in said input waveform.
2. An arrangement as claimed ih claim 1 and such that said impulse attenuated by said low pass filter arrangement is attenuated to an extent such that said impulse is effectively removed.
3. An arrangement as claimed in any of the above claims and wherein said means responsive to said substantially rectangular pulse comprises a monostable circuit arranged to be triggered by said substantially rectangular pulse and means for comparing the output pulse of said monostable circuit with said substantially rectangular pulses to produce an impulse presence indicating pulse when the output pulse of said monostable circuit is of a duration greater than that of said substantially rectangular pulses.
4. An arrangement as claimed in claim 3 and wherein said last mentioned means for comparing comprises a logic gate to which said substantially rectangular pulse and the output pulse of said monostable circuit are applied.
5. An arrangement as claimed in claim 3 or 4 and wherein means are provided for controlling the pulse width or duration of the output pulse of said monostable circuit in a manner dependent upon the length or duration of the impulse in said input waveform.
6. An arrangement as claimed in claim 5 and wherein said last mentioned means comprises means for subtracting the waveform at the output of said low pass filter arrangement from the waveform at the output of said equalising delay arrangement to produce a resultant waveform, means for holding the peak value of said resultant waveform and means for utilising said held peak value of said resultant waveform to control the output pulse width of said monostable circuit.
7. An arrangement as claimed in claim 6 and wherein said means for holding said peak value comprises a peak level holding circuit which is arranged to be primed to register said peak value by said substantially rectangular pulse, means being provided for re-setting said peak level holding circuit as required.
8. An arrangement as claimed in any of the above claims wherein means are provided for subtracting the waveform at the output of said low pass filter arrangement from the waveform at the output of said equalising delay arrangement to produce a resultant waveform, means are provided for differentiating said resultant waveform and means are provided responsive zero crossings of said differentiated waveform for producing a series of substantially rectangular pulses synchronised to said zero crossings, said series of substantially rectangular pulses being applied to a gate circuit controlled by said first mentioned substantially rectangular pulses to provide an output timing pulse related to the required instant of detection.
9. An arrangement as claimed in claim 8 and wherein said means responsive to said zero crossings comprises a comparator circuit, one input of which is comprised of said differentiated waveform and the other input of which is connected to common potential.
10. An impulse detection arrangement
substantially as herein described with reference to the drawings accompanying the provisional specification.
GB5304977A 1978-03-02 1978-03-02 Impulse detection arrangements Expired GB1605048A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB5304977A GB1605048A (en) 1978-03-02 1978-03-02 Impulse detection arrangements

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB5304977A GB1605048A (en) 1978-03-02 1978-03-02 Impulse detection arrangements

Publications (1)

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GB1605048A true GB1605048A (en) 1981-12-16

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Application Number Title Priority Date Filing Date
GB5304977A Expired GB1605048A (en) 1978-03-02 1978-03-02 Impulse detection arrangements

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009122352A2 (en) * 2008-04-03 2009-10-08 Nxp B.V. Glitch monitor and circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009122352A2 (en) * 2008-04-03 2009-10-08 Nxp B.V. Glitch monitor and circuit
WO2009122352A3 (en) * 2008-04-03 2009-11-26 Nxp B.V. Glitch monitor and circuit

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PS Patent sealed
PCNP Patent ceased through non-payment of renewal fee
PE20 Patent expired after termination of 20 years

Effective date: 19980301