GB1603680A - Polyphonic electronic music system - Google Patents

Description

(54) POLYPHONIC ELECTRONIC MUSIC SYSTEM (71) We, D. H. BALDWIN COMPANY, an Ohio Corporation organised and existing under the laws of the State of Ohio, United States of America, of 1801 Gilbert Avenue, Cincinnati, Ohio, United States of America, do hereby declare the invention for which we pray that a patent may be granted to us and the method by which it is to be performed to be particularly described in and by the following statement:- The present invention relates to a polyphonic electronic music system which provides output tone signals corresponding to the played keys in different voices to provide an orchestral chord effect. This orchestral chord can be either musically independent or in combination with conventional organ accompaniment, or it can provide the background or accompaniment to conventional organ solo voices.The present invention further relates to techniques for producing orchestral chord tone signals that are slightly detuned to provide a fuller, richer more realistic ensemble effect.

Upon activation of a single key, it is old in the organ art to produce simultaneously, by stop selection, tones of different timbre and the same pitch, or by coupler selection, different octavely or harmonically related frequencies in the same timbres, or both of these at the same time.

It is also old for keys of different notes played simultaneously on different manuals of an organ to produce different timbres depending upon the particular stops selected on the different manuals.

Furthermore various key-switching circuits have been devised to associate the frequency of a tone oscillator with the highest or the lowest key played. For example in U.S. Patent No. 3,801,721 Bunger discloses a circuit arrangement for assigning position priority to the highest pitch key of a set of actuated keys. Dual oscillator key-switching systems have been designed to respond to the highest and the lowest keys played. However, when the position priority key-switching methods are extended to larger numbers of notes played, the switching becomes very cumbersome both mechanically and electrically.

Various multiplexing techniques have been used to reduce the wiring complexity between the playing key switches and the gating circuits which control the flow of tone signals. Examples include U.S. Patent Nos. 3,746,773 - Uetrecht and 3,916,750 Uetrecht. Time priority systems have also been devised for assigning a plurality of tone frequency means to keys in the order in which they are played in time as in U.S.

Patent No. 3,610,799 -- Watson. However, the individual tones of chord notes played on the same keyboard or manual have generally been heard in the same timbre or timbres in contrast to the present invention.

Thus, it is a principal object of the present invention to achieve a polyphonic synthesizer for use in electronic musical instruments which will sound individual notes simultaneously played on a single manual in different voices.

It is a preferred object of the invention to provide a polyphonic electronic music system capable of automatically giving orchestral chord tonal outputs with different voices for different notes in a complex chord, and of automatic doubling of different voices on the same note when the chord becomes less complex in order to continue the ensemble effect.

According to the present invention, there is provided a polyphonic electronic music system for an electronic musical instrument having at least one manual of keys corresponding to the notes of the musical scale, comprising: means for producing tone signals of frequencies corresponding to the notes of keys contemporaneously played on the manual of keys; and means for gating and filtering the tone signals to produce different voices for different frequencies, the manner of assignment of voices to the individual frequencies being variable according to the number of keys played at any given time.

By "the manner of assignment of voices to the individual frequencies being variable" is meant that, for example, the lowest pitch note in a contemporaneously played group of notes of different pitches will not always have the same voice assigned to it but the voice or voices assigned to it may differ according to the number of notes in the contemporaneously played group, and the same for the next lowest pitch note, and so on.Thus, as a further example, the system might operate to allot to the lowest pitch note in the group flute and trumpet voices if only one note is being played, or trombone and tuba voices, if two notes are being contemporaneously played, or the tuba voice alone if more than two notes are being contemporaneously played; and the system may perform the determination of te actual number of note keys being contemporaneously played by the player of the instrument, and may then select the particular voices to be allotted to the individual notes according to that determination.

In a preferred embodiment, a polyphonic electronic music system for use in an electronic musical instrument comprises a clock means for providing a plurality of clock outputs, a counter and decoder means for counting the clock pulses and decoding the counter outputs into a first set of time division logic signals representative of twelve notes of an octave, a second set of time division logic signals representative of two or more octaves, and a third set of time division logic signals representative of at least two manuals of keys of the electronic musical instrument. Multiplexer means is provided for transmitting certain ones of the first set of ' time division logic signals representative of the actuated key switches of the at least two manuals.Decoder and multiplexer means are provided for receiving the logic signals representative of the actuated key switches, the second set of logic signals, and the third set of logic signals and providing a serial train of time division multiplex logic signals identifying the actuated key switches.

Memory means are provided for storing the serial train of logic signals representative of the actuated key switches for one cycle of the clock means.

Comparator means is provided for comparing the serial train stored in the memory with the next serial train of logic signals representative of the then actuated key switches during the next cycle of the clock means and providing an enabling signal when the stored serial train corresponds to the next serial train. Priority selector means is provided for providing time division logic signals representative of the three lowest notes and the highest note of the actuated key switches. Monostable and enable logic means is provided for receiving the enabling signal from the comparator means, and the logic signals from the priority selector means and providing in response thereto output logic signals representative of the number of actuated keys and logic signals representative of the lowest three notes and the highest note of the actuated keys.

Programmable counter means is provided for receiving the logic signals from the monostable and enable logic means representative of the actuated keys, the first set of logic signals representative of the twelve notes of an octave, and logic signals representative of the two or more octaves and in response thereto producing slightly detuned output tone signals corresponding to the lowest three notes and the highest note of the actuated key switches, and voltage signals representative of the lowest three notes and the highest note of the actuated key switches.

Also provided are voltage control gate and filter means for wave shaping the output tone signals from the programmable counter means to produce desired voicing characteristics. An output system is provided for converting the wave shaped tone signals into audible sound.

The programmable counter means may comprise first, second, third and fourth programmable counters each of which receives a respective master frequency and divides that respective master frequency by a variable number determined by the logic signals from the monostable and enable logic means to produce tone signals representative of the actuated key switches.

The monostable and enable logic means may provide logic signals to the first, second, third, and fourth programmable counters such that if only one key switch is actuated, the third and fourth programmable counters receive logic signals representative of the note of the key switch. If two key switches are actuated, the first and second programmable counters receive logic signals representative of the lower note, and the third and fourth programmable counters receive logic signals representative of the higher note of the actuated key switches. If three or more key switches are actuated, the first programmable counter receives a logic signal representative of the lowest note, the second programmable counter receives a logic signal representative of the second lowest note, the third programmable counter receives a logic signal representative of the third lowest note, and the fourth programmable counter receives a logic signal representative of the highest note of the actuated key switches.

The tone signals produced by the programmable counters are fed to pulse gate and voicing circuits which shape and filter the tone signals to produce the desired voices. A quartet arrangement is provided so that the individual notes of a simultaneously played chord are sounded in different voices to produce an orchestral effect.

Arrangements according to the invention will now be described by way of example and with reference to the accompanying drawings, in which: Figure I is a block diagram of a polyphonic electronic music system in accordance with the present invention.

Figure 2 is a more detailed schematic diagram of the system clock illustrated in Figure 1.

Figure 3 is a more detailed schematic diagram of a portion of the counter and decoder circuit illustrated in Figure 1.

Figure 4 is a more detailed schematic diagram of a portion of the counter and decoder circuit, and the multiplexer circuits 12 and 15 illustrated in Figure 1.

Figure 5 is a detailed circuit diagram of the priority selector circuit illustrated in Figure 1.

Figure 6 is a detailed circuit diagram of the memory circuit, comparator circuit, and monostable and enable logic circuit illustrated in Figure 1.

Figures 7A, 7B, 7C and 7D are detailed circuit diagrams of the programmable counter circuits illustrated in Figure 1.

Figure 8A is a diagram of the digital logic pulses developed by the clock 10 for a period of four microseconds.

Figure 8B is a diagram of the digital logic pulses produced by the counter and decoder circuit 11 for a period of 48 microseconds.

Figure 9A is a diagram of the digital logic pulses of the counter and decoder circuit 11 for a periof of 288 microseconds.

Figure 9B is a diagram of the digital logic pulses of the counter and decoder circuit 11 for a period of 1.152 milliseconds.

Figure 10A is a chart showing the truth table for the logic circuitry of the present invention.

Figure 10B is a truth table for the octave data pulses 0146.

Figure 11 is a diagram showing the orientation of Figures 2, 3, and 4.

Figure 12 is a diagram showing the orientation of Figures 5 and 6.

Figure 13 is a diagram showing the orientation of Figures 7A, 7B, 7C and 7D.

Figure 14 is a block diagram of the rate scaler frequency generator 22 illustrated in Figure 1.

Figure 15 is a graph showing the voltage versus frequency relationship between the output frequency fv and the reference voltages V8-V2 of the vibrato voltage controlled oscillator 366 illustrated in Figure 14.

Figure 16 is a detailed circuit diagram of the master frequency generator 23 illustrated in Figure 1.

Figure 17 is a detailed circuit diagram of the vibrato oscillator 362 illustrated in Figure 14.

Figure 18 is a detailed circuit diagram of the vibrato voltage controlled oscillator 366 illustrated in Figure 14.

Figure 19 is a detailed circuit diagram of the control voltage generator 372 illustrated in Figure 14.

Figure 20 is a detailed circuit diagram of the ensemble voltage controlled oscillator 378 illustrated in Figure 14.

Figure 21 is a detailed circuit diagram of the rate scaler frequency shifters 360 illustrated in Figure 14.

Figure 22 is a diagram of the wave forms of the rate scaler frequency shifters 360.

Figures 23-29 are detailed circuitdiagrams of the voltage controlled gate and filter circuits 21 illustrated in Figure 1.

Figure 30 is a diagram showing the arrangement of Figures 23-29.

Figure 31 is a block diagram of an alternative embodiment of the present invention.

With reference to Figure 1, a block diagram of the preferred embodiment of a polyphonic electronic music system 1 in accordance with the present invention is illustrated. A clock 10 includes a one megahertz oscillator and produces various clock outputs of varying duty cycles and phases at 250 KHz as illustrated in Figure 8A. The CK2 and CK outputs are connected to counter and decoder circuit 11. The CK output is also connected to multiplexer circuits 12. The CK clock is connected to memory circuit 17 and the CK5 output is connected to comparator circuit 16 and monostable and enable logic circuit 19 to control its operation.

Count and decoder circuit 11 is clocked by CK2 and CK2. CK2 is counted by a count by twelve flip-flop circuit and decoded into twelve sequential pulses T1 through T12 and their complements Tl through T12 (See Figure 8B). The T pulses have a guard band of one eighth duty cycle imposed by the CK2 pulse from clock 10 so that there is no overlap between any of the pulses T1--T12. Tl-Tl2 are connected to multiplexer circuits 12 by twelve separate lines 24. Tl-T12 are connected to the demultiplexer and gate circuits 14 by twelve separate lines 26. Counter and decoder circuit 11 also divides CK into six sequential pulses 01--06. The period of each of the 01--06 pulses spans the Tl through T12 sequence of pulses.The 01--06 data pulses are applied on six separate lines 28 to multiplexer circuit 15. Counter and decoder circuit 11 also produces two data pulses M I and M2 each of which encompass the entire sequence of octave time pulses 01--06. M1 and M2 time pulses represent the selected manual of the organ.

and M2 are applied to octave multiplexing circuit 15 as well as to priority selector circuit 18. A nine bit word Q3-Ql 1 produced by counter and decoder circuit 11 is applied on nine separate leads 30 from counter and decoder circuit 11 to memory circuit 17. Seven bits, Q3-Q9, are applied on seven different leads 32 to priority selector circuit 18. Also, time slot pulse T10 and octave time slot pulse 06 are applied to priority selector circuit 18 to decode the seventieth time slot (i.e., the 10th note of the sixth octave). The data pulses T2T 12 connected by eleven separate leads 34 to programmable counter circuits 20.A three bit word produced by counter and decoder 11 comprising Q7, Q9 and Q8 is connected by three separate leads 36 to the programmable counter circuits 20.

Q7, Q9 and Q8 encode the octave time slots 0106 and are used by the programmable counter circuits to decode the octave of the played keys.

Multiplexer 12 encodes the notes played by the two sets of sixty-one key switches 33 representing two manuals or keyboards into a time division multiplex logic signal on lead 39 connected to tab switch logic circuit 13.

The tab switch logic circuit 13 directs each octave of encoded key switch data obtained from multiplexer circuit 12 into the appropriate octave demultiplexer and gate circuits 14. Tab switch logic circuit 13 and demultlplexer and gate circuits 14 are conventional and operate in substantially the same manner as illustrated and described in applicant's U.S. Patents Nos.

3,746,773 and 3,916,750. The Tl-T12 data on lead 26 to demultiplexer and gate circuit 14 is utilized to decode the input from the tab switch logic circuit 13 into the corresponding played notes. The output of demultiplexer and gate circuits 14 is applied to a conventional primary output system 27 (including filters, an amplifier and loud speaker).

A master frequency generator 23 is connected to a top octave frequency generator and dividers 25 which produce tone signals for all 96 notes of the organ which are applied on ninety-six leads 40 to the demultiplexer and gate circuit 14.

Frequency generators 23 and 25 are conventional and may be similar to those illustrated in applicants' U.S. Patent No.

3,816,635. Master frequency generator 23 is also connected to a rate scaler frequency generator 22 which produces four output frequencies MF1, MF2, MF3, and MFH which are applied to the programmable counter circuits 20. A control voltage Vh is connected via line 56 from the counter circuits 20 to the rate scaler frequency generator 22 for the purpose of slightly varying its output frequencies MF1, MF2, MF3 and MFH.

Multiplexer 12 provides time division multiplex signals on twelve separate leads 41 representative of played key switches 33.

Six of the leads correspond to the six octaves of the solo manual (S 1-S6) of the organ and the other six leads correspond to the six octaves of the accompaniment manual (Also6) of the organ. These twelve leads are connected to the multiplexer circuit 15 which decodes this data along with 01---06 and ME and M2 data to produce a sequential time division multiplex output signal train SA on a single lead 42. SA contains data representative of the particular notes played and the manual in which these notes are located.SA is directed to memory 17 where the data is stored for one cycle to be compared with SA data on the next occurrence of the CiC clock to determine whether there has been any change in the played keys from one cycle of the clock to the next. Comparator 16 receives the SA data stored by memory 17 on the previous cycle on lead 44 and upon the occurrence of the CK5 clock signal, compares that data with the SA data on lead 42 for the present cycle. If the data has not changeda a logic signal identified by the mnemonic SCH is applied on lead 45 to the monostable and enable logic circuit 19 to indicate that there has been no change in the keys played.

The prioritHelector circuit 18 decodes SA, M I, 2, T10 06, Q3Q9 to produce on eleven leads 46 connected to monostable and enable logic circuit 19 data representative of the lowest three notes and the highest note played. The monostable and enable logic circuit 19 decodes the information on leads 46 to produce on four leads 48 logic information designated CLEI, CLE2, CLE3, and CLEH representative of three lowest notes played and the highest note played. Monostable and enable logic circuit 19 also produces on two leads 50 information designated GBEI and GBE2 representative of the number of notes that have been played.

The programmable counter circuits 20 receive the CLEI through CLEH information which is converted to four frequency outputs fl-fH on four leads 52.

The four programmable counter circuits 20 also produce on four leads 54 four separate voltages V1, V2, V3, and VH which are representative of the frequency outputs fWfH are applied to the voltage controlled rate scaler frequency generator 22 to control MF1 through MFH so that those frequencies change very slightly to detune the outputs flH so that a richer orchestral effect is produced. The four frequencies fl-fH are applied to the voltage controlled gate and filter circuits 21. The output of the voltage controlled gate and filter circuits 21 is connected to a two channel secondary output system 31 (i.e., an acoustic radiating system including amplifiers and loudspeakers).

With reference to Figure 2, clock 10 comprises a conventional 1MHz oscillator 100 comprising NAND gates 102 and 104 and NOR gate 106 arranged to produce lMHz at the CKl output. The lMHz CK1 output is connected to the clock (CK) inputs of JK flip-flops FFL and FF2.The CKl output and the respective Ql, Q1, and Q2 outputs of flip-flops FFI and FF2 are connected as indicated to NAND gates 108 and 110 and NOR gates 112, 114, and 116 which act to decode these outputs to produce clock outputs KC2, CK3, CK4, CK5, and C. Figure 8A illustrates the time relationship of the various clock outputs CKl, CK2, C, CK4 and CK5.

The CK output from NOR gate 116 is applied to the clock input of flip-flop FF3 (see Figure 3) of counter and decoder circuit 11. The CK2 output of NOR gate 114 is also connected to one of the inputs of each of NOR gates 120 and 122 in counter and decoder circuit 11. The Q3 output of FF3 is connected to the other input of NOR gate 122 and the Q3 output of FF3 is connected to the input of NOR gate 120 and also to the clock (CK) inputs of JK flip-flops FF4, FF5, and FF6. The Q output of flop FF4 is labelled Q4, the Q output of F5 is labelled Q5, and Q the output of FF6 is labelled Q6. The purpose of these outputs will be described later.

The output of NOR gate 120 is labelled QA and the output of NOR gate 122 is labelled QB. The Q and Q outputs of FF4, FF5, and FF6 are encoded by 12 NAND gates 124 to produce 12 logic outputs labelled Tl through T12 which, with reference to Figure 8B can be seen to be 12 sequential pulses having a slightly reduced duty cycle so that there is a guard band between each of the pulses T1 through T12 separating the pulses so that there is no overlap. The guard band separating the pulses is imposed by the CK2 pulse applied to NOR gates 120 and 122. QA and QB are applied to alternate NAND gates 124 so that the end of each T pulse is brought to logic one when CK2 goes to logic one. Thus, there is no overlap between the adjacent T and T pulses.

Counter and decoder circuit 11 also comprises twelve inverters 126 which invert the Tl-Tm pulses to positive true Tl-T12. T1--T12 are applied to the tdemultiplexer and gate circuits 14 to provide time position signals to the demultiplexer and gate circuits 14 in the same manner as described in applicant's U.S. Patents Nos. 3,746,773 and 3,916,750.

The Q6 output of FF6 is connected to the clock (CK) inputs of JK flip-flops FF7, FF8, and FF9 (see Figure 4). The Q outputs of FF7, FF8, and FF9 are respectively labelled Q7, Q8, and Q9. The Q and Q outputs of FF7, FF8 and FF9 are decoded by 6 NOR gates 128 to produce 6 sequential pulses 01 through 06, each having a period of 48 micro-seconds encompassing the period of T1 through T12. (See Figure 9A and 8B).

Sequential periods 01 through 06 represent the octave time slots of the time division multiplex signal as will be hereinafter more fully described. Thus for each 0 time slot the entire sequence of T pulses (T1T12) occurs.~~ The Q7 output of FF7 connected to the clock (CK) input of JK flip-flops FF10 and FF11 which produce at their Q outputs Q10 and Qll logic signals. Q10 and Q11 are decoded by NAND gates 129 and 130 to produce each of their respective outputs MT and MT time division multiplex signals (see Figure 98). ME represents the time for the solo manual of the organ and M2 represents the time slot for the accompaniment manual of the organ.As can be seen M1 and M2 each encompass 01 through 06 so that seventy two T time slots (6x12) are included in each MT and MT time slot. This is more than enough time slots to cover the notes to an organ manual.

Illustrated in the lower right hand corner of Figure 4 is a partial representation of multiplex circuit 12 for one octave of twelve total octaves of the organ. Multiplexer 12 comprises 12 similar circuits (only one of which is shown) -each of which includes twelve key switches 132 (only one of which is shown) for each semitone of the octave connected in series with the cathode twelve diodes 134 (only one of which is shown).

Switches 132 are connected in parallel to a 2.5 volt source, and the anodes of all twelve diodes 134 are connected in parallel to one side of a 1K resistor 136. Resistor 136 is connected to one input of a NAND gate 138 and the other input to NAND gate 138 is connected to diodes 134. The output of NAND gate 138 is connected to one input of NAND gate 140, and the other input of NAND gate 140 is connected to the CK2 output of clock 10 (Figure 2). Similarly, CK2 is connected to a similar NAND gate arrangement in each of the other twelve octave multiplexer circuits for the solo and accompaniment manuals. Connected between each of the switches 132 and diodes 134 is a .0047 micro farad capacitor in series with one of the TI--T1Z outputs of counter and decoder circuit 11 in Figure 3.

Thus, each of the twelve key switches representing one semi-tone of the octave is connected to a different T output of counter and decoder 11 so that each time a key switch is closed, a T pulse representative of the time slot of that particular note is applied to NAND gate 138. NAND gates 138 and 140 act as an RS flip-flop to clean up the output signal to assure that regardless of the noise level of the circuit, the T output is latched until the CK2 output goes negative (at the end of each T pulse) and resets the RS flip-flop.

The multiplexer 12 illustrated in Figure 4, corresponds to one octave of the accompaniment manual of the organ. The output of NAND gate 138 is connected to the Al input of NAND gate 142 in multiplexer circuit 15. The other input of NAND gate 142 is connected to the 01 (first octave) output from NOR gates 128 in counter and decoder circuit 11. Similarly, NAND gates 143-147 are respectively connected at one input to 02, 03, 04, 05 and 06 outputs and the other input is connected to the second, third, fourth, fifth, and sixth accompaniment octave multiplexer circuits (not shown) at inputs A2, A3, A4, A5, and A6 to produce a time division multiplex signal identified ACC corresponding to the keys played on the accompaniment manual.

Similarly, six NAND gates 148 receive six octaves of solo manual T inputs which are NANDed with 01--06 -to provide a time division multiplex signal Identified Solo corresponding to the keys delayed in the solo manual. The output of the accompaniment manual NAND gates 142-147 are combined on a single lead which is marked ACC which is connected to one input of NOR gate 152. The outputs of NAND gates 148 are combined on a single lead marked Solo which is connected to one input of NOR gate 150. The other input of NOR gate 150 is connected to the MT output of NAND gate 129, and the M2 output of NAND gate 130 is connected to the other input of NOR gate 152.The output of NOR gates 150 and 152 are connected to the inputs of NOR gate 154, and NOR gate 154 produces at its output on lead 42 a time division multiplex serial digital logic train of signals representative of the note, octave, and manual of the actuated key switches. This output signal of NAND gate.. 154 is identified by the mnemonic SA. It can be seen that the combination of signals 01--06 and signals T1--TIZ combine to define 72 time slots (6 times 12) for each manual and a total of 144 time slots (2x72) for both the solo and accompaniment manuals.Thus, each key switch on the accompaniment and solo manual has a corresponding time slot which is identified by the serial digital logic train With reference to Figures 5 and 6, the Q3-Q6 inputs in the upper lefthand corner of Figure 6 are connected to the same marked outputs in Figure 3 and Q7-Q9 are connected to the corresponding outputs in Figure 4. The input identified M1 Figure 6 is connected to the corresponding output of NOR gate 154 in Figure 4. The serial data train is applied to NOR gate 160 which gates SA to the data (D) input of flipflop FF13. The clock (CK) input of FF13 is connected to CK2 output of clock 10 (Figure 2).Thus, the SA data train is clocked through FF13 by CK2 but each bit of data is delayed one time slot (since CK2 occurs at the end of each T pulse) to synchronize the frequencies produced by the top octave frequency generator and dividers 25 with the outputs from the programmable counters 20 as will be more fully described below.

The 06 output from NOR gates 128 in Figure 4 is applied to one input of NAND gate 162. The other input of NAND gate 162 receives the output of NAND gate 164.

Applied to one input of NAND gate 164 is the T0 output from counter and encoder circuit 11 in Figure 3, and the other input of NAND gate 164 receives Mn logic data from NOR gate 166 which is the negative true logic for the selected manual ( or M2). Thus, NAND gate 162 and NOR gate 164 follow the Boolean logic equation (T10), (M) (06). This logic equation decodes time slot 70 for either the solo or the accompaniment manual (i.e., the tenth note of the sixth octave). Time slots ldl are used to scan the keys for one manual during M1, and then for the other manual during M2. This information is delayed to time slots 2 through 62 by FF13 as noted above.

M1 - from NAND gate 129 in Figure 4 is applied to the M1 input to NOR gate 168 in Figure 6. M2 from NAND gate 130 in Figure 4 is applied to the M2 input to NOR gate 170 in Figure 6. The other inputs of NOR gates 168 and 170 are respectively connected to solo and accompaniment switch contacts 169 and 171 in solo and accompaniment selector switch 172.

Contacts 169 and 171 are respectively connected through 3.9 k resistors 173 to an appropriate voltage source V to provide logic signals for NOR gates 168 and 170. As can be seen, when switch 172 is moved to the solo position, lead 174 is brought to logic zero but lead 176 remains at logic one.

Thus, when MT goes to logic one, the output of NOR gate 168 goes to logic zero and when M1 goes to logic zero, the output ofNOR gate 168 goes to logic 1. Thus, NOR gate 168 acts as an inverter of the M1 signal. At the same time, since lead 176 is at logic one, the output of gate 170 remains at zero irrespective of the M2 logic state. The output of NOR gate 168 is applied to one input of NOR gate 178. The other input of NOR gate 178 is connected to the output of NOR gate 170. Thus, since the output of NOR gate 170 remains a logic zero while the switch 172 is in the solo position, NOR gate 178 acts as an inverter so that the output of NOR gate 178 is once again M1.The output of NOR gate 178 is applied to one input of NAND gate 180, the other input of NAND gate 180 is connected to the output of NAND gate 182. NAND gate 182 is connected to the solo and accompaniment contacts 169 and 171 of switch 172. In the present hypothetical case, since switch 172 is in the solo position, one input of NAND gate 182 is at logic zero and the other is at logic one. Thus, the output of NAND gate 182 is logic one. When switch 172 is in the off position both inputs of NAND gate 182 are at logic one. Accordingly, it can be seen that the outout of NAND gate 182 is zero if switch 172 is off and logic one if switch 172 is in either the solo or accompaniment positions. Accordingly, NAND gate 180 operates to invert the output of NOR gate 178 only when switch 172 is in either the solo or accompaniment positions.

NOR gate 166 inverts the output of NAND gate 180 so that the output Mn goes to logic one when MT goes to logic one and to logic zero when M1 goes to logic zero.

Similarly, if switch 172 is moved to the accompaniment position, Mn goes to logic one when M2 is applied to NOR gate 164 tc decode time slot 70 for the selected manual.

The output of NAND gate 162 is connected to the preset (PRE) input of flipflop FF14 and the clear (CLR) inputs of flip-flops FF15 and FF16. Thus, at time slot 70, the Q outputs of flip-flops FF14, FF15, and FF16 are set to logic one, zero zero (when no keys are being scanned). The serial multiplex data train is combined with manual time slot Mn to produce SAM data applied to the data (D) input of FF13.

SAM is clocked through FF13 upon each CK2 clock pulse and cleared by each CK3 pulse so that the data remains at the Q output only during the appropriate time slot. The Q output of FF13 is connected to the clock inputs of FF14, FF15 and FF16.

Thus, the first serial data pulse representing a closed key switch is clocked through FF13, and at the trailing edge of this pulse, and Q outputs of FF14, FF15 and FF16 are clocked to zero, one, zero respectively. The second data pulse of SAM representative of the next actuated switch clocks the Q outputs of FF14, 15, and 16 respectively to zero, zero, one. A third data pulse of SAM clocks the Q output of FF14, 15 and 16 to zero, zero, zero. The Q output of FF14 is directly connected by lead 190 to first data (1 D) input of integrated latch circuit L 1.

Latch circuit L1 is sold under the commercial designation 7475. The second data (2d terminal) of latch circuit L1 is connected to the output of NAND gate 192 one input of which is connected to the output of FF14 and the other input of which is connected by lead 191 to the Q output of FF15. The third data (3D) input of latch circuit L1 is connected to the output of NAND gate 194. The 3 inputs of NAND gate 194 are respectively connected to the Q outputs of FF14, FF15, and FF16. Thus NAND gates 192 and 194 decode the outputs of FF14, FF15 and FF16. NAND gate 196 is connected to the 06 and T8 outputs and also receives H or key enable data from the monostable circuit 198 (which will be more fully described hereinafter).

The output of NAND gate -196 is connected to one input of NOR gate 200 the output of which is connected to the G or gate enable inputs of latch circuit L1. The other input of NOR gate 200 received Mn data from NOR gate 166. Thus, it can be seen that at the 68th time slot (06-T8) of the selected manual (Mn) the data inputs on the 1D, 2D, and 3D inputs of latch circuit L1 are gated to the Q outputs of latch circuit L1. If no keys have been played, the GEB1 (1Q) GEB2 (2Q) and BE3 (3Q) outputs of latch circuit L1 will be zero.

These outputs follow the following logic equations GBE1=lD=Q14, GBE2=2D=(Ql4) (Q15), BE3=3D=(QP4) (W) (Q16).

If one key is played, GBE1 goes to logic one and GBE2 and BE3 stay at logic zero. If two keys are placed, GBEI and GBE2 go to logic one and BE3 stays at logic zero. If three keys are played, GEB1, GEB2, and BE3 go to logic one.

NOR gate 202 also receives Mn data and the output of NAND gate 196 so that the logic output of NOR gate 202 designated SSCC (steady state cycle complete) is at logic one when 06, T8, H, and Mn equal one. This logic corresponds to the unused time slot 68, the system not in hold, the manual being scanned corresponding to the manual to which the system is coupled, i.e., the appropriate manual selected by switch 172.

NOR gate 204 has one input grounded and the other input connected to the output of NAND gate 206. The output of NOR gate 204 is identified as steady state valid data (SSVD). SSVD equals logic one when Q13, H, and CK5 equal one. This state corresponds to a played key being scanned, the system in steady state (not in hold), and the data is valid, i.e., CK5 equals one. CK5 goes to logic one at the center of each T time slot (see Figures 8A and 8B) so that data is valid only after initial transients have subsided.

The SSVD output of NOR gate 204 is connected to the G or gate enable inputs of integrated latch circuits L2 and L3. As previously pointed out, the inputs of L2 and L3 receive Q3-Q9 data. The SSCC data from NOR gate 202 is connected to the gate enable inputs of integrated latch circuits L4 and L5. Integrated latch circuits L2 through L5 are commercially available integrated circuits sold under the designation 7475.

Flip-flops FF1 3-FF 17 are integrated.

circuits sold under the designation 7474.

It can be seen, therefore, that each time the Q output of FF13 goes to logic one, i.e., at each time slot representative of a played key (delayed one slot of FF13), and the other conditions are satisfied, (H=CK5=l), SSVD goes to logic one clocking the Q3 through Q9 data on the inputs of L2 and L3 through the latch circuits to the Q outputs of L2 and L3. This will occur each time a note is scanned until ultimately the Q3-Q9 data representative of the highest note played on the selected manual will be present at the Q outputs of L2 and L3. At the conculsion of the scan cycle, SSCC goes to logic one so that latch circuits L4 and L5 clock through to their outputs the data representative of the highest note played.

Thus, information representative of the highest note played is present at the outputs of L4 and L5 at the completion of the cycle.

This data is applied to a series of seven Exclusive OR gates 208. The outputs of Exclusive OR gates 208 are connected in parallel to the inputs of a NAND gate 210.

The other inputs of Exclusive OR gates 208 are connected to the corresponding Q3-Q9 inputs as indicated. When the high note data latched by L4 and L5 is the same as the Q data on inputs Q3-Q9 on the next scan, the outputs of Exclusive OR gates 208 go to logic one simultaneously so the output of NAND gate 210 goes to logic zero. This state occurs only at the time slot representative of the highest note played.

The output of NAND gate 210 identified HN is applied to one input of NOR gate 212 which decodes the CLEH (counter latch enable high) output. The other input of NOR gate 212 is connected to NAND gate 206 which decodes the Q output of FF13 during the CK5 and H equal to one state.

CK5 goes to logic 1 approximately half-way in between CK2 pulses. Thus, CK5 clocks the Q output of FF13 through NAND gate 206 approximately halfway between successive clocks of FF13. Thus, the Q output of FF13 has had an opportunity to reach a steady state before that data is clocked through NAND gate 206. The output of NAND gate 206 is the complement of steady state valid data or SSVD.

With reference to Figure 6, memory 17 comprises an integrated circuit random access memory (RAM) sold under the commercial designation 2102. The A data from Figure 4 is also applied to the data (Din) input of RAM 220. The Q3 through Q11 outputs of flip-flops FF3 through FF11 (from Figures 3 and 4) are applied to the A0 through A8 inputs of RAM 220. The A9 input is grounded and the read/write (R/W) input is connected to the CK clock output of clock 10 in Figure 2. The data out (Dout) output of RAM 220 is connected to one input of Exclusive OR gate 222 in comparator circuit 16. The other input ~ of Exclusive OR gate 222 is connected to SA lead 42.If CK3 is logic one, RAM 220 is reading out data and when CKB is logic zero, the RAM 220 is writing in data. As previously pointed out, logic one of CK5 is the time slot when valid data is being transmitted through the system. With reference to Figure 8A, it can be seen that CK pulses do not occur at the same time that CK5 is at logic one. Thus, RAM 220 records or writes in data only at a time after CK5 has sampled previous data and reads out data at the same time CK5 clocks valid data.

The output of exclusive OR gate 222 is connected to one input of NAND gate 224.

The other input of NAND gate 224 is connected to the CK5 clock output of clock 10 (Figure 2). Since Exclusive OR gate 222 will only present a zero output when the data on the data output of RAM 220 is the same as the data of SA, the output off NAND gate 224 will equal one when SA equals data (Dout) of RAM 220 or when CK5 is at logic zero. The data output of NAND gate 224 is identified SCH and will only be at logic one when the notes played during the previous scan are the same notes being played during the current scan. If the played notes have changed, SCH goes to logic zero during CK5 since the inputs to Exclusive OR gate 222 are not equal. SCH is applied to one input of NOR gate 226, and the other input is connected to the Mn output of NOR gate 178. Thus, the output of NOR gate 226 identified SCHM goes to logic one when the SCH' equals logic zero and Mn equals logic zero.

NOR gates 228 and 230 form an RS flipflop. One input of NOR gate 232 receives time slot 70 data from NAND gate 162 and the other input is connected to the collector of transistor Tl. Normally, when no keys are played, their output of latch Ll is at logic one (eBf=l), H is at logic one and transistor Tl is biased "on". When a key is first played from the manual to which the logic is coupled by switch 172, SCHM goes to logic one and H goes to logic zero. When H goes to logic 0, transistor Tl is turned "off" through the coupling action ~ of capacitor 234 and resistor 236. Since GBE1 is high, both resistors 238 and 240 charge capacitor 234 towards +5 volts. As a result, transistor Tl turns "on" for about 15 milliseconds.When it does, NOR gate 232 decodes a logic one when transistor Tl is "on" and when time slot 70 corresponding to a selected manual Mn occurs, the output of NOR gate 232 resets RS flip flop 230 and 228 and H goes to logic one. If subsequent deletion of keys sets H to logic zerp, H remains logic zero fora proximately 40 milliseconds since G1Eg equals zero and only resistors 240 would charge capacitor 234. The reason for the 40 millisecond delay when keys are released is that it takes longer for the organist to release keys than it does to initially play keys. As long as H is logic zero the system is in hold since no data can be clocked through NAND gate 206.Once H goes to logic one after a key is played, the data corresponding to the played keys is clocked at each CK5 pulse to the counter latch enable outputs CLE1, CLE2, CLE3 and CLEH in the following manner.

CLEI is decoded and determined by NAND gate 206, NAND gate 250, and NOR gate 252. It can be seen that if only one key has been played, GBE2 is logic zero so that NAND gate 250 produces a logic one output to one input of NOR gate 252. Thus, the output of NOR gate 252 remains at logic zero as long as only one key is played.

However, if two or more keys are played, GBE2 is at logic one. Thus, CLE1 follows the following logic equation: CLEI=GBE2 (Q14) (H) (Q13) (CK5) According, if two or more keys have played in the previous scan, at the time slot of the first key played when CK5 goes to logic one, CLEI will go to logic one. Thus, CLE1 goes to logic one for the lowest or first note played when two or more notes are played but remains at logic zero if only one key is played.

CLE2 is decoded by NAND gate 254, NAND gate 256, NAND gate 258, NOR gate 260 and NAND gate 206. CLE2 follows the logic equations:- CLE2=(Q15) (Q13) (H) (CK5) (BE3), CLE2=(BF) (CLE1) The later equation corresponds to two keys being played since BE3 equals logic one for less than three keys and CLE1 equals logic one for two or more keys played as defined above.

CLEH is decoded by NOR gate 212 and NAND gate 206. Thus, CLEH follows the equation: CLEH=(HN) (H) (Q13) (CK5) Thus, it can be seen that CLEH goes to logic one only during the time slot of the highest note played.

CLE3 is decoded by NAND gate 261, 262, 264, NOR gate 266 and NAND gate 206 in accordance with the following logic equations:- CLE3=(Q13) (Q16) (H) (CK5) (BE3) CLE3=(BE3) (CLEH) The first equation corresponds to a played key being scanned, the system not in hold, data valid, the third key slot enabled, and three or more keys played on the previous scan. If EF and CLEH equals one, CLE3 equals CLEH equals 1. This corresponds to less than three keys being played on the previous scan; therefore, CLE3 and CLEH go to logic one for the time slot of the highest note played when less than three keys have been played. -The following table indicates the corresponding note time slots for which the CLE outputs go to logic one when 1, 2, 3 or more keys are played.

KEYS PLAYED I KEY 2 KEYS 3 OR MORE KEYS CLE1 disabled lowest note lowest note CLE2 disabled lowest note second note CLE3 highest note highest note third note CLEH highest note highest note highest note With reference to Figures 7A, 7B, 7C, and 7D; CLE1, CLE2, CLE3, and CLEH from Figure 5 are applied as indicated in Figure 7A. Also, Q7, Q8, and Q9 outputs from FF7, FF8, and FF9 in Figure 4 are connected as indicated. The TZ through 1M outputs from counter and decoder 11 in Figure 3 are connected as indicated in Figure 7A. CLE1 through CLEH go to logic 1 during the time slot of the played keys in accordance with the previous table. The Q=7, Q8 and Q9 data is the data that decodes into the respective octave time slots (01--06).TZ through T12 is decoded bv eight NAND gates 270 into Dl, D2, DS, D4, D5, D6, D7, and D8 data in accordance with the truth table chart in Figure 10A. Four programmable counters 22,274,276, and 278 are respectively connected as indicated in Figure 7B, 7C and 7D. The four programmable counters are identical Internally so only programmable counter 272 will be described. Integrated circuit latches 280, 282 and 284 are commercial type 7475 integrated circuits. The gate enable (G) inputs of latches 28-284 are connected to CLEI. The data inputs (1D--4D) of latches 280 and 282 are connected as indicated to Dl through D8.

The three data inputs 1 D-3D) of latch 284 are connected to Q, Q8, and Q9 as indicated. The logic state of Dl-D8 at any given moment of time is a function of the inputs 'I'2-. Figure 10A indicates the status of the respective Dl-D8 lines for each time slot corresponding to TT through Tut2. As previously pointed out, CLEI goes to logic one during the time slot for the first played note when two or more keys are played. When this logic one is applied to the G inputs of latches 280--284, the data on the data inputs at that time is clocked through to the indicated Q outputs of latches 280, 282, and 284.The Q outputs of latches 280 and 282 are connected to the data inputs (1 D4D) of integrated circuit presettable binary counters 286 and 288.

These binary counters are commercial type 74197. The output of counter 286 is connected to the clock input of counter 288 and the output (Q4) of counter 288 is connected to flip-flop 290. The Q output of flip-flop 290 is connected to the clock (CK) input to flip-flop 292 and flips-flops 294, 296, 298 and 300 are all connected for divide-by-two operation. Flip-flops 290--300 are all commercial type 74107 JK flip-flops. The Q output of flip-flop 290 is also connected through capacitor 302 to the count/load (C/L) input of counters 286 and 288. The clock (CK) input of counter 286 receives master frequency one (MFI) which is a relatively fixed frequency of approximately 2 megaHertz.This MFI frequency is supplied by rate scaler frequency generator 22 connected to the master frequency generator 23 of the system and can be varied slightly at a subaudio rate to produce vibrato effects as well as varied to slightly detune the output to enhance the ensemble effect.

Counters 286 and 288 and flip-flop 290 are connected to operate as a nine bit counter and operate to count to 512 (2 to the ninth power). Thus, counters 286 and 288 and flipflop 290 operate to divide Mfl by 512. The D inputs of counters 286 and 288 are the true inputs which program these counters. Thus, depending upon the input logic state of the D inputs, the count of counters 286 and 288 can be varied.

Looking at Figure 10A, it can be seen that the Dl through D8 true code (inverting D2 and D3) for time slot Tl is the binary number for the number 6 (0000110). Thus, counters 280 and 282 are programmed to count by the number 512 minus 6 or by 506 (see the N column of Figure 10A). The number 6 is loaded into the counter at the end of each cycle when the Q output of flipflop 290 transfers a negative pulse to the CIL (Count/Load) input of counters 286 and 288 via capacitor 302. The C/L input is normally biased to a logic one by resistors 303 and 304 and diode 307. The junction of diode 307 and resistor 305 is bypassed by capacitor 309.Similarly, taking any of the other T time slots and finding the true binary number representative of the D code for that time slot, it can be seen that the number in the N column of Figure 10A is the number by which counters 286 and 288 are programmed to divide MFI if CLE1 goes to logic one during that T time slot.

MF1 when divided by these numbers N produces the 12 semitones of the top octave of the manual. Flip-flops 292, 294, 296, 298 and 300 divide this frequency down to the each of the lower octaves. As can be seen, each of the Q outputs of flip-flops 29--300 are respectively connected to one of 6 NAND gates 304 in Figure 7C. The other two inputs of NAND gates 304 are connected to the Q outputs of latch 284.

The state of the Q outputs of latch 284 when clocked by CLEI represents the state of the (W7, Q9, and Q8 inputs which determines the octave time slot in which the actuated key is located. This data is applied to NAND gates 304 so that only the NAND gate corresponding to the octave of the played key will be enabled to pass that frequency to the output fl.

Figure 10B indicates the truth table logic of the Q7, Q9 and Q8 lines for each of the octave time slots 01 through 06. Assuming the first note time slot TT for the first octave 01 was the lowest note played, it can be seen that MF1 would be divided by 506 and then divided by flip-flops 290 through 300. The 0, 0, 0, inputs on latch 284 would be clocked through at CLEI so that the Q outputs would be at zero and the Q outputs are at one. It can be seen that only the NAND gate 304 connected to the Q output of flip-flop 300 representing the first or lowest octave will be enabled to pass the frequency of the Q output of flip-flop 300. The other NAND gates 304 are turned off.Similarly, all of the other NAND gates 304 are connected only in such a way that they are enabled to pass their respective divided frequency if the state of the Q inputs at the time of CLE1 is such to indicate that a key in that octave has been played.

The digital to analogue converter 271 converts the digital data of programmable counter 272 to analogue voltage V1 as follows. The Q and Q outputs of the latch 284 are also respectively connected to NAND gates 306 and 308 and inverters 310, 312 and 314 respectively as indicated in Figure 7B. The outputs of NAND gates 306 and 308 are connected in series to 17.8 K resistor 316 and 53.3 K resistor 318.

Inverters 310, 312 and 314 are respectively connected to 120 K resistor 320, 240 K resistor 322 and 480 K resistor 324. A 480 K resistor 326 is connected from ground to the common bus 328 connected to all of resistors 316-326. Bus 328 is connected to the emitter of transistor 330 in Figure 7C.

The base of transistor 330 is connected through a I K resistor 332 to a five volt source. The base is also connected through a 2.7 K resistor 334 to the 4Q output of latch 282 and through a 5.6 K resistor 336 to the 3Q output of latch 282. The 3Q and 4Q outputs of latch 282 represent the D7 and D8 data clocked through latch 284. This data controls the biasing of transistor 330 to transistor on. The base voltage of transistor 330 follows the values under column K in Figure 10A. The collector of transistor 330 follows the values under column K in Figure 10A. The collector of transistor 330 is connected to the input of an operational amplifier 338 and the output of amplifier 338 has been labelled Vl.The output of voltage Vl follows the following equation: Vl=30 K/M+5 where K is the value shown under the column K in Figure 10A for the played note time slot, and M is the multiplying factor M shown in Figure 10B for the particular octave of the played note.

The output frequency F1 follows the following equation: MF1 F1= NM where MFI is the frequency at the MF1 input, N equals the number under the N column in Figure 10A for the particular T time slot, and M equals the multiplying factor M in Figure 10B for the octave of the played note.

Programmable counters 274, 276, and 278 operate in the same manner as previously described with respect to programmable counter 272. Programmable counter 274 receives a master frequency MF2, programmable counter 276 receives a master frequency MF3, and programmable counter 4 receives a master frequency of MFH. The output voltage VH from programmable counter 278 controls the amount of rate scaling by rate scale frequency generator 22 so that input frequencies MFI, MF2, MF3, and MFH may be shifted very slightly to detune these frequencies very slightly to enhance the orchestral effect, as will be described later.

The amount of frequency shift at the lower frequency end is by a greater percentage than at the higher frequency end but not enough to give a fixed difference frequency.

The four output frequencies fl, f2, f3, and flI and the four voltages V1, V2, V3 and VH are applied to the voltage controlled gate and filter circuits 21.

With reference to Figure 14, a more detailed block diagram of the rate scaler frequency generator 22 is illustrated.

Master frequency generator 23 provides on three separate leads 352, 354 and 356 frequency signals designated f, f, and fm.

The fm output is also connected on lead 358 to the top octave frequency generator dividers 25. Leads 352, 354, and 356 are connected to rate scaled frequency shifters 360, the operation of which will be described below. Rate scaler frequency generator 22 also comprises a vibrato oscillator 362 which is a conventional vibrato oscillator which generates a vibrato signal at approximately 6 Hertz in the manner to be hereinafter described.

Vibrator oscillator 362 is connected by alead 364 to a vibrato voltage controlled oscillator 366. The vibrato voltage controlled oscillator 366 generates an output signal fv at a frequency which is approximately proportional to the magnitude of the input vibrato voltage qn lead 364 as illustrated in Figure 15. The fv signal is applied on lead 368 to the rate scale frequency shifters 360 and vibrator voltage controlled oscillator 366 also applies a logic voltage signal V5 on lead 370 to rate scale frequency shifters 360.

Rate scale frequency generator 22 also comprises a control voltage generator 372 which receives the VH signal on lead 56 from the programmable counter circuits 20 and also GBE2 and GBE1 signals from the mono and enable logic circuit 19. VH is a tracking voltage which is proportional to the frequency of the oscillator assigned to the highest note being played as previously described. GE and GBE2 are signals representative of the number of keys played as previously described. Control voltage generator 372 provides two output signals on leads 374 and 376 to control ensemble voltage control oscillator 378. Ensemble voltage control oscillator 378 provides two output signals f delta and 1/2 f delta on leads 380 and 382 to rate scale frequency shifters 360 for the purposes that will hereinafter be more fully described.Rate scale frequency shifters 360 receive the respective signals on leads 352, 354, 356, 368, 370, 380 and 382 to provide output frequency signals MF1, MF2, MF3, and MFH which are applied to the programmable counter circuits 20 as previously described.

With reference to Figure 16, master frequency generator 23 is a conventional tunable LC oscillator and divider circuit comprising a tuneable choke coil 384, capacitor 385, resistors 386 and 387, integrated circuit inverter amplifiers 388, 389, 390, 391, and integrated circuit divider 392. The output of inverter amplifier 390 is a square wave signal f on lead 352 as illustrated in Figure 22. Inverter 391 inverts that signal to produce its complement f on lead 354 as illustrated in Figure 22 and divider 392 divides that signal by two to produce fm on lead 356 illustrated in Figure 22.

With reference to Figure 17, a detailed schematic circuit diagram of the vibrato oscillator 362 is illustrated. The voltage on lead 394 is the supply voltage which turns the vibrato oscillator "on" and controls the amplitude of the output vibrato signal on lead 364. The voltage on lead 396 is a reference voltage used for the purpose that will be more fully described below. Lead 396 is connected to the emitter of transistor 398 whose base is biased by the voltage developed across voltage divider resistors 400 and 402. Transistor 398 also has an emitter load resistor 404 and a collector supply resistor 406.

Lead 396 is also connected to the emitter of transistor 408 which is a temperature sensitive transistor. The base emitter drop of transistor 408 is compensated by the base emitter drop of transistor 398. This compensation maintains a nearly constant threshold voltage at the base of transistor 408, and accordingly, a stable vibrato output frequency.

Assuming that the voltage on lead 410 to the base of transistor 408 and the voltage on lead 418 at the collector of transistor 408 are at ground potential, transistor 408, transistor 412, and transistor 414 are all biased "off' and transistor 416 is biased "on". The voltage on lead 418 connected to the collector of transistor 408 and the base of transistor 412 will charge positively through resistor 420 and 422, and when the voltage on lead 418 reaches approximately 0.5 volts, transistor 412 is biased "on" passing current from lead 394 through collector supply resistor 424 and emitter load resistor 426 to ground. At approximately one volt, transistor 414 is also biased "on" thereby effectively grounding the base of transistor 416 through resistor 428 turning transistor 416 "off".

Capacitor 430 commences charging through resistor 420 and resistor 432 raising the voltage on lead 418 thereby causing transistors 412 and 414 to be biased "on" more substantially. The voltage on lead 418 is clamped by the base to emitter drop of transistors 412 and 414 and the voltage on lead 410 is charged positively. At about one volt, transistor 408 is biased "on" clamping the voltage on lead 410 and driving the voltage on lead 418 negatively. This causes transistors 412 and 414 to turn "off" and transistor 416 turns "on" driving the voltage on leads 410 and 418 back to ground potential.

Accordingly, one cycle of the vibrato oscillator has now been completed and the parameters are back to the initial assumed state of ground potential on leads 410 and 418. The output vibrato signal is coupled through a capacitor 436 and developed across a reference resistor 434 on lead 364.

The reference voltage on lead 394 is developed from the 27 volt voltage source at point 437 through the collector supply resistor 438 and the emitter load resistor 440 connected across transistor 442. When transistor 442 is biased "on", reference voltage across resistor 440 is applied to lead 394 and when transistor 442 is biased "off", lead 394 is essentially grounded through resistor 440.

When the input GBE1 is at a logic "one" (no notes played), transistor 444 is biased "on" by diode 446 and resistor 448. The base of transistor 442 is grounded through transistor 454 biasing transistor 442 "off" so that the reference voltage on lead 394 is grounded turning the vibrato oscillator "off". When the first note is played GBE switches to "zero" logic, and capacitor 450 starts charging through resistor 452 and resistor 454 until the IR drop across resistor 454 is less than one diode drop and transistor 444 is biased. Thus, the voltage at the base of transistor 442 approaches the voltage on lead 456 slowly so that transistor 442 is turned "on" slowly. The final voltage on lead 394, lead 456, and the base of transistor 442 is determined by resistor 458, and the setting of variable resistor 460, when transistor 462 is biased "on", and by the setting of variable resistor 460 when transistor 462 is biased "off". Transistor 462 is biased "off' when GBE3 is at logic "one" and is biased "on" when OBE3 is at logic "zero". When the first note is played, G1WFT switches to logic "zero", and the vibrato oscillator turns "on" slowly in a delayed mode. When more than two notes are played, OBE3 switches to logic "one", transistor 462 is biased "off" so that increased voltage is applied on lead 456, and the magnitude of the vibrato oscillator output signal is increased.

With reference to Figure 18, a detailed circuit diagram of the vibrato voltage control oscillator 366 is illustrated. The output of the vibrato oscillator 362 is applied on lead 364 through capacitor 464 to the junction of resistors 468 and 470.

Capacitor 472 is connected from the other side of resistor 470 to ground. Lead 466 is connected from resistor 470 to the base of transistor 474, and lead 476 is connected to the junction of resistors 477 and 478.

Resistors 477, 478, diodes 479 and 480, and resistor 481 are connected between +27 volts and +5 volts to establish low impedance reference voltages V2 and V4.

Transistor 474 is biased at its base by V2 through resistors 468 and 470. Capacitor 464 is a direct current blocking capacitor and capacitor 472 and resistor 470 filter the vibrato signal to obtain a nearly sinusoidal input to the base of transistor 474. The emitter of transistor 482 is at voltage V4.

Resistor 473 is a current limiting supply resistor for transistor 474.

When no vibrato input signal is applied on lead 364, transistor 474 is biased such that very little current flows through resistors 484 and 486 so that voltage V6 is approximately one base to emitter drop of transistor 482 below voltage V4. If transistor 482 is biased "on", resistors 488 and 489 divide the current from transistor 482 so that transistor 490 is biased "on" and transistor 482 is held "on" by the voltage caused by current flowing through resistor 491. If transistor 482 is biased "off", transistor 490 is also biased "off", and diode 492 supplies enough current through resistor 491 and resistor 493 to hold transistor 482 "off". This slight hysteresis effect prevents transistors 482 and 490 from oscillating erratically.

A slight increase in the voltage V8 on lead 466 turns transistors 482 and 490 "off". As voltage V8 increases, voltage V10 on 1-ad 494 is clamped by diode 496 (i.e., one diode drop above five volts), and the current increases through resistor 484 and transistor 498, as well as through resistor 486 and transistor 499. When voltage V8 swings back to normal voltage bias (i.e., V8 equals V2), a slight decrease in voltage turns transistors 482 and 490 "on". As voltage V8 decreases, voltage V6 on lead 493 is clamped by transistor 482, and voltage V4 across the base to emitter junction of transistor 482.

Diodes 500 and 502 and resistors 503 and 504 cause voltage V10 to be biased negatively increasing the current through resistor 484 and transistor 498 as well as through resistor 486 and transistor 499.

From the foregoing, it can be seen that the collector current from transistor 498 and transistor 499 increases with the magnitude of the difference between voltages V8 and V2 (i.e., V8 minus V2 greater than zero or V2 minus V8 greater than zero). Voltage Vs on lead 370 is above ground "high" when V8 minus V2 is positive and transistor 490 is biased "off", and is grounded "low" when V8 minus V2 is negative and transistor 490 is biased "on".

For further purposes of explanation, assume initially that voltage V14 on lead 504 equals ground and equals voltage V16 on lead 505. In this situation, transistors 506, 507 and 510 are biased "off" and transistors 508 and 509 are biased "on". The collector current from transistor 499 charges capacitors 511 and 512. Voltage V16 will then increase linearly. When voltage V16 equals one diode drop across transistor 507, it starts to turn "on" and voltage V18 will decrease to three halves of a diode drop across transistor 507. Resistors 518 and 513 will then bias transistor 509 "off"; When transistor 509 turns "off", resistor 514 and capacitor 512 supply additional current to speed up the switching action of transistor 507 when the collector current of transistor 499 is barely enough to turn transistor 507 "on".When transistor 507 is turned "on", both voltage V14 and voltage V18 equal zero, and voltage V16 is clamped at one base to emitter diode drop across transistor 507. Transistors 506, 508, and 509 are biased "off" and transistors 507 and 510 are biased "on". Resistor 517 is a collector supply resistor for transistor 510.

The collector current of transistor 498 now charges capacitor 511 and voltage V14 becomes positive. The collector current from transistor 598 through capacitor 511 adds to the current from transistor 499 insuring that transistor 507 remains biased "on". Voltage V14 increases until transistor 506 is biased "on" and voltage V14 is clamped to one base to emitter drop across transistor 506. When transistor 506 turns "on", voltage V16 starts to decrease.

Voltage V18 starts to increase until resistors 515 and 516 bias transistor 508 "on". The resulting decrease in voltage V14 is coupled through capacitor 511 to switch transistor 507 "off" and switch transistor 508 "on" very hard. Voltage V14 and voltage V16 now equal zero as originally assumed and the cycle repeats.

The output of transistor 510 is at a frequency v which oscillates at a frequency directly related to the magnitude V8 minus V2 as illustrated in Figure 15. As pointed out previously, output logic signal voltage vs is at logic "one" when V8 minus V2 is greater than zero and at logic "zero" when V8 minus V2 is less than zero.

With reference to Figure 20, a detailed circuit diagram of the ensemble voltage control oscillator 37 is illustrated. This circuit is virtually identical to the right hand portion of the circuit illustrated in Figure 18 and there is a direct comparison by component correlation. In Figure 20, transistors 520, 521, 522, 523, and 524 respectively correspond to transistors 508, 506, 507, 509, and 510, in Figure 18. Capacitors 526 and 527 in Figure 20 directly correspond to capacitors 511 and 512 in Figure 18. Similarly, resistors 528, 529, 530, 531, 532 and 533 correspond to resistors 515, 513, 514, 517, 518, and 516 in Figure 18.

This circuit operates in the same manner as the Figure 18 circuit and the output from transistor 524 is at a frequency f delta on lead 380. An integrated circuit divider 534 divides f delta to produce one-half f delta on lead 382.

With reference to Figure 19, a detailed circuit diagram of the control voltage generator 372 is illustrated. Input voltage VH is the tracking voltage the magnitude of which is proportional to the frequency of the oscillator assigned to the highest note being played as previously described.

Voltage VH is applied through resistor 540 to the base of transistor 541. Transistor 541 inverts VH and supplies current on lead 543 which current is limited by resistor 542, diode 545, resistor 544, and resistor 546.

Resistors 544 and 546 form a voltage divider. When the voltage on the cathode of diode 545 is positive with respect to the voltage on the anode of diode 545, diode 545 is reverse biased and the voltage on the anode is approximately 13 volts. When VH decreases (with decreasing frequency), the voltage on the cathode of diode 545 goes negative and diode 545 is forward biased so that the gain of transistor 541 is increased.

Resistor 548 is connected between the +27 volt supply and lead 549. Lead 549 is connected to resistors 550 and 552.

Resistors 550 and 552 split the current on lead 549 and apply that current by leads 374 and 376 to each side of capacitor 526 in Figure 20. The normal current supplied by resistor 548 is sufficient to establish a minimum frequency f delta of approximately 2.5 KHz. When VH swings negative from approximately 21 volts to 5.5 volts, the frequency f delta increases from 2.5 KHz to 8 KHz.

When more than one note is played, GBE2 goes to logic "one" biasing the base of transistor 549 "on" through resistors 554 and 556. This grounds the cathode of diode 545 and the frequency of F delta is reduced to the range 2.5 KHz to 4 KHz.

When the first note is played, GBE1 goes to logic "zero" thereby grounding the voltage supplied by the 5 volt supply through resistor 558. The base of transistor 559 is switched negative with respect to + 14 volts by capacitor 561 and then charged exponentially through resistor 560 to +14 volts as capacitor 561 charges. The exponential base voltage generates an exponential current on lead 563 through transistor 559 and resistor 562. This current is split by diodes 565 and 567 and resistors 564 and 566 and applied by leads 374 and 376 across capacitor 526 in Figure 20. This causes F delta to be transiently increased to 30 KHz during the onset of the fast attack voices. The transient is negligible by the time the slow attack voices are on.

With reference to Figure 21, a detailed schematic diagram of the rate scale frequency shifters 360 is illustrated. The input leads 368 and 370 forT and Vs are from Figure 18 and input leads 380 and 382 for f delta and one-half f delta are from Figure 20. Assuming Vs is at a logic "one" (i.e., V8-V2 is greater than zero), NAND gate 570 inverts fv to its compliment fv on lead 572. The wave form of fv and the other wave forms relating to Figure 21 are illustrated in Figure 22. The input frequency fm to exclusive OR gate 574 is at 2 MHz and the input fv is a maximum of 30 KHz.

Therefore, Figure 22 shows the wave forms just before and after transitions of fv.

Exclusive OR gate 574 operates such that when the input on lead 572 is at "zero", fm occurs on output lead 576, and when lead 572 is at "one" fm occurs on lead 576 as shown by the wave forms fv and fA in Figure 22. The output on lead 576 is sampled by an integrated circuit delay flipflop 578 at the positive transitions of the four mhz clock frequency f. The output on lead 580 is shown by wave form fB in Figure 22. It can be seen that a transition of fv (positive or negative) inverts fA and the succeeding sample of fA by flip-flop 578 does not change fB. Therefore, two transitions or one cycle is deleted from fB for every cycle of fv. Thus, the frequency of fB is the nominal frequency fM minus the vibrato frequency fv.

Now assuming that the voltage on lead 382 equals the voltage on lead 380 and is at zero, and Vs is still logic "one", integrated circuit inverter 584 inverts Vs so that the output lead 585 is at logic "zero", and NAND gate 586 forces a "one" on output lead 587. Exclusive OR gates 588 and 589 force a "one" on output lead 587. Exclusive OR gates 588 and 589 produce a "one" on outputs 590 and 591. Delay flip-flops 592 and 593 sample outputs 590 and 591 respectively and yield a "one" on output leads 594 and 595 respectively. Therefore, exclusive or gates 596 and 598 invert fB on lead 580 and yield fB at the MFH and Mf2 outputs. Frequency 7B is the same frequency as fB but opposite or complement in phase. Wave form fA on lead 576 is also supplied to exclusive OR gates 600 and 602.Since it has been assumed that the voltages on leads 380 and 382 are zero, the frequency fA appears at the output leads 603 and 604 of exclusive OR gates 600 and 602 respectively. Flipflops 605 and 606 sample fA at the positive transitions of r and yield fC (see Figure 22) on leads 607 and 608 respectively.

The "one" on lead 587 is sampled by flipflop 610 at the positive transitions of which yields a "one" on lead 611. As a result, exclusive OR gates 612 and 614 invert the output on leads 608 and 607 respectively yielding frequency fC at the MF3 and MF1 outputs. It can be seen from Figure 22 that fC is also the nominal frequency fM minus the vibrato frequency fV.

Now assuming that the voltage on leads 380 and 382 is still zero, but that the voltage Vs is now also "zero", NAND gate 570 forces the output on lead 572 to "one" and exclusive OR gate 574 yields IM on lead 576. Since the voltage on leads 380 and 382 equals zero, exclusive OR gates 600 and 602 yield fM on output leads 603 and 604. Fijp- flop 578 synchronizes the transitions of with the positive transitions of f yielding fD (see Figure 22) on lead 580. Flip-flops 605 and 606 synchronize the transitions of fM with the positive transitions of f yielding fD (see Figure 22) on leads 607 and 608.

Since Vs on lead 370 is at "zero", inverter 584 forces a "one" output on lead 585 and NA-ND gate 586 yields tv on lead 587. Since the voltage on leads 380 and 382 equals zero exclusive OR gates 588 and 589 yield fv on leads 590 and 591. Flip-flops 592 and 593 synchronize the transitions of fv with the positive transitions of f yielding fE on leads 594 and 595. Flip-flop 610 synchronizes the transitions of f with the positive transitions of f yielding fF on lead 611 The combination of frequencies of fF and fM into exclusive OR gates 612 and 614 yields frequency fG (see Figure 22) at outputs MF3 and MFI. The combination of frequency fD and fE into exclusive OR gates 596 and 598 yields frequency fH at the MFH and MF2 outputs.It can be seen in Figure 22 that fG and fH have two extra transitions and one extra cycle more than fM for each cycle of fv. Therefore, the output frequency is the nominal frequency fM plus the vibrato frequency fv. Thus, it can be seen that when Vs is at "one" fv is added to tM at each of the MFH, MF1, MF2 and MF3 outputs. In a similar manner the transitions of one-half F delta on lead 382 will be combined by exclusive OR gates 600 with transitions of fv and fM and sampled by flip-flop 605 to add output pulses at the MF3 output. Transitions on lead 382 are combined with the transitions on lead 587 by exclusive OR gate 589, synchronized by flip-flop 593 and subtracted from the frequency on lead 580 by exclusive OR gate 598 to produce an output on MF2.

Similarly transitions of f delta on lead 380 are subtracted by exclusive OR gate 602, flip-flop 606, exclusive OR gate 614, to produce the MF1 output. Transitions of f delta on lead 380 are added by exclusive OR gate 588, flip-flop 592 exclusive OR gate 596 to produce the MFH output.

It can be seen that if a transition occurs on leads 380 or 382 during the same cycle of f (from one positive transition to the next) as a transition of fv occurs, both transitions are missed. Since the probability of this occurring is so slight, it cannot be audibly detected.

Thus, it can be seen that the Master frequencies MF1, MF2, MF3 and MFH applied to the programmable counters 270, 274, 276 and 278 in Figures 7A-C are dynamically controlled and shifted very slightly with respect to one another depending on when the first key is played, the number of keys played, the vibrato voltage controlled oscillator 366, and the ensemble voltage controlled oscillator 378.

With reference to Figure 23, frequencies fl, f2, f3, and fH, are connected to the inputs of integrated circuit dividers 625, 626, 627, 628, 629, 630, 631, and 632.

Frequencies fl, f2, f3, and fH are at the 4 foot pitch, and the dividers 625-632 operate to divide those frequencies down to the 8 foot and 16 foot pitches. The respective Q outputs of dividers 625632 are connected to one of the inputs of NAND gates 633, 634, 635, 636, 637, 638, 639, and 640. The other input of NAND gates 633, 635, 637, and 639 is connected to the solo contact 641 of ensemble switch 172A. Switch 172A represents another set of contacts coupled with switch 172 in Figure 5. The other input of NAND gates 634, 636, 638 and 640 is connected to the accompaniment contact 642 of switch 172A.

As can be seen, when switch 172A is in the position illustrated in Figure 23, one input of NAND gates 634, 636, 638 and 640 is grounded through accompaniment contact 642. Accordingly, the output of NAND gates 634, 636, 638 and 640 remains high irrespective of the logic state of the other input. However, NAND gates 633, 635, 637 and 639 have one input above ground so that the other input connected to the dividers is inverted by those NAND gates.

Thus, as can be seen, switch 172A determines whether the 8 foot or 16 foot pitch is passed. The output of NAND gates 633 and 634 is designated as fDl which is a mnemonic for the divided frequency fl. The output of NAND gates 635 and 636 is designated fD2, the output of NAND gate 637 and 638 is designated fD3, and the output of NAND gates 639 and 640 is designated fDH.

Initially, operation of the quartet mode will be described to illustrate how respective notes of a chord are sounded in different voices. With reference to frequency fDI, that frequency is applied on lead 644 in Figure 23 through resistor 645 and capacitor 646 to the base of transistor 647 in Figure 24 which comprises trombone pulse gate 643 (trombone channel 1). As can be readily seen, the input fDI to the base of transistor 647 causes transistor 647 to produce pulses at its collector, with width of which pulse is determined by capacitor 646 and the current supplied by resistors 648 and 649. The larger the current supplied by resistors 648 and 649, the shorter the pulse and the brighter the output audible tone.

Resistors 649 and 650 are connected by lead 651 to the cathode of diode 652 in Figure 28.

The anode of diode 652 is connected to one side of capacitor 654, and the other side of capacitor 656 is grounded. Capacitor 654 is charged by transistor 656 if quartet switch 657A is closed and two or more keys are played as will be described below. Resistor 657 supplies the emitter current from the quartet switch, and resistors 658, 659 and diode 660 supply base bias current. Diode 660 is connected by lead 661 to lead 662 which is connected to the collector of transistor 664 in Figure 24. The base of transistor 664 is connected through resistor 665 to the GBE2 output in Figure 6. When two or more keys are played, GBE2 goes high or logic one, turning transistor 664 "on" and grounding leads 662 and 661 so that transistor 656 in Figure 28 will charge capacitor 654 if the quartet switch 657 is closed.

When GBE2 becomes logic one, capacitor 654 charges toward 27 volts, and the magnitude of the pulses produced by transistor 647 in Figure 24 becomes greater as controlled by resistor 650 and brighter as controlled by resistor 649. The output pulses of transistor 647 are gated by transistor 666 and fed to a low pass active filter 667 which comprises capacitors 668, 669, 670, 671, 672 and 673, resistors 674, 675, 676, 677, 678, 679 and 680, and transistor 687. The output of filter 667 is applied to lead 681. This filter is conventional and of the same type of active filter with an adjustable Q as disclosed in U.S. Patent No. 3,500,027-Uetrecht.

For quartet operation, i.e., different notes of a chord being sounded in different voices, frequency fD2 at the output of NAND gate 635 and 636 in Figure 23 is applied on lead 682, 683 through resistor 684 and capacitor 685 to the base of transistor 686 in Figure 25. Transistor 686 comprises a saxophone pulse gate 689 (saxophone channel 2) which is very similar to the trombone pulse gate 643 in Figure 24 except that resistor 687 is the only current source available to control the pulse width produced by transistor 686. Accordingly, the pulse width for saxophone gate 689 is substantially wider than the width of pulses produced by transistor 647 in the Trombone pulse gate 643 in Figure 24.Thus, saxophone pulse gate 689 produces a pulse that is substantially wider than the pulse of the trombone pulse gate 643, and the pulse width becomes 50% duty cycle in the high frequency range. Capacitor 688 across the collector -- emitter of transister 686 distorts the pulse output of transistor 686 to a sawtooth wave form in the high frequency range. In the low frequency range, the pulse width is substantially less than 50% and the capacitor 688 has a minor effect upon the wave shape. This capacitor distortion eliminates the need to control the pulse width by a tracking voltage as has been accomplished in prior art electronic musical instruments.

The output of transistor 686 is connected through diode 690 to load resistor 691. The voltage developed across resistor 691 is applied on lead 692 to active filter 694 in Figure 26 which is substantially the same as active filter 667 in Figure 24 except for one difference. Specifically, the output of transistor 695 is channeled via resistor 696, capacitor 697 and resistor 698 to output lead 699. In addition, the output of transistor 695 is also channeled via capacitor 700 and 701 to capacitor 697 and resistor 698 to the output 699. Capacitor 700 and 701 are selected to pass only the higher frequency components. Diode 702 distorts the higher frequency components depending upon the signal level and the bias current supplied by resistor 703. Thus, diode 702 changes the harmonic content of the higher frequency components giving the filter a variable filter characteristic. Attention is directed to U.S.

Patent No. 3,801,721-Bunger for a more thorough description of such variable filters.

Similarly, during quartet operation, frequency fD3 is applied via lead 705 and 706 (Figure 23) to the base input of another saxophone pulse gate 708 (saxophone channel 3) (Figure 25) which is substantially the same as pulse gate 689 previously described. The output of saxophone pulse gate 708 is applied to an active filter 710 in Figure 27. Active filter 710 operates in the same manner as active filter 694 in Figure 26 and produces an output on lead 712.

As in the operation of trombone pulse gate 643 (Figure 24), the operating voltage for transistor 686 in saxophone pulse gate 689 (Figure 25) is supplied on lead 714 which is connected through diode 715 to capacitor 716 in the quartet switch gate arrangement illustrated in Figure 28. As previously described, with respect to transistor 656, when the GBE2 input to transistor 664 in Figure 24 goes high (when two or more notes are played) transistor 664 is biased "on" and leads 662 and 661 are essentially grounded. This causes transistor 718 to turn "on" (if switch 657A is closed) causing capacitor 716 to start charging so that voltage is applied on lead 714 to transistor 686 as capacitor 716 charges giving the desired attack characteristics for the saxophone tone signal.In a similar manner, the operating voltage for saxophone pulse gate 708 is supplied through resistor 720, lead 722 which is connected through diode 723 to capacitor 724 in Figure 28. Transistor 725 is biased "on" when one or more notes are played (as will be described below) charging capacitor 724 and gradually applying voltage on lead 722 to pulse gate 708 to give the desired attack characteristic to the saxophone tone signal produced by gate 708.

With reference to Figure 24, transistor 727 is biased "on" when GBE1 goes high as a result of one or more notes being played. Lead 728 is connected to the correspondingly-numbered lead in Figure 28 so that it can be seen that both transistor 725 in the saxophone 3 switch gate and transistor 730 in the trumpet H switch gate are biased "on" whenever one or more notes are played.

In the quartet operation, the frequency fDH is applied to the base of transistor 732 in Figure 23. Transistors 732 and 734 form a trumpet pulse gate 736 (trumpet channel H) which operates substantially in the same manner as the trombone pulse gate 643 (Figure 24) previously described. The principal difference is that the component values of the capacitor and resistors are chosen to obtain a narrower pulse which is more consistent with the trumpet voice. Voltage is applied to the collectors of transistors 732 and 734 on lead 738 which is connected through diode 739 to capacitor 740 in Figure 28. As previously described, when one or more notes are played, transistor 730 is biased "on" and capacitor 740 commences charging applying the operating voltage to the collectors of transistors 732 and 734 in a gradual attack mode.The value of capacitor 740 is selected to provide the requisite trumpet attack characteristic. The output of transistor 734 is applied on leads 742 and 743 to the input of an active filter 744 in Figure 25. Active filter 744 is substantially similar to filters 667,694 and 710 except that the component values are selected to provide a larger Q at a higher frequency resulting in a brighter trumpet voice. The output of active filter 744 is applied on lead 745, combined with the output of trombone filter 667 on lead 681 and applied to the input of volume control circuit 746 (in Figure 29) via lead 747. Similarly (in Figure 26), the output of saxophone active filter 694 on lead 699 is combined on lead 681 and fed to volume control 746 on lead 747.

Similarly, the output of saxophone active filter 710 on lead 712 is applied to another channel of volume control 746 in Figure 29.

Volume control circuit 746 comprises two conventional current fork arrangements which control the output volume of the tone signals on multiple channels while avoiding the noise problems often incident to the utilization of multiple or ganged potentiometers. Since both channels of volume control circuit 746 operate in exactly the same manner, only one channel will be described. Transistors 750 and 752 comprise a current fork arrangement for the direct current supplied to the collector of transistors 750 and 752 by a 22 volt source connected at point 751 and for the Ac current signal supplied on lead 747. The base of transistor 752 is connected to a 22 volt source through resistor 753 and the base of transistor 750 is connected to a 27 volt source through a voltage divider arrangement comprising resistors 754, 755 and volume potentiometer 756.If volume potentiometer 756 is adjusted so that a full 27 volts is applied through resistor 755 to the base of transistor 750, transistor 750 conducts virtually all of the current and the AC component is essentially shorted to ground by capacitor 758. Thus, there is no output signal. However, as the volume pot 756 is adjusted downwardly, transistor 752 starts conducting more and more current. If volume pot 756 is adjusted until no voltage is applied to resistor 755, transistor 752 is conducting virtually all of the current and virtually the entire output signal is applied through capacitor 760 to an audio amplifier circuit 762 having RF suppression.

Transistor 764 operates as an amplifier, the DC operating point of which is determined by resistors 765 and 766. Capacitors 767, 768 and 769 and resistors 780 and 781 act to suppress radio frequencies. The output is applied on lead 784 to one audio channel comprising a conventional amplifier and speaker. The other channel of volume control circuit 746 produces an output on lead 786 to another channel of the audio system.

As can be seen when the quartet switch 657a is closed and only one note is played, that one note is sounded in both the trumpet (channel H) and saxophone (channel 3) voices. If two notes are played, the highest note is sounded in the trumpet (channel H) and saxophone (channel 3) voice and the lowest note is sounded in the trombone (channel 1) and saxophone (channel 2) voices. If three notes are played, the lowest note is sounded in the trombone (channel 1) voice, the second note is sounded in the saxophone (channel 2) voice, and the third note is sounded in the trumpet (channel H) and saxophone (channel 3) voices. If four notes are played, each note is sounded in a separate voice.If quartet operation is not desired but it is desired for all notes of a chord to be sounded in the same voice, respective switches are supplied for each of the trumpet, trombone, and saxophone voices which will permit all notes to be sounded in those voices as selected. For example, with reference to Figure 24, if trombone switch 790 is closed, 27 volts is applied to the emitters of transistors 791 and 792. However, transistor 792, will not turn "on" until GBEI biases transistor 727 "on" so that current will flow through resistors 793 and 794 and diode 795 to bias transistor 792 "on": Transistor 792 and capacitor 797 produce an increasing voltage on lead 798 which is applied to trombone pulse gates 800 and 802. Trombone pulse gates 800 and 802 operates in the same manner as previously described with respect to trombone pulse gate 643.In a similar manner, when GBE2 goes high when two or more notes are played, transistor 791 is biased "on" so that voltage is applied on lead 803 to trombone pulse gates 804 and through diode 814 and lead 651 to trombone pulse gate 643. Similarly, it should be apparent how the trumpet switch 810 in Figure 25 and the saxophone switch 812 operate in conjunction with transistors 664 in Figure 26 and Figure 27 to turn on the respective trumpet and saxophone pulse gates as varying numbers of keys are played.

It should be noted, that isolation diodes 814 (in Figure 24) 816 (in Figure 23) 818 and 820 (both in Figure 25) are provided for isolation purposes so that the operating voltage developed by the quartet switch arrangement in Figure 28 only turns on the pulse gate utilized by the quartet arrangement and not the other pulse gates in the respective voicing circuits.

With reference to Figure 31, an alternative embodiment of the present invention is illustrated. This embodiment utilizes analog voltage controlled oscillators rather than digital programmable counter circuits to produce the desired tone signal frequencies as will be more fully described below. The Figure 31 alternative embodiment comprises an exponential reference voltage generator 800, four sample and hold circuits 802, four voltage controlled oscillators 804, and four octave dividers 806.

The exponential reference voltage generator 800 is a conventional circuit which comprises an electronic switch which can be turned on by input T-l to charge a capacitor to a fixed reference voltage very rapidly at the beginning of the scan period.

A resistance load then discharges the capacitor in a calibrated fashion during the scan period so that one half of the reference voltage remains on the capacitor at the end of one octave scan period. The output reference voltage is applied on lead 808 to the four sample and hold circuits 802. Thus, at the beginning of each scan cycle (i.e. at Tl) the exponential voltage is brought to its highest value and then allowed to decay exponentially to one half that value during the scan period.

In the Figure 31 embodiment, four sample and hold circuits 802 and four voltage control oscillators 804 are shown so that the system is in conformity with the Figure 1 embodiment. However, any number of sample and hold circuits and voltage control oscillators could be utilized depending upon the ultimate number of output frequencies desired. The sample and hold circuits 802 are conventional sample and hold circuits which sample the reference voltage on line 808 at the instant that the respective note played information, CLEI, CLE2, CLE3, CLEH is respectively applied to the four sample and hold circuits and then hold and transmit that sampled reference voltage to the voltage controlled oscillators.Briefly, the conventional sample and hold circuits comprise an electronic switch controlled by the note played signals and a capacitor having a short charge time and a long decay time that will charge to the sampled reference voltage at the time the note played information is received and hold the sampled reference voltage between samples. In the Figure 31 embodiment, the note scan is reversed so that the highest note played is scanned first and each succeeding lower note is scanned in reverse order. In this manner, the exponential reference voltage which decays from a high value to a low value can be utilized to control the four voltage controlled oscillators. The oscillator frequency is directly proportional to voltage.

Accordingly, at the time slot for the highest note played, CLEH goes to logic one and the first sample and hold circuit samples the exponential reference voltage at that time and transmits that reference voltage as vfH to the fourth of the four voltage controlled oscillators. At that point in time, vfH will have decayed to a value which will cause the fourth voltage controlled oscillator to produce a tone signal at a frequency corresponding to the semitone of the highest note played but at a frequency corresponding to the highest octave. Similarly, at the time slot for the third lowest note played, CLE3, the decaying reference voltage is again sampled and transmitted as vf3 to the third of the voltage controlled oscillators 804.This reference voltage vf3 causes the second of the voltage controlled oscillators to produce a tone signal at the frequency of the semitone of the third lowest note played but at the highest octave. Similarly, at the time slot for the second and first lowest notes played, CLE2 and CLEI, the sample and hold circuits transmit corresponding reference voltage vf2 and vfl to the second and first voltage controlled oscillators causing those voltage controlled oscillators to produce tone signals at a frequency corresponding to the semitones of the second and first lowest notes but at the highest octave.

The four voltage controlled oscillators 804 are conventional voltage controlled oscillators that are well known in the art, and as will be readily apparent, the frequency of the output of each of the voltage controlled oscillators is dependent upon the input voltage from the respective sample and hold circuits. It should also be apparent that while the Figure 1 embodiment scans upwardly from the lowest note to the highest note, by a very simple rewiring of the multiplex circuit, the scan can be reversed so that the notes are scanned from the highest to the lowest notes played.

The octave time slot information, Q7, Q8 and Q9, is applied to the four octave divider circuits 806 which may be identical to the octave divider circuits illustrated in Figures 7-B and 7-C. Specifically, the four octave dividers 806 may correspond to the dividers 292, 294, 296, 298 and 300, the Nand gates 304 and the latch circuit 284 illustrated in Figures 7B and 7C. The respective octave information, Q7, Q8 and Q9, operates to cause the output tone signals from the four voltage controlled oscillators to be divided down to the appropriate octave of the played notes. Thus, outputs fl, 12, f3 and f4 are tone signals at the desired semitone and octave of the played keys. These tone signals can be applied to the voltage controlled gate and filter circuits 21 in the same manner as previously described.

Accordingly, it should be apparent that the Figure 31 embodiment is an analog system which may replace the programmable counter circuits illustrated in Figure 7B. Otherwise, except for the reverse scan of the notes, the two embodiments are virtually analogous.

WHAT WE CLAIM IS: 1. A polyphonic electronic music system for an electronic musical instrument having at least one manual of keys corresponding to the notes of the musical scale, comprising: means for producing tone signals of frequencies corresponding to the notes of keys contemporaneously played on the manual of keys; and means for gating and filtering the tone signals to produce different voices for different frequencies, the manner of assignment of voices to the individual frequencies being variable according to the number of keys played at any given time.

2. A polyphonic electronic music system as claimed in claim 1, wherein means are provided to determine the number of keys contemporaneously played and to select the voice for each individual note depending upon the number of keys played.

3. A polyphonic electronic music system, as claimed in claim 2, wherein at least first, second, third and fourth voices are provided and so arranged that if one note is played, that note is sounded in the third and fourth voices; if two notes are played in a chord, the first note is sounded in the first and second voices and the second note is sounded in the third and fourth voices; if three notes are played in a chord, the first note is sounded in the first voice, the second note is sounded in the second voice, and the third note is sounded in the third and fourth voices; and if four notes are played, the first note is sounded in the first voice, the second note is sounded in the second voice, the third note is sounded in the third voice, and the fourth note is sounded in the fourth voice.

4. A polyphonic electronic music system as claimed in claim 1 or claim 2 or claim 3, wherein there are provided plural gating and filtering means for the tone signals arranged to produce the attack and voice characteristics of a plurality of predetermined musical instruments; said instrument further comprising routing means for causing individual ones of said tone signals to be passed through respective predetermined individual ones of said plural means for gating and filtering depending upon the number of keys played at any given time; and audio output means for audibly sounding the notes passed by the gating and filtering means; whereby individual ones of said tone signals corresponding to the notes of the keys simultaneously played are sounded in different voices to produce an orchestral effect.

5. A polyphonic electronic music system as claimed in claim 4, wherein said plural gating and filtering means comprises at least

**WARNING** end of DESC field may overlap start of CLMS **.

Claims (15)

**WARNING** start of CLMS field may overlap end of DESC **. controlled oscillator to produce a tone signal at a frequency corresponding to the semitone of the highest note played but at a frequency corresponding to the highest octave. Similarly, at the time slot for the third lowest note played, CLE3, the decaying reference voltage is again sampled and transmitted as vf3 to the third of the voltage controlled oscillators 804. This reference voltage vf3 causes the second of the voltage controlled oscillators to produce a tone signal at the frequency of the semitone of the third lowest note played but at the highest octave.Similarly, at the time slot for the second and first lowest notes played, CLE2 and CLEI, the sample and hold circuits transmit corresponding reference voltage vf2 and vfl to the second and first voltage controlled oscillators causing those voltage controlled oscillators to produce tone signals at a frequency corresponding to the semitones of the second and first lowest notes but at the highest octave. The four voltage controlled oscillators 804 are conventional voltage controlled oscillators that are well known in the art, and as will be readily apparent, the frequency of the output of each of the voltage controlled oscillators is dependent upon the input voltage from the respective sample and hold circuits. It should also be apparent that while the Figure 1 embodiment scans upwardly from the lowest note to the highest note, by a very simple rewiring of the multiplex circuit, the scan can be reversed so that the notes are scanned from the highest to the lowest notes played. The octave time slot information, Q7, Q8 and Q9, is applied to the four octave divider circuits 806 which may be identical to the octave divider circuits illustrated in Figures 7-B and 7-C. Specifically, the four octave dividers 806 may correspond to the dividers 292, 294, 296, 298 and 300, the Nand gates 304 and the latch circuit 284 illustrated in Figures 7B and 7C. The respective octave information, Q7, Q8 and Q9, operates to cause the output tone signals from the four voltage controlled oscillators to be divided down to the appropriate octave of the played notes. Thus, outputs fl, 12, f3 and f4 are tone signals at the desired semitone and octave of the played keys. These tone signals can be applied to the voltage controlled gate and filter circuits 21 in the same manner as previously described. Accordingly, it should be apparent that the Figure 31 embodiment is an analog system which may replace the programmable counter circuits illustrated in Figure 7B. Otherwise, except for the reverse scan of the notes, the two embodiments are virtually analogous. WHAT WE CLAIM IS:

1. A polyphonic electronic music system for an electronic musical instrument having at least one manual of keys corresponding to the notes of the musical scale, comprising: means for producing tone signals of frequencies corresponding to the notes of keys contemporaneously played on the manual of keys; and means for gating and filtering the tone signals to produce different voices for different frequencies, the manner of assignment of voices to the individual frequencies being variable according to the number of keys played at any given time.

2. A polyphonic electronic music system as claimed in claim 1, wherein means are provided to determine the number of keys contemporaneously played and to select the voice for each individual note depending upon the number of keys played.

3. A polyphonic electronic music system, as claimed in claim 2, wherein at least first, second, third and fourth voices are provided and so arranged that if one note is played, that note is sounded in the third and fourth voices; if two notes are played in a chord, the first note is sounded in the first and second voices and the second note is sounded in the third and fourth voices; if three notes are played in a chord, the first note is sounded in the first voice, the second note is sounded in the second voice, and the third note is sounded in the third and fourth voices; and if four notes are played, the first note is sounded in the first voice, the second note is sounded in the second voice, the third note is sounded in the third voice, and the fourth note is sounded in the fourth voice.

4. A polyphonic electronic music system as claimed in claim 1 or claim 2 or claim 3, wherein there are provided plural gating and filtering means for the tone signals arranged to produce the attack and voice characteristics of a plurality of predetermined musical instruments; said instrument further comprising routing means for causing individual ones of said tone signals to be passed through respective predetermined individual ones of said plural means for gating and filtering depending upon the number of keys played at any given time; and audio output means for audibly sounding the notes passed by the gating and filtering means; whereby individual ones of said tone signals corresponding to the notes of the keys simultaneously played are sounded in different voices to produce an orchestral effect.

5. A polyphonic electronic music system as claimed in claim 4, wherein said plural gating and filtering means comprises at least

a first, second, third, and fourth means for wave shaping said tone signals into first, second, third and fourth voices, respectively.

6. A polyphonic electronic music system as claimed in claim 4 or claim 5, wherein means are provided for selectively disabling said routing means and causing all of said notes to sound in a single predetermined voice.

7. A polyphonic electronic music system as claimed in any one of the preceding claims, and comprising multiplexer means for producing time division logic data signals representative of the octave and semitone of the notes of the keys played on the manual; logic means for receiving said time division logic data signals and producing first logic signals corresponding to the number of keys played and second logic signals corresponding to the notes of the keys played on the manual; and programmable counter means for producing in response to said second logic signals a plurality of tone signals on separate outputs corresponding to the notes of the keys played.

8. A polyphonic electronic music system as claimed in claim 7, wherein said gating and filter means are controlled by said first logic signals to cause individual tone signals corresponding to the notes of a simultaneously played chord to be sounded in separate predetermined voices.

9. A polyphonic electronic music system as claimed in claim 7 or claim 8, wherein said programmable counter means comprises first, second, third, and fourth programmable counters controlled by said second logic signals and divider means controlled by said time division logic signals representative of the octave of notes played to produce first, second, third and fourth tone signals.

10. A polyphonic electronic music system as claimed in any one of claims 7 to 9, comprising clock means for providing a plurality of clock outputs; counter and decoder means for generating from the clock outputs a first set of time division logic signals representative of twelve notes of an octave, a second set of time division logic signals representative of two or more octaves, and a third set of time division logic signals representative of at least two manuals of keys of the instrument; means for transmitting representative ones of the first set of time division logic signals to corresponding ones of the key switches of the manuals; multiplexer means for receiving logic signals corresponding to actuated key switches, the second set of logic signals, and the third set of logic signals and providing a serial train of time division multiplex signals identifying the actuated key switches; memory means for storing the serial train of signals representative of the actuated key switches during the next cycle of the counter and decoder means and comparator means providing a hold signal when the stored serial train does not correspond to the next serial train; priority selector means for providing time division logic signals representative of the three lowest notes and the highest note of the actuated key switches; and monostable and enable logic means for receiving the hold signal from the comparator means, and the logic signals from the priority selector means and providing in response thereto output logic signals representative of the number of actuated keys and logic signals representative of the lowest three notes and the highest note of the actuated keys; and wherein said programmable counter means receives the logic signals from the monostable and enable logic means representative of the actuated keys, the first set of logic signals representative of the twelve notes of an octave, and the logic signals representative of the two or more octaves, and in response thereto produces the output tone signals corresponding to the notes of the actuated key switches and voltages representative of the notes of the actuated key switches, said gating and filtering means being voltage-controlled.

11. A polyphonic electronic music system as claimed in claim 10, wherein said monostable and enable logic means are arranged not to provide output logic signals for a first predetermined time period after key switches are first actuated, and not to provide output logic signals for a second predetermined period of time if one or more actuated keys are released.

12. An electronic organ having a primary tone generating and audio output system, and an accompaniment system according to any one of the preceding claims producing and wave-shaping secondary tone signals corresponding to certain preselected simultaneously actuated ones of said key switches to provide an orchestral accompaniment for tone signals sounded by the primary audio output system.

13. A polyphonic electronic music system according to any one of claims 1 to 11, wherein said gating and filtering means are capable of sounding m orchestral voices of different timbre, where m > 2; and said toneproducing means assign to each of said m orchestral voices a frequency in the musical scale determined by both the number n of keys contemporaneously played, where l < n < m, and their relative position on the manual of keys.

14. A polyphonic electronic music system according to any one of claims 1 to 11, wherein said gating and filtering means are capable of producing a plurality of orchestral voices of different timbre; and said tone-producing means sound each one of said plurality of orchestral voices in a pitch based on the number of keys played contemporaneously and the relative position of the played keys on said manual of keys.

15. A polyphonic electronic music system for an electronic musical instrument, substantially as described with reference to Figures 1 to 30, or Figure 31, of the accompanying drawings.