GB1603616A - Electric oscillator circuit arrangements - Google Patents

Description

(54) IMPROVEMENTS IN OR RELATING TO ELECTRIC OSCILLATOR CIRCUIT ARRANGEMENTS (71) We, THE GENERAL ELEC TRIC COMPANY LIMITED, of 1 Stanhope Gate, London W1A 1EH, A British company, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed to be particularly described in and by the following statement: The present invention relates to electric oscillator circuit arrangements.

In particular although not exclusively the invention relates to oscillators for use in timing pulse generators for digital data transmission systems.

According to the present invention in a digital data transmission system including one or more stations at which digit value signals being transmitted over the system are regenerated and a digit signal retiming arrangement at one of said stations comprising digit value storage means into which received digit values are entered in turn and from which said digit values are arranged to be read out in turn at a rate substantially equal to the mean rate at which said digit values are entered in said storage means, a timing pulse generator for controlling the rate of read-out of said digit values comprises a voltage controlled oscillator, phase comparator means to compare an output of the oscillator with input timing signal to derive a control signal for said oscillator, and filter means between the phase comparator and the oscillator the bandwidth of which is arranged to be dependent upon the magnitude of said control signal.

A digital data transmission system embodying the present invention will now be described by way of example with reference to the accompanying drawings, of which: Figure 1 shows schematically a part of the transmission system Figure 2 shows in greater detail a part of the system shown in Figure 1, and Figure 3 shows in greater detail a part of the system shown in Figure 2.

The data transmission system may be arranged to accept data in binary-coded form at a maximum bit rate of, say, 120 Mega bits/second and to translate this into ternary coded form, at a corresponding maximum symbol rate of 90 Megabauds, for transmission over a coaxial cable. The ternary coded symbols are reshaped at intervals along the cable by means of regenerative repeaters, at which the timing of the regenerated symbol is effected by clock extraction means responsive to timing or clock information in the received symbols.

One form of clock extraction means comprises a tuned circuit which is arranged to support forced oscillations at the clock frequency, induced by transients derived from the incoming symbols, and from which a continuous train of clock pulses can be derived for timing the regeneration of the symbols. The tuned circuit is of sufficiently high Q to provide clock pulses in the intervals between input pulses.

Such clock extraction means are "broad band" devices, in that they are able to track the timing information in the incoming symbols fairly closely, but because this timing information is affected by noise and distortion in these incoming symbols the extracted clock signals are subject to jitter about the true clock timing instants.

It has been shown that in transmission systems incorporating a chain of regenerative repeaters the jitter phase excursion builds up as the square root of the number of regenerators in the chain once that number exceeds, say, twenty. However, because of the frequency spectrum shaping effect of the succession of tuned circuits, the energy becomes more and more concentrated about the clock frequency, and the magnitude of jitter phase excursion which can occur is proportional to the number of repeaters. Long chains of repeaters can therefore produce jitter with a large peak to r.m.s. ratio, though in practice the peaks only occur rarely if the data stream is effectively random.

The jitter may be reduced by using a single jitter reducer at the end of the chain of repeaters, with a data store large enough to accommodate the extremes of phase excursion encountered, say up to four ternary symbol periods in either sense.

Referring now to Figure 1 apparatus at one station of a digital data transmission system, for example at a receiving terminal of that system, comprises a symbol regenerator arrangement 1 which, in dependence upon timing information extracted by means of clock extraction circuit 2 from ternary coded data symbols received over a transmission path 3, regenerates those symboles and passes them to a data storage arrangement 4 by way of a ternary to binary decoder (not shown). The timing of the decoded binary signals will in general retain any jitter which has been introduced into the timing of the incoming ternary data symbols, and a phase-locked oscillator arrangement 5 is provided to generate regular clock pulses at the mean clock rate of the binary signals.The decoded data is entered in the storage arrangement 4 in dependence upon the incoming timing signals and is read out under control of the regular clock pulses from the oscillator arrangement 5.

Referring now to Figure 2, the storage arrangement 4 comprises a sixteen-bit binary shift register 6 which is arranged to accept in serial mode sixteen bits of the incoming data stream and then transfer them in parallel to a sixteen bit binary store 7. At a time averaging some eight bit periods after the transfer them in parallel to a sixteen bit binary store 7. At a time averaging some eight bit periods after the transfer of the sixteen bits into the store 7 these sixteen bits are again transferred in parallel to a sixteen bit shift register 8, from which they are then read out serially. The transfer to the shift register 8 and the subsequent serial read- out are carried out under the control of regular clock pulses from the oscillator arrangement 5.

The input timing signals at a rate of some one hundred and twenty megahertz are applied directly to the shift register 6 and by way of a divide-by-sixteen circuit 9 to time the transfer into the store 7. Similarly clock pulses from the oscillator arrangement 5 at a rate of one hundred and twenty megahertz are applied directly to time the read-out from the shift register 8 and by way of a divide-by-sixteen circuit 10 to time the transfer from the store 7 to the shift register 8.

Referring now to Figure 3 the arrangement 5 comprises an oscillator 11, operating at a frequency of one hundred and twenty megahertz, which is effectively phaselocked to the sixteenth harmonic of a seven and a half megahertz crystal-controlled oscillator 12 which in turn is controlled to operate substantially at the mean frequency of an input signal on a path 13, as follows.

An output from the oscillator 11 is frequency divided by sixteen in a circuit 14 and the resultant seven and a half megahertz signal is applied to a phase comparator 15 together with an output from the oscillator 12, the output of the comparator 15 being used to control the frequency of the oscillator 11. At the same time another output from the divider circuit 14 is applied with the signal on the path 13 to another phase comparator 16, whose output is used to control the frequency of the crystal oscillator 12. A network 17 provides a resistor/capacitor shunt path between the output of the comparator 16 and earth, which acts effectively as a low-pass filter.

As described above the incoming timing signals at the end of a chain of repeaters, as represented by the frequency divided signals on the path 13, will in general vary in phase relatively slowly for much of the time, but infrequent phase excursions or peaks may be of appreciable amplitude. Between these peaks the phase of the oscillator 12 will tend to follow that of the signal on the path 13.

When a jitter peak occurs, however, the oscillator 12 will not be able to follow the rapid change of phase of the signal on the path 13 due to the slow response of the network 17, and the phase error, and hence the magnitude of the control signal developed at the output of the comparator 16, will tend to increase. If it exceeds positive or negative threshold values set by a resistive potential divider 18 one or other of two amplifiers 19 and 20 is arranged to apply a positive voltage proportional to the excess to a voltage compensator circuit 21. This circuit 21 comprises a unity-gain differential amplifier circuit (not shown) which is arranged to allow the gate electrode voltage of a field-effect transistor 22 to follow that of the source electrode, keeping the resistance of the transistor 22 substantially constant, except when a positive voltage is received from one of the amplifiers 19 and 20, when the effect to the change of resistance of the transistor 22 is to reduce the value of capacitance and increase the value of resistance presented by the network 17, and thereby increase the effective bandwidth of the filter. The rate of change of phase of the oscillator 12 can then be increased to follow that of the signal on the path 13 until the peak phase excursion is passed.

It will be appreciated that due to the operation of the phase-control loop for the oscillator 12 at one sixteenth of the data bit rate of one hundred and twenty megabits per second, jitter phase errors equivalent to several bit periods will be represented by proportionally lower phase errors in the phase control loop. The values for the threshold voltages provided by the divider network 18 for the amplifiers 19 and 20 may be set to correspond to phase excursions in either sense equivalent to, say, six or seven bits, the margin of two or one bits respectivelv ensuring that the maximum phase excursion that occurs in practice does not exceed the capacity of the store 7 to contain that excursion.

The network 17 comprises a capacitor 23, an amplifier 24, and resistors 25, 26 and 27, and is arranged such that it presents to the control signal path 28 a series combination of the resistor 27 and the transistor 22, and a capacitance value effectively equal to that of the capacitor 23 multiplied by the ratio of the value of the resistor 25 over the resistance value of the resistor 27 and the transistor 22 taken together.

WHAT WE CLAIM IS: 1. A digital data transmission system including one or more stations at which digit value signals being transmitted over the system are regenerated and a digit signal retiming arrangement at one of said stations comprising digit value storage means into which received digit values are entered in turn and from which said digit values are arranged to be read out in turn at a rate substantially equal to the mean rate at which said digit values are entered in said storage means, wherein a timing pulse generator for controlling the rate of read-out of said digit values comprises a voltage controlled oscillator, phase comparator means to compare an output of the oscillator with an input timing signal to derive a control signal for said oscillator. and filter means between the phase comparator and the oscillator the bandwidth of which is arranged to be dependent upon the magnitude of said control signal.

2. A digital data transmission system in accordance with Claim 1 wherein said filter means comprises a capacitor, a capacitance multiplier, and variable resistance transistor means to control the multiplication ratio of said multiplier. and thereby the time constant of said filter means, in dependence upon a signal applied to said transistor means.

3. A digital data transmission system in accordance with Claim 2 wherein the signal applied to said transistor means is dependent upon the value of the control signal for said oscillator.

4. A digital data transmission system substantially as hereinbefore described with reference to the accompanying drawings.

**WARNING** end of DESC field may overlap start of CLMS **.

Claims (4)

**WARNING** start of CLMS field may overlap end of DESC **. It will be appreciated that due to the operation of the phase-control loop for the oscillator 12 at one sixteenth of the data bit rate of one hundred and twenty megabits per second, jitter phase errors equivalent to several bit periods will be represented by proportionally lower phase errors in the phase control loop. The values for the threshold voltages provided by the divider network 18 for the amplifiers 19 and 20 may be set to correspond to phase excursions in either sense equivalent to, say, six or seven bits, the margin of two or one bits respectivelv ensuring that the maximum phase excursion that occurs in practice does not exceed the capacity of the store 7 to contain that excursion. The network 17 comprises a capacitor 23, an amplifier 24, and resistors 25, 26 and 27, and is arranged such that it presents to the control signal path 28 a series combination of the resistor 27 and the transistor 22, and a capacitance value effectively equal to that of the capacitor 23 multiplied by the ratio of the value of the resistor 25 over the resistance value of the resistor 27 and the transistor 22 taken together. WHAT WE CLAIM IS:

1. A digital data transmission system including one or more stations at which digit value signals being transmitted over the system are regenerated and a digit signal retiming arrangement at one of said stations comprising digit value storage means into which received digit values are entered in turn and from which said digit values are arranged to be read out in turn at a rate substantially equal to the mean rate at which said digit values are entered in said storage means, wherein a timing pulse generator for controlling the rate of read-out of said digit values comprises a voltage controlled oscillator, phase comparator means to compare an output of the oscillator with an input timing signal to derive a control signal for said oscillator. and filter means between the phase comparator and the oscillator the bandwidth of which is arranged to be dependent upon the magnitude of said control signal.

2. A digital data transmission system in accordance with Claim 1 wherein said filter means comprises a capacitor, a capacitance multiplier, and variable resistance transistor means to control the multiplication ratio of said multiplier. and thereby the time constant of said filter means, in dependence upon a signal applied to said transistor means.

3. A digital data transmission system in accordance with Claim 2 wherein the signal applied to said transistor means is dependent upon the value of the control signal for said oscillator.

4. A digital data transmission system substantially as hereinbefore described with reference to the accompanying drawings.