GB1603554A - Digital data processing - Google Patents

Description

(54) DIGITAL DATA PROCESSING (71) We, GENERAL INSTRUMENT MICRO ELECrRONICS LIMITED, a British Company, of Neward Road North, Glenrothes, Fife, Scoland KY7 4NL, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: This invention relates to digital data processing and particularly concerns a circuit for shaping a received digital waveform representing a sequence of digital bfts The invention is applicable, for example, to the processing of data to be displayed by a television receiver, such as Teletext information.In a Teletext system, a television/logic interface circuit, commonly called a data grabber, is provided and the circuit of the present invention can be designed for such a data grabber to recover the incoming digital data for use in the subsequent logic circuitry According to the present invention, there is provided a circuit for shaping a received digital waveform representing a sequence of digital bits, the circuitcomprismg means for producing an output voltage and for switching that voltage between two levels in dependence upon the first differential with respect to time of said received waveform, the producing means comprising differentiating means for producing a first signal corresponding to said first differential and a second signal corresponding to the inverse of said first differential, and comparator means for receiving said first and second signals and for comparing those signals with a single threshold level to determine the switching instants of the output voltage from one to the other and the other to the one of said two levels in dependence upon said first differential and its inverse respectively passing through said single threshold level in a given direction. In one example, the differentiating means may comprise an inductive circuit having a tapped inductance providing said first and second signals at respective sides. of the tap of the inductance.

In a preferred embodiment, the comparison means comprises means operable to produce a third signal corresponding to excursions of the first signal with the same sign as, and of a magnitude above, said threshold level, and a fourth signal corresponding to excursions of the second signal with the same sign as, and of a magnitude above, said threshold level, and a bistable circuit having a set and a reset input connected to receive respective ones of the third and fourth signals.

For a better understanding of the invention and to show how the same may be carried into effect, reference will now be made by way of example to the accompanying drawings, in which: Figure 1 is a circuit diagram of a Teletext and Viewdata and clock regenerator; and Figure 2 is a diagram showing waveforms of signals occurring in the regenerator of Figure 1.

The function of the circuit of Figure 1 is to receive data from a television receiver and regenerate that data in a form suitable for digital processing. It also generates a clock signal which provides timing information about the data.

Line A of Figure 2 shows the waveform of digital data as received by the regenerator, the binary bits '0' and '1' being indicated over the waveform. Such data can be severely corrupted by signal reflections, nonlinear phase response of the receiver IF amplifier, inter-channel interference and noise. The regerator is intended to overcome much of this corruption to increase the chances of obtaining clear and correct data for subsequent logic circuitry, together with the appropriate clock signal.

Line F of Figure 2 shows the form of output data required and below line F are evenly spaced vertical lines showing the position required for the clocking edge of each clock pulse in a Teletext system.

Line G of Figure 2 shows a second input signal R SYNC which defines when the clock signal should commence.

Returning to Figure 1, 1 denotes the input which in use is connected to a television re ceiver to receive the complex video signal which, when Teletext is being received, has the form shown in line A of Figure 2. The input 1 is coupled by capacitor Cl to an amplifier comprising transistor TR1 and resistors R1 to R4. A differentiator is formed by an inductance L1, being a centre-tapped four turn coil by an inductance LI, being a centre-tapped four turn coil on a ferrite bead.

The ends of inductance L1 are connected to the inverting inputs of respective com parators 2 and 3 which are provided by an integrated circuit IC1 (type 75 1t}7 B) ener gised from a +5 volts supply and from a 5 volts supply. The outputs of the com parators go to the set and reset inputs of a bistable circuit 4 formed by two NAND gates provided by an integrated circuit IC2 (type 74S00). One output of the bistable circuit is connected to an output DATA, the signal at which is shown in line F of Figure 2.

That output and the RSYNC input go re spectively to the clock and preset mputs of a D-type bistable circuit 5 (type 74 S74).

The clear input of circuit 5 is connected to a NAND gate also provided by circuit IC2) the inputs of which are connected to 5 volts via a resistor Rl 1 and to 0 volts via a switch 6.

The Q output (line H of Figure 2) of circuit 5 is connected to the preset input of a J-K bistable circuit 7 ( of type 74 S112) forming the first stage of a three stage di vide-by-eight counter 7, 8 and 9 the output of which is connected to output CLOCK and delivers the signal shown in line I of Figure 2. Stage 8 is also i of type 74 S112 and stage 9 is of type 74 S74. The preset inputs of stages 8 and 9 and the J,K and clear inputs of stage 7 are fed from the 5 volts supply via a resistor R10. The clear inputs of stages 8 and 9 are fed from the Q output of circuit 5.

The clock inputs of stages 7 and 8 are connected to a quartz oscillator of fre quency 55.5 MHZ. This oscillator comprises a crystal X1, resistor R9, NAND gate 10 OC2), capacitors C4 and C5 and a three turn air cored inductance L2.

In operation, the incoming data (line A of FIgure 2) is first amplified by transistor TR1 and then differentiated by causing a current proportional to the input voltage to flow through inductance L1. Since induc tance L1 is centre-tapped two output volt ages are produced, one being the inverse of the other (lines B and C of Figure 2). These voltages are compared in comparators 2 and 3 with a reference voltage of about 200 mV set up by divider R6, R7. The output voltages of the comparators are shown in lines D and E of Figure 2. It will be seen that a transition from '1' to '0' in the input voltage causes the output voltage from comparator 2 to go low and a transition from '0' to '1' causes the output voltage from comparator 3 to go low.The outputs from the comparators are converted by the bistable circuit 4 to a shaped form (line F of Figure 2) of the voltage suitable for subsequent processing by logic circuitry.

A 6.9375 MHz clock signal is also developed to enable subsequent logic circuitry to clock the regenerated data.

With switch 6 open, the counter 7, 8, 9 is free running, as is appropriate for Viewdata.

For Teletext, the switch is closed to apply a signal to circuit 5 in order to control the phase of the clock signal so that its clocking edges fall in the centre of the bit period (line F of Figure 2). In this mode, the R-SYNCH signal stops the counter and resets it to a predetermined state and the next leading edge of the DATA output signal removes the reset.

The counter is reset to a state such that the first clock edge out of the counter occurs in the middle of the data bit which removed the reset. By changing the state to which the counter is reset, allowance can be made for propagation delays of the control bistable circuit 5 and the counter stages and for the asynchronous nature of the oscillator.

Generally speaking, it will be seen that the invention provides means which produces an output digital waveform the high-low transitions of which are determined by the instants at which the first differential of the input signal and its inverse traverse a single reference level on one side of zero. Thus, for example, '0' to '1' transitions can be determined by the first differential going above the reference level and '1' to '0' transitions by the inverse of the first differential above the reference level.

In the preferred embodiment, the differentials are defined by the use of a centretapped inductance.

WHAT WE CLAIM IS:- 1. A circuit for shaping a received digital waveform representing a sequence of digital bits, the circuit comprising means for producing an output voltage and for switching that voltage between two levels in dependence upon the first differential with respect to time of said received waveform, the producing means comprising differentiating means for producing a first signal corresponding to said first differential and a second signal corresponding to the inverse of said

**WARNING** end of DESC field may overlap start of CLMS **.

Claims (7)

**WARNING** start of CLMS field may overlap end of DESC **. Line G of Figure 2 shows a second input signal R SYNC which defines when the clock signal should commence. Returning to Figure 1, 1 denotes the input which in use is connected to a television re ceiver to receive the complex video signal which, when Teletext is being received, has the form shown in line A of Figure 2. The input 1 is coupled by capacitor Cl to an amplifier comprising transistor TR1 and resistors R1 to R4. A differentiator is formed by an inductance L1, being a centre-tapped four turn coil by an inductance LI, being a centre-tapped four turn coil on a ferrite bead. The ends of inductance L1 are connected to the inverting inputs of respective com parators 2 and 3 which are provided by an integrated circuit IC1 (type 75 1t}7 B) ener gised from a +5 volts supply and from a 5 volts supply. The outputs of the com parators go to the set and reset inputs of a bistable circuit 4 formed by two NAND gates provided by an integrated circuit IC2 (type 74S00). One output of the bistable circuit is connected to an output DATA, the signal at which is shown in line F of Figure 2. That output and the RSYNC input go re spectively to the clock and preset mputs of a D-type bistable circuit 5 (type 74 S74). The clear input of circuit 5 is connected to a NAND gate also provided by circuit IC2) the inputs of which are connected to 5 volts via a resistor Rl 1 and to 0 volts via a switch 6. The Q output (line H of Figure 2) of circuit 5 is connected to the preset input of a J-K bistable circuit 7 ( of type 74 S112) forming the first stage of a three stage di vide-by-eight counter 7, 8 and 9 the output of which is connected to output CLOCK and delivers the signal shown in line I of Figure 2. Stage 8 is also i of type 74 S112 and stage 9 is of type 74 S74. The preset inputs of stages 8 and 9 and the J,K and clear inputs of stage 7 are fed from the 5 volts supply via a resistor R10. The clear inputs of stages 8 and 9 are fed from the Q output of circuit 5. The clock inputs of stages 7 and 8 are connected to a quartz oscillator of fre quency 55.5 MHZ. This oscillator comprises a crystal X1, resistor R9, NAND gate 10 OC2), capacitors C4 and C5 and a three turn air cored inductance L2. In operation, the incoming data (line A of FIgure 2) is first amplified by transistor TR1 and then differentiated by causing a current proportional to the input voltage to flow through inductance L1. Since induc tance L1 is centre-tapped two output volt ages are produced, one being the inverse of the other (lines B and C of Figure 2). These voltages are compared in comparators 2 and 3 with a reference voltage of about 200 mV set up by divider R6, R7. The output voltages of the comparators are shown in lines D and E of Figure 2. It will be seen that a transition from '1' to '0' in the input voltage causes the output voltage from comparator 2 to go low and a transition from '0' to '1' causes the output voltage from comparator 3 to go low.The outputs from the comparators are converted by the bistable circuit 4 to a shaped form (line F of Figure 2) of the voltage suitable for subsequent processing by logic circuitry. A 6.9375 MHz clock signal is also developed to enable subsequent logic circuitry to clock the regenerated data. With switch 6 open, the counter 7, 8, 9 is free running, as is appropriate for Viewdata. For Teletext, the switch is closed to apply a signal to circuit 5 in order to control the phase of the clock signal so that its clocking edges fall in the centre of the bit period (line F of Figure 2). In this mode, the R-SYNCH signal stops the counter and resets it to a predetermined state and the next leading edge of the DATA output signal removes the reset. The counter is reset to a state such that the first clock edge out of the counter occurs in the middle of the data bit which removed the reset. By changing the state to which the counter is reset, allowance can be made for propagation delays of the control bistable circuit 5 and the counter stages and for the asynchronous nature of the oscillator. Generally speaking, it will be seen that the invention provides means which produces an output digital waveform the high-low transitions of which are determined by the instants at which the first differential of the input signal and its inverse traverse a single reference level on one side of zero. Thus, for example, '0' to '1' transitions can be determined by the first differential going above the reference level and '1' to '0' transitions by the inverse of the first differential above the reference level. In the preferred embodiment, the differentials are defined by the use of a centretapped inductance. WHAT WE CLAIM IS:-

1. A circuit for shaping a received digital waveform representing a sequence of digital bits, the circuit comprising means for producing an output voltage and for switching that voltage between two levels in dependence upon the first differential with respect to time of said received waveform, the producing means comprising differentiating means for producing a first signal corresponding to said first differential and a second signal corresponding to the inverse of said

first differentisl, and comparator means for receiving said first and second signals and for comparing those signals with a single threshold level to determine the switching instants of the output voltage from one to the other and the other to the one of said two levels in dependence upon said first differential and its inverse respectively passing through said single threshold level in a given direction.

2. A circuit according to claim 1, wherein the differentiating means comprises an inductive circuit having a tapped inductance providing said first and second signals at respective sides of the tap of the inductance.

3. A circuit according to claim 1 or 2, wherein the comparison means comprises means operable to produce a third signal corresponding to excursions of the first signal with the same sign as, and of a magnitude above, said threshold level, and a fourth signal corresponding to excursions of the second signal with the same sign as, and of a magnitude above, said threshold level, and a bistable circuit having a set and a reset input connected to receive respective ones of the third and fourth signals.

4. A circuit according to any one of the preceding claims, in combination with a clock circuit for generating clock pulses.

5. A circuit according to claim 4 and comprising clock control means arranged to operate in dependence upon said output voltage to synchronise the clock pulses with the output voltage.

6. A circuit for shaping a received digital waveform substantially as hereinbefore described with reference to the accompanying drawings.

7. A television/logic interface circuit including a circuit according to any one of the preceding claims.