GB1603197A

GB1603197A - Electronic machine guard

Info

Publication number: GB1603197A
Application number: GB53956/76A
Authority: GB
Original assignee: Rigby Electronics Ltd
Current assignee: Rigby Electronics Ltd
Priority date: 1978-03-09
Filing date: 1978-03-09
Publication date: 1981-11-18

Description

(54) AN ELECTRONIC MACHINE GUARD (71) We, RIGBY ELECTRONICS LIMITED a British Company of Windmill Works, Station Road,- Swinton, M27 2BU do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement:- The present invention relates to an apparatus for electronically guarding a machine.

According to the present invention, there is provided apparatus for electronically guarding a machine comprising a series of transmitters, a series of receivers arranged to receive radiation from the transmitters, detector circuitry operative to detect when one or more beam paths from the transmitters to the receivers is blocked and means responsive to the detector circuitry for stopping the machine in the event of such blockage, the means responsive to the detector circuitry comprising duplicate output circuitry adapted for disposal in the power supply to the machine and a safety circuit operative to cross monitor the two branches of the output circuitry and interrupt the power supply should a difference in state thereof be detected.

An advantageous embodiment of the invention may incorporate any one or more of the following preferred features:- (a) The transmitters are constituted by an array of light emitting diodes.

(b) The receivers are constituted by an array of phototransistors.

(c) The detector circuitry comprises a missing pulse detector operative to detect when a pulse from a light emitting diode is not received by the corresponding phototransistor.

(d) The detector circuit comprises of a monostable and bistable circuit, the bistable being arranged to detect a change in state at the output of the monostable when a blockage occurs and to produce a signal at its output to operate the means responsive to the detector circuitry.

(e) Each branch of the means responsive to the detector circuitry comprises a relay having contacts adapted to be disposed in the power supply circuit to the machine.

(f) The transmitters and receivers are sequentially operated so that only when a given transmitter is transmitting is its corresponding receiver connected to provide a response.

(g) The transmitters and receivers are controlled by a clock coupled with a counter.

(h) A test source is provided operative to supply a test pulse to the detector circuitry to check the operation of this circuitry and the means responsive thereto.

In order that the invention may be more clearly understood, one embodiment of the invention will now be described, by way of example; with reference to the accompanying drawings, in which: Figure 1 shows a block circuit diagram of one form of electronic guard apparatus.

Figure 2 shows a possible physical arrangement of detector parts of the apparatus of Figure 1 on a machine to be guarded, and Figures 3 and 4 together show a complete circuit diagram corresponding to the block diagram of Figure 1.

Referring to the drawings, the apparatus basically comprises a clock oscillator 1 feeding counters 2. The outputs from the counters 2 lead respectively to an array 3 of light emitting diodes and a corresponding array 4 of photocells. The photocell array 4 output is connected via a de-multiplexor 5 to monostables 6, the output of the monostables are connected to bistable multivibrators 7, the output of the bistable multivibrators are connected to the output relay 8. "Fail safe" features are provided by the duplicated output circuits being cross-monitored by the safety circuit 9 which isolates the output relays 8 from the power supply if a difference in the two output relays 8 is detected.

The full circuitry of the block diagram of Figure 1 is shown represented in Figure 3 and the physical arrangement of certain parts of the circuit on a guarded machine is shown in Figure 2. Referring to Figure 2, part of a protective cage 15 around a machine is shown.

The cage defines an opening 16 through which the machines operator controls and oversees the operation of the machine. The array 3 of light emitting diodes is disposed at one side of the opening and the array 4 of photocells at the other. Rays of infra-red light are emitted sequentially by the light emitting diodes of the array 3 and are received, also sequentially, by corresponding ones of the photocell array 4. If the operator, or anyone else, places a hand, for example, in or through the aperture 16, at least one photocell will not receive the infra-red light emitted from the corresponding diode and the signal appropriate to that reception will therefore not be produced. The missing signal will then be detected and the machine power supply terminated.

The manner in which this absent signal is detected and the power supply terminated is as follows. Referring to Figures 1 and 3, the clock 1 is an oscillator comprising a conventional CMOS multivibrator running at 5 kilohertz and feeding the counters 2 which are seven stage ripple counters (integrated circuit IC1 on Figure 3 and IC14 on Figure 4) connected in such a way that they count to the fifth i.e. 2 = 32 and resets itself (this total counter count is chosen in dependence upon the number of light emitting diodes and photocells which are to be fed and this in turn is dependent upon the height of the opening 16 and the minimum required spacing of the diodes. In this case the spacing was chosen to be less than the minimum likely finger thickness of the machine operator).The output from the counter 2 (transmitter) is fed to the array 3 of light emitting diodes, the output R of counter 2 (receiver) is fed to the array 4 of photocells in such a way that each diode transmits infra-red light for half a clock period in turn. The outputs from the 32 phototransistors (reference PT in Figure 4) are demultiplexed by demultiplexer 5 to feed the monostables 6 in such a way that each photo transistor is only connected through to the common output line for a whole clock period during which its respective diode should be transmitting. This arrangement has two advantages.Firstly, the problem of a phototransistor providing a signal for light transmitted other than from its respective diode is avoided, and, secondly, as each phototransistor must switch on and off during its relevant clock cycle as the corresponding diode only transmits for half a clock cycle there is an inherent check on the operation of each phototransistor and light emitting diode.

The first three outputs of IC1 are fed to a binary to octal decoder (reference IC2 in Figure 3) which produces eight separate outputs, each of which go high in turn every eight pulses of the clock oscillator. These eight outputs are buffered by emitter followers EF which feed the transmitter board (referenced TB1 in Figure 4). The fourth, fifth and sixth outputs of IC1 are fed to a second binary to octal decoder (reference IC3 in Figure 3).

The outputs of IC3 are also buffered by transistors BT to form outputs A, B, C and D which also feed the transmitter board.

A separate counter and de-coder is provided for the receiver board, consisting of IC14 and IC15 of Figure 4. This counter is maintained in syncronism with IC1 of Figure 3 by being reset by the reset output of IC3.

The missing pulse detector comprises an operational amplifier (referenced Al in Figure 4) employed as a comparator and used to amplify multiplexed signals from the phototransistors PT of the receiver board (referenced RB in Figure 4). The output of the amplifier Al is fed into a CMOS gate G1 to obtain digital output signals normally consisting of a train of pulses at the same frequency as that of the clock oscillator 1. The output circuit from gate G1 to the output relays is duplicated for safety reasons, only one circuit will be described. The output from CMOS gate G1 is fed to a continuously retriggerable monostable 6, which is set to 1.5 times the clock period and as a result its output is held "set" so long as there is a continuous train of pulses at its input.Should a pulse be missing, however, the output of the monostable M1 will change for half a clock period before being "set" again by the next pulse. This change of output is fed to the reset input of a bistable circuit 7 whose output controls an output relay RL1 having contacts CRL1 disposed in the power supply circuit to the machine being guarded.

The bistable circuit is reset when a missing pulse is detected by the monostable circuit so de-energising the output relay. The bistable will remain reset until a start signal is received from the start/stop circuit 10.

The start/stop circuit 10 is connected to the foot switch through terminals 2 and 3.

When the foot switch is not pressed a missing pulse is generated by gates 4 and 5 which switch off one light emitting diode. This missing pulse is detected by the monostable circuits 6 and the output relays are deenergised. When the foot switch is pressed the missing pulse is removed and the bistables are set by the positive going edge on their clock inputs, the output relays are therefore energised, and will stay energised until a missing pulse is generated by either releasing the foot switch or interrupting any of the infra-red beams.

A "latch" facility is provided to allow the output relays to remain on when the foot switch is released. Terminals 4 and 3 are linked to use this facility. Terminal 4 goes positive when both output relays are energised and holds the foot switch input terminal 3 positive even when the foot switch is released.

The relays are unlatched by generating a missing pulse by either interrupting a beam or connecting terminal Tl 1 to terminal T12.

Safety Features.

The safety circuit 9 performs the following checks.

1. That whenever the foot switch is released, all output relay contacts return to their deenergised position. The output relay contacts are monitored by passing a high D.C. level 9v through them in the de-energised position.

This provides a high D.C. level at points A and B on the safety circuit in Figure 3. If any of the relay contacts do not return to their de-energised position, the high D.C.

level is not passed through to points A or B.

Points A and B are fed to the input of NAND gate 12a, the output of gate 12a will go to a high level if either A or B is at a low level.

The output of gate 12a is fed to one input of NAND gate 12b, the other input of gate 12b is fed from the start/stop circuit and goes to a high level when foot switch is released. The output of 12b therefore goes to low level if either point A or B is at low level when the foot switch is released. If 12b output goes low relay RL3 is energised and latched in, so directly de-energising relays RL1 and RL2. Relay RL3 can now only be de-energised by removing the power supply to the guard.

2. That both output relays are in the same state. Points A and B are fed to "exclusive OR" gate lla, the output of gate lla goes to a high if its inputs are not identical. Gate 11b inverts the output of gate lla to energise relay RL3 if point A and B are not the same.

3. If either output relay contacts have not returned to the de-energised position the other relay is prevented from energising. Points A and B are fed to the "date" inputs of the bistable associated with the other output circuit. This prevents the bistable being set by the start/stop circuit 10.

Four indicating light emitting diodes are provided to indicate: 1. Power on 2. Beams complete 3. Run 4. Tripped.

The power supply is of the conventional series regular type using a Darlington output transistor TD and incorporating a red light emitting diode DM to indicate when the power is on. A constant current switch CS supplies the light emitting diodes TB of the array 3 through terminal X.

Referring particularly to Figure 4, the connections of the light emitting diodes of the transmitter board TB and the phototransistors of the receiver board RB are shown. Four banks of eight light emitting diodes LED and four banks of eight phototransistors PT are provided (only one of each are shown). Each light emitting diode has an associated switching transistor ST whose emitter is connected to either terminal A, B, C or D depending on the bank number and whose base is connected to one of the '1' to '8' outputs of the binary to octal decoder No. 1 IC2 buffered by the emitter followers EF.The terminals A, B, C and D are the output terminals of the buffer transistor BT which are fed from the binary to octal decoder No. 2 IC3. The anodes of all the light emitting diodes are connected to a common line CL which is connected to terminal X of the constant current switch which is only switched on for each half clock period so that, as already mentioned, each LED only transmits for the first half of a relevant clock period.

On the receiver board RB, the output of each phototransistor PT is differentiated using a capacitive resistive combination CR, and the outputs multiplexed on to a common output line OL by means of an integrated circuit 1C6 provided for each bank.

WHAT WE CLAIM IS: 1. Apparatus for electronically guarding a machine comprising a series of transmitters, a series of receivers arranged to receive radiation from the transmitters, detector circuitry operative to detect when one or more beam paths from the transmitters to the receivers is blocked and means responsive to the detector circuitry for stopping the machine in the event of such blockage, the means responsive to the detector circuitry comprising duplicate output circuitry adapted for disposal in the power supply to the machine and a safety circuit operative to cross monitor the two branches of the output circuitry and interrupt the power supply should a difference in state thereof be detected.

2. Apparatus as claimed in Claim 1, in which the transmitters are constituted by an array of light emitting diodes.

3. Apparatus as claimed in Claim 1 or 2, in which the receivers are constituted by an array of phototransistors.

4. Apparatus as claimed in Claim 1, 2 or 3, in which the detector circuitry comprises a missing pulse detector operative to detect when a pulse from a transmitter is not received by the corresponding receiver.

5. Apparatus as claimed in any preceding claim, in which the detector circuit comprises a monostable sub-circuit and a bistable subcircuit, the bistable sub-circuit being arranged to detect a change in state at the output of the monostable sub-circuit when a blockage occurs and to produce a signal at its output to operate the means responsive to the detector circuitry.

6. Apparatus as claimed in any preceding claim, in which each branch of the means responsive to the detector circuitry comprises a relay having contacts adapted to be disposed in the power supply circuit of the machine.

7. Apparatus as claimed in any preceding claim, in which the transmitters and receivers are sequentially operated so that only when a

**WARNING** end of DESC field may overlap start of CLMS **.

Claims

**WARNING** start of CLMS field may overlap end of DESC **. or connecting terminal Tl 1 to terminal T12. Safety Features. The safety circuit 9 performs the following checks. 1. That whenever the foot switch is released, all output relay contacts return to their deenergised position. The output relay contacts are monitored by passing a high D.C. level 9v through them in the de-energised position. This provides a high D.C. level at points A and B on the safety circuit in Figure 3. If any of the relay contacts do not return to their de-energised position, the high D.C. level is not passed through to points A or B. Points A and B are fed to the input of NAND gate 12a, the output of gate 12a will go to a high level if either A or B is at a low level. The output of gate 12a is fed to one input of NAND gate 12b, the other input of gate 12b is fed from the start/stop circuit and goes to a high level when foot switch is released. The output of 12b therefore goes to low level if either point A or B is at low level when the foot switch is released. If 12b output goes low relay RL3 is energised and latched in, so directly de-energising relays RL1 and RL2. Relay RL3 can now only be de-energised by removing the power supply to the guard. 2. That both output relays are in the same state. Points A and B are fed to "exclusive OR" gate lla, the output of gate lla goes to a high if its inputs are not identical. Gate 11b inverts the output of gate lla to energise relay RL3 if point A and B are not the same. 3. If either output relay contacts have not returned to the de-energised position the other relay is prevented from energising. Points A and B are fed to the "date" inputs of the bistable associated with the other output circuit. This prevents the bistable being set by the start/stop circuit 10. Four indicating light emitting diodes are provided to indicate: 1. Power on 2. Beams complete 3. Run 4. Tripped. The power supply is of the conventional series regular type using a Darlington output transistor TD and incorporating a red light emitting diode DM to indicate when the power is on. A constant current switch CS supplies the light emitting diodes TB of the array 3 through terminal X. Referring particularly to Figure 4, the connections of the light emitting diodes of the transmitter board TB and the phototransistors of the receiver board RB are shown. Four banks of eight light emitting diodes LED and four banks of eight phototransistors PT are provided (only one of each are shown). Each light emitting diode has an associated switching transistor ST whose emitter is connected to either terminal A, B, C or D depending on the bank number and whose base is connected to one of the '1' to '8' outputs of the binary to octal decoder No. 1 IC2 buffered by the emitter followers EF.The terminals A, B, C and D are the output terminals of the buffer transistor BT which are fed from the binary to octal decoder No. 2 IC3. The anodes of all the light emitting diodes are connected to a common line CL which is connected to terminal X of the constant current switch which is only switched on for each half clock period so that, as already mentioned, each LED only transmits for the first half of a relevant clock period. On the receiver board RB, the output of each phototransistor PT is differentiated using a capacitive resistive combination CR, and the outputs multiplexed on to a common output line OL by means of an integrated circuit 1C6 provided for each bank. WHAT WE CLAIM IS:

1. Apparatus for electronically guarding a machine comprising a series of transmitters, a series of receivers arranged to receive radiation from the transmitters, detector circuitry operative to detect when one or more beam paths from the transmitters to the receivers is blocked and means responsive to the detector circuitry for stopping the machine in the event of such blockage, the means responsive to the detector circuitry comprising duplicate output circuitry adapted for disposal in the power supply to the machine and a safety circuit operative to cross monitor the two branches of the output circuitry and interrupt the power supply should a difference in state thereof be detected.

given transmitter is transmitting is its corresponding receiver connected to provide a response.

8. Apparatus as claimed in any preceding claim, in which the transmitters and receivers are controlled by a clock coupled with a counter.

9. Apparatus as claimed in any preceding claim, in which a test source is provided operative to supply a test pulse to the detector circuitry to check the operation of this circuitry and the means responsive thereto.

10. Apparatus for electronically guarding a machine substantially as hereinbefore described with reference to the accompanying drawings.

11. A machine provided with apparatus as claimed in any preceding claim.