GB1601942A - System for transmitting alarm information over telephone lines - Google Patents

Description

(54) A SYSTEM FOR TRANSMITTING ALARM INFORMATION OVER TELEPHONE LINES (71) We, the POST OFFICE, a British corporation established by Statute, of 23, Howland Street, London W1P 6HQ, do hereby declare the invention, for for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: This invention relates to systems in which alarm information is transmitted via telephone lines from subscribers' premises to one of a number of terminal stations and particularly relates to a processor for use in such a system.

The alarm system is of the type which has a plurality of transmitters which are located at subscribers' premises each transmitter being adapted to transmit signals indicative of the state of its associated alarm to a telephone line, said signals being in the form of modulated carrier waves, a plurality of receivers located at one or more local exchanges for receiving the transmitted signals the or each local exchange having a local processor which is arranged to sequentially scan the outputs of the receivers at its exchange and, when it detects a signal indicative of an alarm condition, to transmit a signal coded with information indicative of subscriber identity and alarm information destination to a central processor which is operative to direct the alarm information to one of a number of terminal stations.

Such an alarm system will be called a system of the kind referred to.

In accordance with one aspect of the present invention there is provided a local processor for a system of the kind referred to comprising a plurality of inputs each for connection via a telephone line to an alarm, means for continuously scanning said inputs, memory means for storing data indicative of the state of said alarms as represented by signals at said inputs sensed during the previous scanning sequence, means for comparing the state of each alarm with its state during the previous scanning sequence and means responsive to said comparing means detecting a change in the state of an alarm for transmitting a signal indicative of said alarm and its destination to an output which is for connection to the central processor of said system.

Each scanning means may be arranged to provide a plurality of scans during a scanning sequence, one of said scans constituting a check of the condition of highways provided in the processor. The memory may be a read/write memory.

The local processor may include an FDM/TDM transmitter for transmitting signals to the central processor and an FDM/TDM receiver for receiving signals from the central processor.

The invention will be described now by way of example only with particular reference to the accompanying drawings. In the drawings: Figure I is a block schematic diagram of an alarm signalling system; Figures 2A and 2B together are a block schematic diagram of a local processor used in the system of Figure 1: Figures 3A and 3B together are a block schematic diagram of a central processor used in the system of Figure 1. and Figure 4 is a block schematic diagram of terminal station equipment used in the system of Figure 1.

The signalling system shown in Figure 1 of the drawings is for transmitting alarm signals from a subscriber's premises via existing telephone lines to one of a number of terminal stations or display locations where the alarm information is required e.g. police, fire, security and plant maintenance organisations. The alarm information is transmitted over the telephone lines in encoded form and in such a manner that the signals do not interfere with normal speech signals on the telephone lines.

The system has transmitting equipment located in the subscriber's premises. Two types of transmitting equipment are indicated at 10 and 11. Each piece of transmitting equipment 10, 11 is connected via a local public telephone line 12 to an associated receiver 14, 15. The receivers are located in a local exchange and are connected to a processor 16 in that exchange. The transmitter 10 produces a carrier signal on which is modulated alarm information. The modulated carrier is received by the associated receiver which produces an output in the form of single bit binary information which is fed to the local processor 16.

The transmitter 10 is designed to operate with a single input from an alarm.

The transmitter 11 is designed to operate with two alarm inputs. The transmitter generates a carrier wave which is amplitude modulated by a combination of three tone frequencies which are switched in order to indicate the state of the alarm contact inputs.

The associated receiver responds to the modulated carrier and produces an output in the form of single bit binary information which is fed to the local processor 16.

The system has a number of local exchanges (only one is shown in Figure 1) each of which contains a number of receivers all connected to a single local processor 16. Each processor 16 is arranged to continuously scan the outputs of the receivers connected to it. Each local processor 16 is connected by a dedicated line to a central processor 20 disposed at a central exchange. When a local processor detects an alarm condition from one of the pieces of alarm equipment it compiles a message containing subscriber identity and destination for the alarm and transmits this message to the central exchange 20. The central processor at the central exchange receives this message and directs it via a private line to an appropriate one of a number of display points 21. The display points can be located at a fire headquarters, police headquarters, or a central display station.A connection can also be provided to a Post Office maintenance point.

Each receiver output is connected to an input of a local processor 16 (Figure 1). Each local processor 16 can accept a maximum of 1024 data inputs. The local processor can be split between two exchanges where circumstances dictate, two processors being connected in tandem. One processor is then known as the primary local processor and the other the secondary local processor. The construction of a local processor is shown in Figure 2.

The local processor shown in Figure 2 has an input stage consisting of 16 multiplexers 500 to which the data inputs from the receivers are connected in blocks of 16 indicated at 501.

The data output of each multiplexer 500 is connected to data highway 502 which leads to a highway test injection circuit 503. Each multiplexer 500 also has a connection to a data identity highway 504 which leads to the circuit 503. The input stage also includes 16 programmable-read-only memory circuits (PROM) 505 which can receive signals from the highway 504 and which have outputs to the circuit 503 via a control and display address highway 506. In the present embodiment the memory circuits 505 consist of mechanical on/off switches. The functions of the memory circuits 505 are: (a) to label the data inputs with the binary coded address of the terminal at which the message is to be displayed.

(b) to provide output signals which determine whether the data inputs are to be handled in pairs or blocks of 4.

(c) to determine if selected data is to be routed to both the display terminal nominated by the binary address of (a) and a Post Office maintenance terminal or to the nominated terminal only. For data required at only the Post Office maintenance terminal (e.g. fault and test data) the message is addressed to that terminal by a nominated binary address code.

The highway test injection circuit 503 has two output highways 508 and 509 leading therefrom, the highways 508 and 509 being connected to a primary secondary local processor changeover switch 510. The highway 508 is a data and identity highway and the highway 509 is a control and display address highway. Connected across the highways 508 and 509 are a highway test check circuit 512. a read/write memory 514 and a comparator 515. The memory 514 has a memory output 516 which is connected to the comparator 515.

The comparator 515 has a call output 518 which is connected to the switch 510.

The switch 510 has an output connected to a TDM/FDM transmitter 522 which is connected via a line 523 to the central processor 20. A return path from the central processor 20 is provided via a line 525 and aTDM/FDM receiver stage 526 to a switch 510A which is coupled to the switch 510. The switch 510A is connected to a TDM/FDM transmitter 528 which is connected to the secondary local processor. Signals received from the secondary local processor are fed via a receiver stage 530 to the switch 510.

The switch Sl0A has a first output 532 whose function will be described, a second output 533 which is a reset/release for a scan generator 535 and a third output 536 connected to the read/write memory 514. The scan generator 535 is connected'to the output 518 of the comparator 515. The scan generator 535 has three outputs 537, 538 and 539. The output 537 is connected to the highway 504 to control scanning of the input data and to the read/write memory 514 so that the memory can be scanned in synchronism with the input data; the output 538 is connected to the highway test injection circuit 503 and to the highway test circuit 512: and the output 539 is a priority control output which is connected to the comparator 515.

In use binary data input to the multiplexers 500 is scanned under the control of the comparator 515 and the priority control derived from the scan generator 535. In a complete scan sequence under the normal conditions when no alarm signals are transmitted a total of four scans are made. The first scan is used to check the various information highways, the second scan examines the first data bit of either the data blocks of two or blocks of four, the third scan examines the remaining data inputs, and the fourth scan examines those data inputs to be duplicated to the Post Office maintenance terminal.

The first scan or highway test sequence establishes that the data, data indentity and control and address highways 502, 504, 506, 508 and 509 are functioning correctly by injecting a test signal from the scan generator 535 at the highway test injection circuit 503 and checking the validity of the data in the highway test check circuit 512. During the subsequent three scans the data input multiplexers 500 and their associated PROM's 505 are scanned in sequence under the control of the scan generator 535. As each data input is switched to the data highway 502 it is compared with the contents of the read/write memory 514 which is scanned in synchronism with the data inputs. The contents of the read/write memory 514 are the data inputs from the previous scan sequence. Each data input is uniquely identified as a binary code during the same sequence and used to switch the multiplexers 500.

If no alarm signals are being transmitted the local processor continuously scans the data inputs. Whenever a difference is detected between the input data and the data contained in the memory 514, the comparator 515 stops the scan on that data input and signals a call to the changeover switch 510.

This call signal locks the changeover switch 510 onto the primary local processor and loads data. call and address information into the TDM/FDM transmitter 522 for onward transmission to the central processor 20. When the central processor 20 has examined the message signals, control signals are returned to the local processor. If the message is accepted bv the central processor 20 the read/write memory 514 is up-dated to the current state of the data input being examined. The scan generator is then reset to the first of its scans in a scan sequence and is released and the call signal removed. This releases the changeover switch 510 which can then accept another message from either the primary or secondary processors.

If however the message is not accepted by the central processor 20 the return signal on line 525 only releases the scan generator and removes the call signal. The memory 514 is not up-dated and since the scan generator is not reset it continues to examine the remaining data inputs in sequence. The next data change accepted by the central processor then initiates a highway test followed by re-examination of the data inputs on the second scan of the scan sequence.

Two forms of testing are available in the local processor. The first test is the highway test which is local to each processor and tests that each line in each highway can be switched from logic 1 to logic 0 when the multiplexers 500 and PROM'S 505 are inhibited. If the highway test fails further scans of data are inhibited and a local fault alarm is outputted from the processor. This alarm condition is also passed to the Post Office maintenance terminal bv the TDM/FDM transmission arrangement.

The second test is a remote test which is generated at the Post Office maintenance terminal and signalled via the central processor to all local processors. It generates an alarm (logic 1) data input at a specified input to a selected local processor by way of the switch 510A and output line 532 from this switch. The local processor responds and signals this alarm to the Post Office maintenance terminal. Correct receipt of this message initiates transmission of a clear (logic 0) data signal to the local processor which should in turn be signalled back to the Post Office maintenance terminal. Provision is made to access each local processor in turn either automatically or by manual operation in order to perform testing or local control functions including customer interrogation.

Electrical security in the local processors is achieved by diversification of power supplies.

The arrangement is such that each power unit feeds a limited number of receiver units and their associated multiplexers 500. Failure of one power unit is signalled via a separately powered data multiplexer to the Post Office maintenance terminal and does not affect the remaining inputs to the local processor. Failure of power to the common equipment is catastrophic. This is indicated at the central processor 20 as a failure of the TDM/FDM link to the local processor. Duplicated transmission paths are provided between local and central processors with automatic changeover and alarm facilities and the TDM/FDM links have both parity and signal level monitors. The restoration of a power supply can only be achieved by following a prescribed routine which ensures that false alarm conditions are not generated when power is re-applied.The circuits are mounted on plug-in units all of which incorporate a U-link connection whereby removal of any item causes an alarm to be outputted.

The operation of the secondary local processor is substantially identical with that of the primary local processor, the exception being the changeover switch operation. Instead of feeding a changeover switch, the data, call and address information is fed directly to a TDM/FDM transmission link the output of which is connected to the changeover switch in the primary local processor. Information returned from the central processor first passes through the changeover switch and is then retransmitted to the secondary local processor.

The changeover switch is held locked to the secondary local processor until the call signal is removed.

Each local processor is connected to the central processor 20 (see Figure 1). A maximum of 30 local processors can be connected to the central processor. The function of the central processor 20 is to identify call signals originating from the local processors or display points, to route the message to the display termination identified by the binary address code, check that the display termination is free to accept the message and return control information to the local processor originating the call. The central processor is shown in block schematic form in Figure 3.

Referring to Figure 3 the central processor comprises a plurality of local processor terminations 550 (only one shown in Figure 3), a local processor termination being provided for each local processor. Each local processor termination comprises a TDM/FDM receiver 552 connected to receive signals from the local processor. The receiver 552 is connected to a test injection and gate circuit 553. The circuit 553 has data, address and control outputs 554, 555, 556 which are respectively connected to a data highway 558, an address highway 559 and a control highway 560. A remote test highway 562 is connected via a line 563 to a TDM/FDM transmitter 564 in the local processor termination 550. The test injection and gate circuit 553 is connected by a reset and release line 566 and a memory up date line 567 to the transmitter 564.A remote test generator 569 is connected to the remote test highway 562 and is operable by means of a key pad 570. The key pad 570 and remote test generator may be located at a Post Office maintenance terminal.

It will be appreciated that all other local processor terminations are connected to the highways 558. 559, 560 and 562 in a similar manner. This is indicated generally at 572. The control data and address highways 560. 558 and 559 are connected by control data and address lines 574, 575 and 576 to a display termination 578. Only one display termination is shown in Figure 8 but a plurality of other display terminations may be connected to the highways 558, 559, 560 as indicated at 580. A maximum of 30 display terminations can be connected to the main highways. Each display termination has a test, check and store 582 which is connected to the lines 574, 575, 576. The test. check and store has data and call outputs connected to a TDM/FDM transmitter 584 the output of which is connected by a line 585 to a display point.The test check and store 582 has a local test input 586 and a reset input 587 which is connected to an FDM/TDM receiver 588 which receives signals returned from the display point along line 585. The receiver 588 is also connected to the transmitter 584. The receiver 588 has call and address outputs which are connected to a test, injection and gate circuit 589 which has a reset/repeat input, and data and address outputs connected respectively to the lines 574, 575 and 576. The gate 589 has a local test input 591 and an enable input 592. The gate 589 also has a data input from the data output of the store 582 and a control output which is connected to a reset input on the test, check and store 582.

The central processor also includes a test arrangement consisting of a highway test check circuit 595 connected by data and address lines 596 and 597 to the data and address highways. The output of the circuit 595 is connected to a scan generator 599 which in turn is connected to a test sequence generator 600. The scan generator 599 also receives outputs from highway test check circuits of other terminations indicated at 601. Thus the scan generator 599 and test sequence generator 600 are common for all the display terminations.

The operation of the central processor is cyclic, the operation of the scan generator 599 being stopped only under fault conditions. All messages are therefore given equal priority.

In use information received from a local processor is presented to the receiver 552 and gate 553 of the corresponding local processor termination from the output of the FDM/TDM link. The arrangement is such that the terminations 550 are enabled sequentially by means of signals derived from the scan generator 599. The scan generator 599 also generates local test control signals and a binary code to identify the local processor termination being examined. The enable signal generated by the generator 599 initially causes the gate 553 to generate test signals which are passed to the data and address highways 558 and 559. The test signal validity is checked by the local test check circuit 582 associated with the display termination 578 and a separate check circuit 595 connected directly to the highways. Then the gate input is examined to see if a call signal is present.If a call signal is present the data and address information is switched onto the highways for the remaining period of the enable signal.

Each display termination test, check and store 582 is programmed to recognise a specific address code. The display termination which recognises the address code received from the local processor then tests to see if the store is empty or full. If the store is empty the data is loaded into the store and control signals are returned to the local processor termination which then signals memory up data and reset/release to the local processor. A circuit within the local processor termination 550 ensures that once a call signal has been identified by the central processor it will on subsequent scans be ignored until it has been removed and re-established by the local processor. This is to ensure that the same message is not repeatedly loaded into the display termination 578.

Should the store 582 be full control information is returned to the local processor termination which then signals only release to the local processor and a flag is set in the store to indicate that a further message is waiting to be displayed. With the data loaded into the display termination store 582 the data together with a call signal is transmitted via the TDM/FDM link 584 to the display point. When the display point has recorded the message, an acknowledgement signal is returned along line 585 to the receiver 588 in the display termination. A reset signal is then applied from the receiver 588 to the reset input 587 of the store to clear the store. The display is also subsequently cleared.

If it is required to transfer a message to a second display point the address of the selected new display and a call signal are returned to the display termination 578 in place of the acknowledgement signal. The data output from the store 582 is hard wired to the input of a gate 589 which performs in a similar manner to a local processor termination gate. When this gate is supplied with call and address signals it is enabled in the same manner as a local processor termination gate and passes information onto the data and address highways 558, 559. If the second display termination is free the message is loaded into the new store and control signals return to reset the original display store and cancel the call and address signals for the original display point.If the second display termination is full a control signal is returned to the original display point to regenerate the call signal.

The testing facilities of the central processor will now be described. A local test which is operative during the first part of an enable period inhibits normal operation of the gates and causes them to apply logic 1 followed by logic 0 to each line of each highway. The test check circuits are enabled during this period and any line which fails to signal the logic levels in the correct sequence at the correct time causes the test check circuits 595 and/or the test check and store 582 to output local alarm signals and stop further input gates being enabled by the scan generator 599.

Remote testing of the local processors covers the operation of most parts of the central processor. Each display point can also generate a test message to a predetermined local processor which will check the operation of that display point central processor termination together with the display point itself.

Power supply arrangements for the central processor are similar to those in the local processor. A failure of one power supply (other than that feeding the common equipment) only inhibits one part of the system. All plug-in items incorporate a U-link connection so that the removal of any item causes an alarm output.

Figure 4 illustrates the functional blocks of a display point 21. The display point is connected to receive TDM/FDM signals from the central processor via line 585. The display point has an FDM/TDM receiver 610 which receives the signals from the central processor.

The receiver 610 has a data output line 611 which is connected to the data inputs of a visual display 612 and a printer 614. The receiver also has a call output 616 which is connected to the load input of the visual display 612 the load input of the printer 614 the set input of a visual alarm 618 and the set input of an audible alarm 619. The receiver 610 also has an output to a message waiting circuit 620. The receiver has acknowledge and control outputs indicated generally at 622 which are connected to the reset input of the display 612, the print input of the printer 614 the reset input of the alarm 618 and the reset input of the alarm 619. A local test circuit 624 is connected to the visual display 612.The line 622 from the receiver 610 is connected to the transfer reset/repeat input of an acknowledge and transfer control circuit 626 which also has an enable input connected to the visual alarm 618.

The circuit 626 also receives signals from a transfer address PROM 628. The acknowledge and transfer control circuit 626 has acknowledge transfer address and call outputs which are connected to a TDM/FDM transmitter 630 the output of which is connected to the line 585 to the central processor. The transmitter 630 also has an input from a system test circuit 631.

In operation on receipt of a call signal from the central processor, data is loaded into the visual display 612 and the printer (if present) 614. The visual alarm 618 also responds by flashing and the audible alarm circuit 619 emits an audible alarm to attract the attention of an operator at the display point. The visual alarm also enables the acknowledge and transfer control circuit 626. When the action required by the message has been decided by the operator either the acknowledgement or one of the transfer keys of the circuit 626 is operated. Operation of the acknowledgement key causes the message stored in the central processor 20 to be cancelled and when returned to the display point the acknowledgement signal cancels the visual display, audible and visual alarms and causes the printer to print the received message.Operation of one of six interlocked transfer keys associated with the circuit 626 signals call and transfer address to the central processor and removes the audible alarm. The transfer address is read from the PROM 628 which is housed within the visual display. The central processor treats the call in the same way as a local processor call. If the central processor 20 is able to load the message into the new display store a control signal is returned to the display point which cancels the visual display, visual alarm and call and address and causes the printer to operate. If the new display store is full the control signal returned to the display point causes the call signal to be regenerated.Should the transfer fail (for example because the second display point is faulty) the message can still be accepted at the originating display by operating the acknowledgement key of the circuit 626. The message can only be transferred once by any one display point. The second display point can however re-transfer the message if required. Although in practice only six transfer keys are provided with the circuit 626 any of the other display points may be addressed and the number of transfer keys increased if required.

Two forms of testing facility are available at the display point. The first is a local test controlled by a circuit 624. Operation of a local test key causes the visual display 612 to step all digits in parallel from 000000 to 999999 at approximately 1 second intervals. This is to check that all seven segments display elements are operating correctly. The key also lights all indicator lamps while it is depressed.

The second is a system test and this generates a test message at a nominated local processor. This is controlled by the system test circuit 631. Correct receipt of the message at the display point provides an overall check of local and central processors and the display equipment. Both test functions are available at any time when the display point is not in receipt of a message.

Turning now to the message assembly and display format, a typical message from a local processor 16 programmed to examine input data in a block of four bits would be 231244 ABLP The two most significant digits of this message indicate the identity of the local processor from which the message originates and are derived from the scan generator in the central processor 20. The next most significant digit indicates primary or secondary processor and is derived from the position of the local processor changeover switch. The three least significant digits define the position of the data inputs on the data multiplexer 500 and are derived from the local processor scan generator. The four alpha characters relate to the four data bits being examined. An alarm condition is shown as the alpha character and the clear conditions as a bar.

For a message where only two data bits are examined the alpha characters B and P are not displayed. Various options are available in the printer mechanism but all give the same display format.

231244 ABLP 35 11.46 ACK 11.48 (1) (2) (3) (4) (5) Item (1) is the message identity and alarm condition.

Item (2) is a running message log up-dated by one for each message received and reset to 00 at 24.00.

Item (3) is the time at which the message was received at the display terminal.

Item (4) is an indication that the message has been locally acknowledged. For various transfer conditions separate alpha numerical codes are displayed.

Item (5) is the time at which the acknowledgement (or transfer) was effected.

The printer 614 incorporates a self contained real time clock but provision is made to inject external 1 minute pulses if required.

It will be appreciated that several options are available at display points. Although the arrangement shown in Figure 9 has only one display equipment provision is made to connect two terminals in parallel. The modes of operation are a) both working b) one working one stand by.

Interlocks prevent both units being switched to stand by and should the working unit be disconnected the remaining device switches to the working mode. Disconnecting both units (or one where no stand by unit is provided) signals a fault condition to the central processor 20. The display may be either visual only or visual and printer. Alternatively the FDM/TDM system may be interfaced to a computer.

Reference is made to our copending application No. 9246/77 (Serial No. 1601941) from which the present application has been divided and to application No. 8020841 (Serial No.

1601943) which is also divided from that application. Application No. 9246/77 (Serial No.

16001941) describes and claims a system for transmitting alarm information from a subscriber's premises to one of a number of terminal stations via telephone lines.

Application No. 8020841 (Serial No. 1601943) describes and claims a central processor for use in such an alarm system.

WHAT WE CLAIM IS: 1. A local processor for a system of the kind referred to comprising a plurality of inputs each for connection via a telephone line to an alarm, means for continuously scanning said inputs, memory means for storing data indicative of the state of said alarms as represented by signals at said inputs sensed during the previous scanning sequence, means for comparing the state of each alarm with its state during the previous scanning sequence and means responsive to said comparing means detecting a change in the state of an alarm for transmitting a signal indicative of said alarm and its destination to an output which is for connection to the central processor of said system.

2. A local processor as claimed in claim 1 wherein said scanning means is arranged to provide a plurality of scans during a scanning sequence, one of said scans constituting a check of the condition of highways provided in the processor.

3. A local processor as claimed in claim 1 or claim 2 wherein said memory is a read/write memory.

4. A local processor as claimed in any one of claims 1 to 3 wherein said local processor includes an FDM/TDM transmitter for transmitting signals to the central processor and an FDM/TDM receiver for receiving signals from the central processor.

5. A local processor substantially as hereinbefore described with reference to and as shown in the accompanying drawings.

**WARNING** end of DESC field may overlap start of CLMS **.

Claims (5)

1. **WARNING** start of CLMS field may overlap end of DESC **.

   The printer 614 incorporates a self contained real time clock but provision is made to inject external 1 minute pulses if required.

   It will be appreciated that several options are available at display points. Although the arrangement shown in Figure 9 has only one display equipment provision is made to connect two terminals in parallel. The modes of operation are a) both working b) one working one stand by.

   Interlocks prevent both units being switched to stand by and should the working unit be disconnected the remaining device switches to the working mode. Disconnecting both units (or one where no stand by unit is provided) signals a fault condition to the central processor 20. The display may be either visual only or visual and printer. Alternatively the FDM/TDM system may be interfaced to a computer.

   Reference is made to our copending application No. 9246/77 (Serial No. 1601941) from which the present application has been divided and to application No. 8020841 (Serial No.

   1601943) which is also divided from that application. Application No. 9246/77 (Serial No.

   16001941) describes and claims a system for transmitting alarm information from a subscriber's premises to one of a number of terminal stations via telephone lines.

   Application No. 8020841 (Serial No. 1601943) describes and claims a central processor for use in such an alarm system.

   WHAT WE CLAIM IS: 1. A local processor for a system of the kind referred to comprising a plurality of inputs each for connection via a telephone line to an alarm, means for continuously scanning said inputs, memory means for storing data indicative of the state of said alarms as represented by signals at said inputs sensed during the previous scanning sequence, means for comparing the state of each alarm with its state during the previous scanning sequence and means responsive to said comparing means detecting a change in the state of an alarm for transmitting a signal indicative of said alarm and its destination to an output which is for connection to the central processor of said system.
2. 2. A local processor as claimed in claim 1 wherein said scanning means is arranged to provide a plurality of scans during a scanning sequence, one of said scans constituting a check of the condition of highways provided in the processor.
3. 3. A local processor as claimed in claim 1 or claim 2 wherein said memory is a read/write memory.
4. 4. A local processor as claimed in any one of claims 1 to 3 wherein said local processor includes an FDM/TDM transmitter for transmitting signals to the central processor and an FDM/TDM receiver for receiving signals from the central processor.
5. 5. A local processor substantially as hereinbefore described with reference to and as shown in the accompanying drawings.